JP2002108494A - クロック同期回路及び方法 - Google Patents

クロック同期回路及び方法

Info

Publication number
JP2002108494A
JP2002108494A JP2001217526A JP2001217526A JP2002108494A JP 2002108494 A JP2002108494 A JP 2002108494A JP 2001217526 A JP2001217526 A JP 2001217526A JP 2001217526 A JP2001217526 A JP 2001217526A JP 2002108494 A JP2002108494 A JP 2002108494A
Authority
JP
Japan
Prior art keywords
clock signal
delay
delayed
reference clock
synchronization circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001217526A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002108494A5 (enExample
Inventor
Young Tan Kyamu
キャム・ヤング・タン
Waa Roo Teiamu
ティアム・ワー・ロー
Teck Chy Allen Lim
テック・チェ・アレン・リム
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of JP2002108494A publication Critical patent/JP2002108494A/ja
Publication of JP2002108494A5 publication Critical patent/JP2002108494A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Pulse Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
JP2001217526A 2000-07-18 2001-07-18 クロック同期回路及び方法 Pending JP2002108494A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/618,405 US6831490B1 (en) 2000-07-18 2000-07-18 Clock synchronization circuit and method
US09/618405 2000-07-18

Publications (2)

Publication Number Publication Date
JP2002108494A true JP2002108494A (ja) 2002-04-10
JP2002108494A5 JP2002108494A5 (enExample) 2008-07-03

Family

ID=24477556

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001217526A Pending JP2002108494A (ja) 2000-07-18 2001-07-18 クロック同期回路及び方法

Country Status (2)

Country Link
US (1) US6831490B1 (enExample)
JP (1) JP2002108494A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112202446A (zh) * 2019-07-08 2021-01-08 北京三中科技有限公司 一种相位同步装置和方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9164134B2 (en) 2012-11-13 2015-10-20 Nvidia Corporation High-resolution phase detector
US9471091B2 (en) 2012-11-28 2016-10-18 Nvidia Corporation Periodic synchronizer using a reduced timing margin to generate a speculative synchronized output signal that is either validated or recalled
CN112350718B (zh) * 2020-09-25 2023-06-27 苏州华兴源创科技股份有限公司 时钟源电路、机箱及多机箱级联系统

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09186682A (ja) * 1995-12-28 1997-07-15 Nec Eng Ltd クロック信号調整回路
JPH10327055A (ja) * 1997-05-07 1998-12-08 Lg Semicon Co Ltd 遅延ロックド回路

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5118975A (en) * 1990-03-05 1992-06-02 Thinking Machines Corporation Digital clock buffer circuit providing controllable delay
JP3232351B2 (ja) * 1993-10-06 2001-11-26 三菱電機株式会社 デジタル回路装置
US5638410A (en) * 1993-10-14 1997-06-10 Alcatel Network Systems, Inc. Method and system for aligning the phase of high speed clocks in telecommunications systems
US5645519A (en) * 1994-03-18 1997-07-08 Jai S. Lee Endoscopic instrument for controlled introduction of tubular members in the body and methods therefor
US6346839B1 (en) * 2000-04-03 2002-02-12 Mosel Vitelic Inc. Low power consumption integrated circuit delay locked loop and method for controlling the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09186682A (ja) * 1995-12-28 1997-07-15 Nec Eng Ltd クロック信号調整回路
JPH10327055A (ja) * 1997-05-07 1998-12-08 Lg Semicon Co Ltd 遅延ロックド回路

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112202446A (zh) * 2019-07-08 2021-01-08 北京三中科技有限公司 一种相位同步装置和方法

Also Published As

Publication number Publication date
US6831490B1 (en) 2004-12-14

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