JP2002107760A - Method for manufacturing liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent defects caused by particles in an interlayer insulating film and to improve the yield. SOLUTION: The interlayer insulating film is formed in two steps. After a first interlayer insulating film 13 is formed, brush cleaning is implemented by using a cathode water in the process prior to the formation of a second interlayer insulating film 14. Thereby, leaking caused by particles in the interlayer insulating film can be prevented and the yield can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a liquid crystal display device.

[0002]

2. Description of the Related Art In recent years, polycrystalline silicon and amorphous silicon can be formed on a light-transmitting insulating substrate by a CVD method (Chemical Vapor Deposition) or the like. Is being actively conducted.

[0003] Starting from application as a switching element of a pixel in a display section, application to a driving circuit (mainly composed of a CMOS transistor) for operating a switching element in a polycrystalline silicon film has also been put to practical use. It is getting.

Polycrystalline silicon is converted to a TFT (Thin Film Tran)
A conventional method of manufacturing a CMOS transistor used for an active layer of a sistor will be described.

As shown in FIG. 4A, a silicon nitride film 2 and an amorphous silicon film 3 are formed on a light-transmitting insulating substrate 1 by a CVD method. Thereafter, in order to reduce the amount of H in the amorphous silicon film 3, an annealing process is performed in an N2 atmosphere.

As shown in FIG. 4B, an amorphous silicon film 3 is instantaneously melted by using an excimer laser, and a polycrystalline silicon layer 4 is grown.

[0007] As shown in FIG.
Is patterned by CDE (Chemical Dry Etching) to form an island-shaped polycrystalline silicon film 4b for an n-type TFT and an island-shaped polycrystalline silicon film 4a for a p-type TFT.

As shown in FIG. 4D, a gate insulating film 5 is deposited on the entire surface by using a CVD method.

As shown in FIG. 4E, a metal film is deposited on the gate insulating film 5 by sputtering, and the RIE (Reac
The gate electrodes 6a and 6b are formed by patterning using a tive ion etching method.

As shown in FIG. 4F, the gate electrodes 6a, 6
Using P as a mask, P ions are implanted into the polycrystalline silicon films 4a and 4b in a self-aligned manner. As a result, FIG.
As shown in (g), the polycrystalline silicon film 4b for the n-type TFT
Source and drain regions 4b excluding the channel region in FIG.
P is introduced into the source and drain regions 4a1 of the p-type TFT polycrystalline silicon film 4a at a low concentration.

After applying a resist on the entire surface, PEP
(Photo Engraving Process)
As shown in (1), a resist film 11 covering the entire upper portion of the p-type TFT and a resist film 10 covering a region slightly larger than the gate electrode 6b of the n-type TFT are formed. And
Using the resist films 10 and 11 as masks, both end regions 4b2 of the source / drain regions 4b1 in the n-type TFT are
P ions are implanted at a high concentration. After that, the resist film 1
0 and 11 are removed by an ashing method.

As shown in FIG. 5B, a resist is again applied to the entire surface, and a resist film 12 covering the entire n-type TFT region is formed by a PEP process. Using the resist film 12 as a mask, the source and drain regions 4a of the p-type TFT
1 is doped with B at a high concentration. After that, the resist film 12 is removed.

As shown in FIG. 5C, an interlayer insulating film 20 is deposited on the entire surface by using the CVD method.

As shown in FIG. 5D, a contact hole 16 is formed in the interlayer insulating film 20.

As shown in FIG. 5E, a metal film is deposited on the whole so as to fill the contact hole 16 and is patterned to form a signal line 17, thereby completing a CMOS transistor.

[0016]

However, the conventional manufacturing method described above has a problem that the interlayer insulating film 20 is easily affected by particles when the interlayer insulating film 20 is formed, and a leak failure occurs frequently in the interlayer insulating film 20. .

The present invention has been made in consideration of the above circumstances, and it is an object of the present invention to provide a method of manufacturing a liquid crystal display device that prevents defects caused by particles and contributes to an improvement in yield. And

[0018]

According to a method of manufacturing a liquid crystal display device according to the present invention, a step of forming a semiconductor layer on an insulating substrate and forming an interlayer insulating film on the insulating substrate on which the semiconductor layer is formed are provided. The step of forming the interlayer insulating film includes the steps of forming the interlayer insulating film in n steps, forming the j-th interlayer insulating film, and then forming the j + 1-th interlayer insulating film. The method is characterized in that the step includes a step of cleaning the j-th interlayer insulating film. In the washing step, washing may be performed using cathode water and a brush.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. As shown in FIG. 1A, a silicon nitride film 2 having a thickness of, for example, 300 nm and an amorphous silicon film having a thickness of, for example, 50 nm are formed on a light-transmitting insulating substrate 1 by a CVD method. The film 3 is formed by a CVD method. Thereafter, in order to reduce the amount of H in the amorphous silicon film 3, an annealing process is performed in an N2 atmosphere. For example, by performing annealing at 500 ° C. for 1 hour, the hydrogen concentration in the amorphous silicon film 3 can be reduced to 0.1 atom% or less.

Thereafter, the insulating substrate 1 is used to reduce dust and the like.
Wash. At this time, by cleaning the insulating substrate 1 using, for example, ozone water, an oxide film layer is formed on the surface of the amorphous silicon film 3 in addition to the natural oxide film.

Thereafter, ion implantation without a mass separation function is performed, and a desired concentration of B ions is added to the amorphous silicon film 3.
Inject into. The injection conditions at this time are, for example, acceleration voltage 1
0 keV, dose 7E11 / cm2, gas concentration 5%
/ H2 gas dilution.

The B ions implanted at this time penetrate the oxide film near the surface and are almost entirely implanted into the amorphous silicon film 3. Thereafter, the oxide film region near the surface of the amorphous silicon film 3 is completely removed using, for example, a hydrofluoric acid-based solution.

As shown in FIG. 1B, the amorphous silicon film 3 is instantaneously melted and polycrystallized by using an excimer laser, and the polycrystalline silicon layer 4 is grown. By this processing, B that has been implanted into the amorphous silicon film 3 becomes Si
Is melted in the insulating substrate 1. Therefore, this polycrystalline silicon film 4 becomes a film containing B.

The amount of B in the polycrystalline silicon film 4 is determined by controlling the ion implantation device. However, when ion implantation is performed using an ion implantation apparatus having no mass separation function, the oxide film on the surface layer of the amorphous silicon film 3 functions as a protective film. Therefore, by removing this oxide film layer before the excimer laser process, it is possible to perform polycrystallization without taking in B, and other contaminants such as C, N, and O caused by the environment into the film. Can be. Here, the oxide film layer to be removed by washing before the polycrystallization step is, for example, 50 to 10
0 °, and the amorphous silicon film removed at the same time is 10 °.
About Å.

As shown in FIG. 1C, the polycrystalline silicon film 4
After covering the surface of the portion corresponding to the active region and the conduction region in FIG. 1 with a resist film (not shown), patterning is performed by CDE (Chemical Dry Etching) to form an island-shaped polycrystalline silicon film for an n-type TFT. 4b
And an island-shaped polycrystalline silicon film 4a for a p-type TFT. After that, the resist film is removed.

As shown in FIG. 1D, a gate insulating film 5 is deposited on the entire surface by using a thermal CVD method. here,
The gate insulating film 5 is made of a silicon oxide film, and its preferable thickness is, for example, about 100 nm or less.

As shown in FIG. 1E, a metal film is deposited on the gate insulating film 5 by sputtering to a thickness of, for example, 200 nm, and is patterned by RIE (Reactive Ion Etching) to form gate electrodes 6a and 6b. I do. The metal film may be, for example, an alloy of molybdenum and tungsten, and has a thickness of, for example, 250 nm.

As shown in FIG. 1F, the gate electrodes 6a, 6
P is ion-implanted into the polycrystalline silicon films 4a and 4b in a self-aligned manner using b and a resist film for patterning (not shown) as a mask.

As a result, as shown in FIG.
Source and drain regions 4b1 excluding the channel region in the polycrystalline silicon film 4b for FT, and source and drain regions 4a in the polycrystalline silicon film 4a for p-type TFT
1, P is introduced at a low concentration. Here, B is introduced into the channel layer, for example, at about 3E11 / cm2 to 2E12 / cm2. Generally, when an impurity is implanted at a low concentration into a channel layer, an ion implantation apparatus having no mass separation function is used. However, in order to further enhance the controllability of the implantation, an ion implantation apparatus equipped with a mass separation function may be used. Thereafter, the resist film is removed by an ashing method.

After applying the resist on the entire surface, the PEP
According to the process, as shown in FIG.
And a resist film 10 slightly larger than the gate electrode 6b of the n-type TFT, for example, about 2 μm larger on one side. Then, using the resist films 10 and 11 as a mask, P ions are implanted at a high concentration into both end regions 4b2 of the source / drain regions 4b1 in the n-type TFT. Thereafter, the resist films 10 and 11 are removed by an ashing method. In P ion implantation, P
Using H3 gas, the injection conditions are, for example, 1E15 / cm2, 70
It may be keV.

Thereafter, the resist film is removed by an ashing method, and P ions are implanted under the conditions of, for example, 3E13 / cm 2 and 80 keV. In the n-type TFT, the source / drain region 4b2 in which P is heavily doped and the P / P
Is implanted to form source and drain regions 4b1. The low-concentration region 4b1 lowers the electric field intensity near the drain end, reduces the leak current, and has the effect of preventing the TFT from deteriorating.

As shown in FIG. 2B, a resist is applied to the entire surface again, and a resist film 12 covering the entire n-type TFT region is formed by a PEP process. Using the resist film 12 as a mask, the source and drain regions 4a of the p-type TFT
1 is doped with B at a high concentration. In this ion implantation, B2H6 gas is used, and the dose and the acceleration voltage may be, for example, 2E15 / cm2 and 70 keV. Note that the same ion implantation apparatus as used when B is implanted at a low concentration in the previous step can be used. Thereafter, the resist film 12 is removed by an ashing method. After this, 500 times in N2 atmosphere
Annealing is performed at 1 ° C. for 1 hour. This process is performed to activate the implanted impurities.

Next, unlike the conventional method, an interlayer insulating film is formed at least twice. The total thickness is, for example, 66
It is set to 0 nm.

As shown in FIG. 2C, the plasma C
A first interlayer insulating film 13 is deposited on the entire surface by using the VD method. Here, a first interlayer insulating film 13 is formed,
Before forming the interlayer insulating film 14 as a layer, brush cleaning is performed using cathode water at a rotation speed of, for example, 200 rpm.

Subsequently, as shown in FIG. 2D, a second interlayer insulating film 14 is formed by a plasma CVD method to form an interlayer insulating film 15 having a total thickness of 660 nm.

Subsequently, regions other than the contact portions on the source and drain regions are covered with a resist film (not shown) and, for example, an ammonium fluoride solution is used as shown in FIG.
As shown in (e), a contact hole 16 is opened in the interlayer insulating film 20. Thereafter, the resist film is stripped.

As shown in FIG. 2F, a metal film is entirely deposited by sputtering so as to fill the contact hole 16 and is patterned to form a signal line 17, thereby completing a CMOS transistor. Here, the metal film is, for example, Mo, Al, Mo in order of 50 nm, 40 nm.
It may be formed to a thickness of 0 nm or 50 nm. In the device manufactured through the above steps, defects of the interlayer insulating film due to particles are prevented.

In the above embodiment, after the first interlayer insulating film 13 is formed, the first interlayer insulating film 13 is formed at 200 rpm using cathode water.
Brush cleaning is performed at a rotational speed of m. The result of examining that the number of particles is reduced by this cleaning process will be described.

The following are seven types of cases B1 to B7 in which the type of cleaning water and the number of rotations and the transport speed of the brush are changed.
The condition of B7 is shown, and FIG. 3 shows the number of particles in each case. Case B1: pure water, rotation speed 300 rpm, conveyance speed 900 mm / min Case B2: anode ultrapure water, rotation speed 300 rpm, conveyance speed 900 mm / min Case B3: cathode water, rotation speed 300 rpm, conveyance speed 900 mm / min Case B4: Cathode water, rotation speed 400 rpm, conveyance speed 600 mm / min Case B5: cathode water, rotation speed 200 rpm, conveyance speed 600 mm / min Case B6: cathode water, rotation speed 400 rpm, conveyance speed 1200 mm / min Case B7: cathode water, rotation speed 200 rpm, transport speed 1200 mm / min

As is clear from FIG. 3, in cases B5 and B7 in which the number of rotations was 200 rpm using the cathode water,
It can be seen that the effect of reducing the number of particles can be obtained more than in most other cases.

The above-described embodiment is merely an example, and does not limit the present invention. For example, methods, conditions, materials, and the like of film formation and ion implantation can be freely changed as necessary.

In the above embodiment, the interlayer insulating film is formed in two steps, and cleaning is performed after the first interlayer insulating film is formed. However, film formation may be performed three or more times, and cleaning may be performed between any of the film formations.

[0043]

As described above, according to the method of manufacturing a liquid crystal display device of the present invention, an interlayer insulating film is formed at least in two steps, and cleaning is performed between any of the films. It is possible to form an interlayer film with few particles, and it is possible to prevent occurrence of a defect due to particles in the interlayer film.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view of an element showing a method of manufacturing a liquid crystal display device according to an embodiment of the present invention for each process.

FIG. 2 is a vertical cross-sectional view of an element showing a method of manufacturing the liquid crystal display device according to the embodiment for each step.

FIG. 3 is a graph showing the difference in the number of particles when the type of cleaning water, the number of rotations of the brush, and the transport speed are changed.

FIG. 4 is a longitudinal sectional view of an element showing a conventional method of manufacturing a liquid crystal display device for each process.

FIG. 5 is a vertical cross-sectional view of an element showing a method of manufacturing the liquid crystal display device according to the embodiment for each step.

[Explanation of symbols]

 Reference Signs List 1 insulating substrate 2 silicon nitride film 3 amorphous silicon film 4 polycrystalline silicon film 5 gate insulating film 6 gate electrode 10, 11, 12 resist film 13 interlayer insulating film (first layer) 14 interlayer insulating film (second layer) 15 Interlayer insulating film (whole) 16 Contact hole 17 Signal line

 ──────────────────────────────────────────────────続 き Continuing on the front page F term (reference) 2H088 FA18 FA21 HA04 2H092 HA06 JA34 JA35 JB56 KA05 KA12 KA18 KB25 MA07 MA19 MA22 MA26 MA30 NA29 5C094 AA42 AA43 BA03 BA43 CA19 DA15 EB02 FA02 FB02 FB15 GB10 5F110 DD0424BB DD25 EE06 EE44 FF02 FF29 GG02 GG13 GG32 GG34 GG44 GG52 HJ01 HJ04 HJ13 HJ23 HL03 HL04 HL12 HL23 HM15 NN03 NN04 NN35 NN40 PP03 PP35 QQ11

Claims (2)

[Claims] 1. A method for manufacturing a liquid crystal display device, comprising: a step of forming a semiconductor layer on an insulating substrate; and a step of forming an interlayer insulating film on the insulating substrate on which the semiconductor layer is formed. In the step of forming an insulating film, the interlayer insulating film is formed in n (n is an integer of 2 or more) times, and a j-th (j is an integer of 1 or more and n-1 or less) forming an interlayer insulating film And a step of cleaning the j-th interlayer insulating film before forming the (j + 1) -th interlayer insulating film. 2. The method for manufacturing a liquid crystal display device according to claim 1, wherein in the cleaning step, cleaning is performed using cathode water and a brush.