JP2002100783A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which has high dielectric strength and reduced on resistance, by improving the structure of a drift area depleted in an off-state. SOLUTION: This semiconductor device has a p-type channel diffusion region 77 formed on an insulating film 6 on a semiconductor base 5, a trench gate electrode 111 formed on its sidewall across a gate insulating film 10, an n+-type source region 88 formed along its upper edge, an n+ drain region 99 formed at a distance from the electrode 111, a drain drift region 290 extending between the drain and gate, and a thick insulating film 12 formed thereupon. The drift region 290 is in superposition structure formed by laminating a plate type n-type divided drift path region 1 and a plate type p-type partition region 2 repeatedly by turns; and a p-type side end region 2a is formed directly below the bottom n-type divided drift path region 1 and a p-type side end region 2a is also formed above the top n-type divided drift path region 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a high breakdown voltage and a large current capacity applicable to MOSFETs (insulated gate type field effect transistors), IGBTs (conductivity modulation type transistors), bipolar transistors, diodes and the like.

[0002]

2. Description of the Related Art Generally, semiconductor elements can be roughly classified into a horizontal structure having an electrode portion on one side and a vertical structure having an electrode portion on both surfaces.
For example, FIG. 10 shows an SOI (silicon) having a horizontal structure.
on-insulator-MOSFET. The structure of this SOI-MOSFET is an n-channel MOSFET
A p-type channel diffusion layer 7 formed on an insulating film 6 on a semiconductor substrate 5 and a field plate formed on the channel diffusion layer 7 with a gate insulating film 10 interposed therebetween. Gate electrode 11, an n ⁺ -type source region 8 formed at one end of the gate electrode 11 in the channel diffusion layer 7, and an n ⁺ -type drain formed at a position separated from the other end of the gate electrode 11. Area 9
And an n-type low concentration drain region (drain / drift region) 90 extending between the drain and the gate, and a thick insulating film 12 formed on the low concentration drain region 90.

The low-concentration drain region 90 is formed by a MOS
When the FET is in the ON state, it functions as a drift region in which carriers flow by an electric field. When the FET is in the OFF state, it depletes to reduce the electric field strength and increase the breakdown voltage. Low concentration drain region 9
Increasing the impurity concentration of 0 and shortening the current path length in the region 90 leads to an effect of lowering the substantial on-resistance (drain-source resistance) of the MOSFET because the drift resistance becomes lower. In addition, the depletion layer between the drain and the channel that progresses from the pn junction Ja between the p-type channel diffusion layer 7 and the n-type low-concentration drain region 90 does not easily spread, and reaches the maximum (critical) electric field strength of silicon quickly. (Drain-source voltage) is reduced.
That is, there is a trade-off relationship between the on-resistance (current capacity) and the withstand voltage. It is known that this trade-off relationship is similarly established in semiconductor devices such as IGBTs, bipolar transistors, and diodes.

FIG. 11 shows another structure of a lateral MOSFET. FIG. 11A shows a p-channel MOSFET, which includes an n-type channel diffusion layer 3 formed on a p ⁻ type semiconductor layer 4 and a field plate formed on the channel diffusion layer 3 via a gate insulating film 10. With gate electrode 1
1, a p ⁺ -type source region 18 formed on one end side of the gate electrode 11 in the channel diffusion layer 3, and a p-type low-concentration drain region (drain) where the well end is located immediately below the other end side of the gate electrode 11. A drift region 14, ap ⁺ -type drain region 19 formed at a position separated from the other end of the gate electrode 11, an n ⁺ -type contact region 71 adjacent to the p ⁺ -type source region 18, and p And a thick insulating film 12 formed on the low-concentration drain 14. Also in such a structure, the on-resistance and the withstand voltage are determined in a trade-off relationship by the current path length and the impurity concentration of the well-shaped p-type low-concentration drain region 14.

FIG. 11B shows a double diffusion type n-channel MO.
SFET, and n formed on the p ⁻ type semiconductor layer 4
Type low concentration drain layer (drain / drift layer) 22;
A gate electrode 11 with a field plate formed on the low-concentration drain layer 22 via the gate insulating film 10;
A well-type p-type channel diffusion region 17 formed at one end of the gate electrode 11 in the low-concentration drain layer 22;
Formed in a well shape in the channel diffusion region 17
⁺ -Type source region 8, a well-like p-type top layer 24 formed on the surface layer between the gate electrode 11 and the n ⁺ -type drain region 9 spaced thereto, the n ⁺ -type source region 8 It has an adjacent p ⁺ -type contact region 72 and a thick insulating film 12 formed on the p-type top layer 24. Even in such a structure, the on-resistance and the breakdown voltage are determined in a trade-off relationship by the current path length and the impurity concentration in the n-type low-concentration drain layer region 22.

However, in the structure of FIG. 11B, the n-type low-concentration drain layer 22 is sandwiched between the lower p ^- type semiconductor layer 4 and the upper p-type top layer 24.
Is in the off state, p-type channel diffusion region 17 and p
Not only from the n-junction Ja, but also the n-type low concentration drain layer 2
The depletion layer also extends from the upper and lower pn junctions Jb, Jb.
As a result, the low-concentration drain layer 22 is depleted quickly, so that a high breakdown voltage structure is obtained. To that extent, the impurity concentration of the low-concentration drain layer 22 can be increased, and the current capacity can be increased by reducing the on-resistance.

On the other hand, as a semiconductor device having a vertical structure, for example, a trench gate type n-channel MOS shown in FIG.
FETs are known. This structure is dug into the n-type low-concentration drain layer 39 formed on the n ⁺ -type drain layer 29 to which the back electrode (not shown) is in conductive contact, and the surface side of the low-concentration drain layer 39. Trench gate electrode 21 buried in trench groove via gate insulating film 10
And a p-type channel diffusion layer 2 formed on the surface of the low-concentration drain layer 39 so as to be as shallow as the depth of the trench gate electrode 21.
7, an n ⁺ -type source region 18 formed along the upper edge of the trench gate electrode 21, and a thick insulating film 12 covering the gate electrode 21. Note that an n-type IGBT structure can be obtained by using a two-layer structure including an n ⁺ -type upper layer and a p ⁺ -type lower layer instead of the single n ⁺ -type drain layer 29. Even in such a vertical structure, the portion of the low-concentration drain layer 39 functions as a drift region forming a drift current in the vertical direction when the MOSFET is on, and depletes and increases the breakdown voltage when the MOSFET is off. Again, the on-resistance and the withstand voltage are governed by the thickness and the impurity concentration of the low-concentration drain layer 39, and there is a trade-off between the two.

[0008]

FIG. 13 shows n of silicon.
4 is a graph illustrating a relationship between an ideal withstand voltage and an ideal on-resistance of a channel MOSFET. Ideal breakdown voltage is pn due to shape effect
It was assumed that there was no reduction in junction breakdown voltage. It is assumed that the ideal on-resistance is so small that the resistance of the portion other than the low concentration drain region can be ignored. FIG. 13 shows the relationship between the ideal breakdown voltage and the ideal on-resistance of the vertical n-channel MOSFET shown in FIG. In the vertical element, the direction in which the drift current flows when turned on is the same as the direction in which the depletion layer extends and spreads due to the reverse bias when turned off. Paying attention only to the low-concentration drain layer 39 in FIG. 12, the ideal withstand voltage BV in the off state is approximately obtained by the following equation. ^{_{BV = E c 2 ε 0 ε}} Si α (2-α) / 2qN D (1) E c: E c (N D), the maximum electric field intensity of the silicon in the impurity concentration _{N D} ε _0: dielectric constant of vacuum epsilon _Si : relative dielectric constant of silicon q: unit charge N _D : impurity concentration of low concentration drain region α: coefficient (0 <α <1) In addition, the ideal on-resistance per unit area at the time of on is approximately obtained by the following equation. I get it. _{R = αW / μqN D μ:} μ (N D), where the mobility of electrons in the impurity concentration _{N D,} since it is _{W = E c ε 0 ε Si} / qN D, R is, R = _{E c} ε ₀ becomes ^{_{ε Si α / μq 2 N D}} 2 (2). (1) is obtained (2) erases the qN _D from equation, using the optimal value as for example 2/3 of the ^{α, R = BV 2 (27} / 8E c 3 ε 0 ε Si μ) (3) . Here, although the ON resistance R appears to be proportional to the square of the withstand voltage BV, since _{E c} and μ is dependent on _{N D,} 2.4 to 2.6 of the fact 13 of the BV
It is proportional to the power.

FIG. 13 shows a horizontal type M shown in FIG.
MOSF with OSFET structure replaced with n-channel type
The relationship between the ideal withstand voltage of ET and the ideal on-resistance is shown. This n
In the channel type MOSFET, the direction in which the drift current flows in the on-state is the horizontal direction, while the direction in which the depletion layer extends in the off-state is not the horizontal direction from the well end but substantially the vertical direction (upward) from the well bottom. Is faster. In order to obtain a high breakdown voltage with the depletion layer extending in the vertical direction, the depletion must be performed from the pn junction surface (well bottom) between the low-concentration drain region 14 and the channel diffusion layer 3 to the surface of the low-concentration drain layer 14 (well surface). Must. Therefore, the maximum value of the doping amount of the net of the low-concentration drain region 14 is limited to S _D = E _c ε ₀ ε _Si / q (4). When the lateral length of the low-concentration drain region 14 is L, the ideal breakdown voltage BV is BV = E _c Lβ (5). Here, β is an unknown coefficient (0 <β <1). Further, the ideal on-resistance R per unit area, obtained in approximately by _{^{R = L 2 / μqS D (}} 6). Thus, (5), (6) to clear the L from equation (4) Substituting ^{equation, R = BV 2 / β 2} E c 3 ε 0 ε Si μ (7)

FIG. 13 shows a horizontal type 2 shown in FIG.
The relationship between the ideal withstand voltage and the ideal on-resistance of the structure of the heavy diffusion type n-channel MOSFET is shown. In the structure of FIG. 11B, a p-type top layer 24 is provided in the structure of FIG. 11A, and the low-concentration drain layer 22 is pinched and depleted early by a depletion layer extending from both upper and lower sides. The net doping amount _SD of the low concentration drain region 22 is shown in FIG.
It can be increased to about twice as much as that of (a). Relationship between _{S D = 2E c ε 0 ε} Si / q (8) ideal on-resistance R and the ideal breakdown voltage BV when such becomes ^{R = BV 2 / 2β 2 E} c 3 ε 0 ε Si μ (9) .

Although the trade-off relationship between the on-resistance and the breakdown voltage is somewhat improved as compared with FIG. 13, the concentration can be set only up to twice as high, and the current capacity and the breakdown voltage of the semiconductor element can be freely designed. Degrees are still low.

In view of the above problems, the first aspect of the present invention
The challenge is to improve the structure of the drift region,
It is an object of the present invention to provide a semiconductor device in which a trade-off relationship between on-resistance and withstand voltage is greatly relaxed, and a high withstand voltage can be used to increase current capacity by reducing on-resistance.
A second object of the present invention is to provide a manufacturing method capable of manufacturing the semiconductor device with good mass productivity.

[0013]

In order to solve the above-mentioned problems, a means taken by the present invention is to provide a drift region in which a drift current flows in an on state and is depleted in an off state, such as a lightly doped drain region of a MOSFET. 1, the drift region has a parallel divisional structure such as a layered structure, a fibrous structure, or a honeycomb structure, and is adjacent to the first conductivity type divided drift path region 1, as schematically shown in FIG. The second conductivity type partition region 2 is provided between the side surfaces (boundary) of each other to separate the pn junction.

That is, as shown in FIG. 1A, the drift region is a layered structure having two or more plate-shaped first conductivity type (for example, n-type) divided drift path regions 1 which are connected in parallel at least at their ends. A second parallel plate-shaped drift path group (divided drift path aggregate) 100 having a structure and a plate-shaped second part interposed between the divided drift path areas 1 and 1 and separated by a pn junction.
And a conductive type (for example, p-type) partition region 2. The plurality of second conductivity type partition regions 2 are connected in parallel to each other at least at the ends.

The structure of the drift region shown in FIG. 1 (b) is a fibrous structure, and has a streak-like first conductivity type (n-type) divided drift path region 1 and a streak-like second conductivity type (p-type). (Type) The partition areas 2 are arranged in a checkered pattern in the cross section of the aggregate.

Further, the first conductivity type (n) shown in FIG.
(Type) The divided drift path region 1 has connection portions 1a at four corners.

As can be clearly understood from FIG. 1A, the pn junction is separated along the outer side of the first conductive type split drift path region 1 at the outermost end (the uppermost end or the lowermost end) of the parallel drift path group 100. A two-conductivity-type end region 2a may be provided.

When the semiconductor device is in an on state, a drift current flows through a plurality of divided drift path regions 1 and 1 connected in parallel. On the other hand, when the semiconductor device is in an off state, the first conductive type divided drift path region 1 and 1 are connected. A depletion layer is formed from the pn junction with the second conductivity type partition region 2 by the first conductivity type divided drift path 1.
It spreads inside and is depleted. Since the depletion ends spread laterally from both sides of the single second conductivity type partition region 2, depletion is greatly accelerated. Also, the second conductivity type partition region 2 is simultaneously depleted. Therefore, the semiconductor device has a high withstand voltage, and n
Since the impurity concentration in the mold-dividing drift path region 1 can be increased, the on-resistance can be reduced. In particular, in the present invention, the depletion end enters both of the first conductivity type divided drift path regions 1 and 1 from both side surfaces of the single second conductivity type partition region 2, and the depletion spreads to both. Since the end effectively acts on the divided drift path regions 1 and 1, the total occupied width of the second conductivity type partition region 2 for forming the depletion layer can be halved, and the first conductivity type divided drift path is correspondingly reduced. The cross-sectional area of the region 1 can be increased, and the on-resistance is significantly reduced as compared with the related art. It is preferable that the occupied width of the second conductivity type partition region 2 is small. It is desirable that the impurity concentration of the second conductivity type partition region 2 is low. As the number (the number of divisions) of the first conductivity type divided drift path region 1 per unit area is increased, the trade-off relationship between the on-resistance and the withstand voltage can be greatly reduced.

In the present invention, the trade-off relation between the ideal on-resistance r and the ideal withstand voltage BV with respect to the first conductive type divided drift path region 1 is as follows, assuming that the width of the second conductive type partition region 2 is infinitely small. since the ideal oN resistance r of a ray is equivalent to N times the ideal on-resistance R of the formula (9), a ^{r = NR = BV 2 / 2β} 2 E c 3 ε 0 ε Si μ (10), relationship of the ideal on the whole parallel drift path group resistor R and the ideal breakdown voltage BV becomes ^{R = BV 2 / 2Nβ 2 E} c 3 ε 0 ε Si μ (11). Therefore, it is understood that the larger the number of divisions N of the drift region, the more a semiconductor device with significantly reduced on-resistance can be realized.

That is, according to the present invention, in a semiconductor device having a drift region in which a drift current flows in a lateral direction in an on state and is depleted in an off state, the drift region includes a plurality of first conductivity type divided drift paths connected in parallel. Having a parallel drift path group having a region and a second conductivity type partition region interposed between adjacent ones of the first conductivity type divided drift path region, wherein the drift region is an insulating film on a semiconductor layer. And a surface side insulating film.
According to such a configuration, the on-resistance can be reduced and the withstand voltage can be increased.

Here, it is desirable that the insulating film on the semiconductor layer be formed thicker than the surface-side insulating film. The drift region may have a superimposed parallel structure in which a layered first conductivity type divided drift path region and a layered second conductivity type partition region are alternately and repeatedly stacked. It is sandwiched between the upper insulating film and the front-side insulating film. The drift region may have a structure in which stripe-shaped first conductivity type divided drift path regions and stripe-shaped second conductivity type partition regions are alternately arranged along the surface of the insulating film on the semiconductor layer. it can.

Further, according to the present invention, a second conductivity type side end region is provided outside the outermost first conductivity type divided drift path region of the parallel drift path group, and the second conductivity type side end region is formed. The length and width are substantially equal to the length and width of the second conductivity type partition region. Further, a second conductivity type side end region is provided outside the outermost first conductivity type split drift path region of the parallel drift path group, and the length and width of the second conductivity type side end region are outermost. The first conductive type divided drift path region is substantially equal in length and width. With this configuration, it is possible to reduce the on-resistance and increase the withstand voltage.

[0023]

Next, an embodiment of the present invention will be described with reference to the accompanying drawings.

[Embodiment 1] FIG. 2A is a plan view showing an SOI-MOSFET having a horizontal structure according to Embodiment 1 of the present invention, and FIG. 2B is a sectional view taken along the line AA 'in FIG. 2A. FIG. 2C is a cross-sectional view showing a state cut along a line, and FIG.
It is a sectional view showing the state where it was cut by the B 'line.

The structure of the SOI-MOSFET of this example is an offset gate structure of an n-channel MOSFET, similar to the structure shown in FIG. 10, and is a p-type MOSFET formed on an insulating film 6 on a semiconductor substrate 5. A channel diffusion region 7, a gate electrode 11 with a field plate formed on the channel diffusion region 7 via a gate insulating film 10, and an n ⁺ type formed on one end side of the gate electrode 11 in the channel diffusion region 7. Source region 8 and n ⁺ -type drain region 9 formed at a position separated from the other end of gate electrode 11.
And a drain drift region 190 extending between the drain and the gate, and a thick insulating film 12 formed on the drain drift region 190.

The drain drift region 19 in this embodiment
0 indicates a strip-shaped n-type divided drift path region 1 and a strip-shaped p
It has a striped parallel structure in which the mold partition areas 2 are alternately and repeatedly arranged on a plane. One end of the plurality of n-type divided drift path regions 1 is connected to p-type channel diffusion region 7 by p-type.
and n junction, the other ends thereof are formed an n ⁺ -type are connected to the drain region 9 of, n ⁺ -type drift path group 100 connected in parallel branched from the drain region 9 side. Outside the divided drift path region 1 at the outermost end of the parallel drift path group 100, a striped p-type end region 2a is provided, and all the divided drift path regions 1 are p-type semiconductor regions along the side surfaces. 2 (2a). One end of each of the plurality of p-type partition regions 2 is connected to a p-type channel diffusion region 7, and the other end is connected to an n ⁺ -type drain region 9.
Pn junction, and are branched and connected in parallel from the p-type channel diffusion region 7 side.

When the MOSFET is on, carriers (electrons) flow from the n ⁺ -type source region 8 into the plurality of n-type divided drift path regions 1 via the channel inversion layer 13 immediately below the gate insulating film 10, and the drain・ Drift current flows in the electric field due to the voltage between the sources. On the other hand, in the off state, the channel inversion layer 13 immediately below the gate insulating film 10 disappears, and the pn junction J between the n-type divided drift path region 1 and the p-type channel diffusion region 7 is caused by the drain-source voltage.
a, n-type drift path region 1 and p-type partition region 2
From the n-junction Jb, a depletion layer spreads into the n-type split drift path region 1 and is depleted. The depletion end from the pn junction Ja spreads in the path length direction in the n-type split drift path region 1, while the depletion end e from the pn junction Jb spreads in the path width direction in the n-type split drift path region 1, and Since the depletion edge extends from both sides, depletion is greatly accelerated. Also, the p-type partition region 2 is simultaneously depleted. As a result, the electric field intensity is reduced, the breakdown voltage becomes high, and the impurity concentration of the n-type divided drift path region 1 can be increased accordingly, so that the on-resistance is reduced. In particular, in this example, the n-type split drift path regions 1 and 1 adjacent from both side surfaces of the p-type partition region 2
Since the depletion end e enters both sides of 1
The total occupied width of the p-type partition region 2 for forming the depletion layer can be reduced by half, and the sectional area of the n-type divided drift path region 1 can be increased accordingly, and the on-resistance is reduced as compared with the conventional case. .
As the number (the number of divisions) N of the n-type divided drift path region 1 per unit area is increased, the trade-off relationship between the on-resistance and the withstand voltage can be greatly reduced. Three or more are more remarkable than two. Preferably, the occupied width of the p-type partition region 2 is small.

Here, the ideal withstand voltage BV is, for example, 100V.
Assuming that the impurity concentration N in the n-type split drift path region 1_D
= 3 × 10^Fifteen(Cm^-3) 、 Maximum electric field strength of silicon
E_c = 3 × 10⁵(V / cm), electron mobility μ = 1
000 (cm²/ V · sec), dielectric constant ε in vacuum₀
= 8.8 × 10^-12(C / V · m), ratio of silicon
Dielectric constant ε_Si= 12, unit charge q = 1.6 × 10
^-19(C). Low concentration drain region shown in FIG.
In the region 90, when the length is 6.6 μm and the thickness is 1 μm, the ideal
The on-resistance R is 9.1 (m ohm-cm)²). This
In contrast, in this example, the n-type split drift path region 1 and the p-type
The width of the partition area 2 is, for example, 10 μm, 1 μm, 0.1 μm
When the ideal on-resistance R is calculated as the value of (β = 2/3,
The length of the n-type divided drift path region 1 and the p-type partition region is 5 μm.
m), width 10 μm, 7.9 (m ohm-cm²) When the width is 1 μm, 0.8 (m ohm · cm)²) For a width of 0.1 μm, 0.08 (m ohm-c
m²) When the width is 1 μm or less, dramatic reduction in on-resistance is possible.
Noh. n-type divided drift path
If the width is smaller than the width of region 1, the effect is still remarkable.
You. The width of the n-type divided drift path region 1 and the p-type partition region is
Currently about 0.5μm by photolithography and ion implantation
Temperature is the limit of the mass production level,
Substantial progress will enable further width reductions in the future
Therefore, the on-resistance can be significantly reduced.

In particular, the structure of the drift region of this embodiment is a pn repeating structure having a stripe shape on a plane, so that 1
Since it can be formed by photolithography one time, the cost of the element can be reduced by simplifying the manufacturing process.

[Embodiment 2] FIG. 3A is a plan view showing a double diffusion type n-channel MOSFET according to Embodiment 2 of the present invention, and FIG. 3 (c) is a cross-sectional view showing a state cut along line ′, and FIG.
It is a sectional view showing the state where it was cut by the -B 'line.

The double diffusion type n-channel MOSFET of the present embodiment
11B is an improvement of the structure shown in FIG. 11B, and includes a drain drift region 122 formed on a p ⁻ type or n ⁻ type semiconductor layer 4 and a gate on the drain drift region 122. A gate electrode 11 with a field plate formed via an insulating film 10;
Well-shaped p-type channel diffusion region 17 formed on one end side of gate electrode 11 in drift region 122 and n ⁺ formed in p-type channel diffusion region 17 in a well shape
-Type source region 8 and n ⁺
And a thick insulating film 12 formed on the drain drift region 122.

The drain drift region 12 in this embodiment
2, a strip-shaped parallel structure in which strip-shaped n-type divided drift path regions 1 and strip-shaped p-type partition regions 2 are alternately arranged on a plane, similarly to the first embodiment shown in FIG. Has become. And a plurality of n-type split drift path regions 1
Has a pn junction with a p-type channel diffusion region 17,
The other ends thereof are connected to the n ⁺ -type drain region 9 and branch off from the n ⁺ -type drain 9 side to form a parallel drift path group 100 connected in parallel. Outside the divided drift path region 1 at the outermost end of the parallel drift path group 100, a p-type side end region 2a for sandwiching the divided drift path region 1 is provided.
It is sandwiched between the mold regions 2 (2a). One end of each of the plurality of p-type partition regions 2 is connected to a p-type channel diffusion region 7, and the other ends thereof are pn-junction with an n ⁺ -type drain region 9. It branches from the side and is connected in parallel.

Also in this example, when in the off state, pn
Since the depletion edge from the junction Jb extends in the width direction of the n-type split drift path region 1, and the depletion edge extends from both sides, depletion is greatly accelerated. At the same time, the p-type partition region 2
Is also depleted. For this reason, similarly to the first embodiment, the breakdown voltage becomes high, and the impurity concentration of the n-type divided drift path region 1 can be increased, so that the on-resistance can be reduced.

Here, comparing the conventional structure shown in FIG. 11B with an ideal withstand voltage of 100 V, the on-resistance of the conventional structure shown in FIG. 11B is about 0.5 (m ohm · c).
m ² ), on the other hand, in the structure of this example, when the thickness of the divided drift path region 1 and the p-type partition region 2 is 1 μm and the width is 0.5 μm, as in the first embodiment, the on-resistance is reduced. 0.4
(M ohm · cm ² ). Split drift path area 1
By further reducing the width of the p-type partition region 2, the on-resistance can be significantly reduced. By increasing the thickness of the divided drift path region 1 and the p-type partition region 2, the resistance cross-sectional area of the divided drift path 1 can be increased and the on-resistance can be reduced. For example, if it is 10 μm, the on-resistance is 1/10, and if it is 100 μm, the on-resistance is 1/100.
Can be In order to dope such a thick region, impurity ions may be implanted into the same site with a plurality of (or continuously different) energies.

[Embodiment 3] FIG. 4A is a plan view showing an SOI-MOSFET having a horizontal structure according to Embodiment 3 of the present invention, and FIG. 4B is a sectional view taken on line AA 'in FIG. FIG. 4C is a cutaway view showing a state cut along a line, and FIG.
It is a sectional view showing the state where it was cut by the B 'line.

The structure of the SOI-MOSFET of this embodiment is such that a p-type channel diffusion layer 77 formed on the insulating film 6 on the semiconductor substrate 5 and a gate insulating film 10 on the side wall of the channel diffusion layer 77. Gate electrode 11 formed
1, an n ⁺ -type source region 88 formed along the upper edge of the trench gate electrode 111, an n ⁺ -type drain region 99 formed at a position separated from the trench gate electrode 111, and a drain-gate , And a thick insulating film 12 formed on the drain drift region 290.

The drain drift region 29 in this embodiment
Numeral 0 is a superimposed parallel structure in which a plate-shaped n-type divided drift path region 1 and a plate-shaped p-type partition region 2 are alternately and repeatedly stacked. A p-type side end region 2a is formed immediately below the lowermost n-type divided drift path region 1, and a p-type side end region 2a is also formed on the uppermost n-type divided drift path region 1. ing. The net doping amount of the p-type side end region 2a is set to 2 × 10 ¹² / cm ² or less. Multiple n
One end of the type-divided drift path region 1 is pn-juncted with a p-type channel diffusion layer 77, and the other end thereof is connected to an n ⁺ -type drain region 99, and branches off from the n ⁺ -type drain 99 side. Thus, a parallel drift path group 100 connected in parallel is formed. One end of each of the plurality of p-type partition regions 2 is p-type.
Type channel diffusion layer 77, the other end of which is n
It has a pn junction with the ⁺ type drain region 99 and is branched from the p type channel diffusion layer 77 side to be connected in parallel.

Also in this layered structure, the ideal on-resistance is given by the above equation (11), and N is the number of stacked n-type divided drift path regions 1. When the ideal withstand voltage is 100 V, in the conventional structure (N = 1), the ideal on-resistance R = 0.
5 (m ohm · cm ² ), but in this example, N = 10
In the case of, R = 0.05 (m ohm · cm ² ),
The on-resistance drastically decreases in inverse proportion to the division number N.

The key technology of the embodiment shown in FIGS. 2 and 3 is photolithography and ion implantation, whereas the key technology of the present embodiment shown in FIG. 4 is a plate-shaped n-type split drift path region. This is a crystal growth method for alternately and repeatedly laminating 1 and a p-type partition region 2 in a plate shape. As the number of stacked layers increases, the total thickness increases, and the time required for crystal growth increases, so that the impurity distribution disorder due to impurity diffusion cannot be ignored.
Ideally, it is preferable that the n-type split drift path region 1 and the p-type partition region 2 are formed as thin as possible, and the crystal is grown at such a low temperature that disorder of the impurity distribution can be ignored. For this purpose, MOCVD (metal organic chemical vapor deposition crystal growth) used for compound semiconductors such as gallium arsenide and M are used rather than epitaxial growth often used in silicon technology.
BE (molecular beam crystal growth method) is suitable. According to this, the layer thickness of the layered n-type divided drift path region 1 and the layered p-type partition region 2 can be reduced, and the on-resistance can be significantly reduced.

In this embodiment, when the n-type divided drift path region 1 and the p-type partition region 2 are formed thin and the impurity concentration is increased, the channel inversion layer 13 is hardly formed, and the channel resistance is hardly reduced. As a result, it is difficult to lower the on-resistance. In order to improve this, it is effective to locally reduce the portion of the n-type divided drift path region 1 and the p-type partition region 2 which is in contact with the gate insulating film 10 to a low concentration region.

[Fourth Embodiment] FIG. 5A is a plan view showing a lateral MOSFET according to a fourth embodiment of the present invention, and FIG. 5B is a sectional view taken along line AA 'in FIG. 5A. FIG. 5C is a cut-away view showing a cut-off state, and FIG. 5C is a cut-away view showing a state cut along the line BB ′ in FIG. 5A.

The structure of the MOSFET of this embodiment is such that a p-type channel diffusion layer 77 formed on the p ^- type or n ^- type semiconductor layer 4 and a gate insulating film 10 on the side wall of the channel diffusion layer 77 are provided. Formed gate electrode 111
An n ⁺ -type source region 88 formed along the upper edge of trench gate electrode 111;
11 and an n ⁺ -type drain region 99 formed at a position separated from
Drift region 290 and drain / drift region 2
90 and a thick insulating film 12 formed thereon.

The drain drift region 29 in this example
0 is the same as that of the third embodiment, and the plate-like n
Drift path region 1 and plate-shaped p-type partition region 2
Are alternately and repeatedly laminated.
A p-type side end region 2a is formed immediately below the lowermost n-type divided drift path region 1, and a p-type side end region 2a is also formed on the uppermost n-type divided drift path region 1. ing. The net doping amount of this p-type side end region 2a is 2 ×
10 ¹² / cm ² or less. One end of the plurality of n-type divided drift path regions 1 is connected to the p-type channel diffusion layer 77 by pn.
The other ends thereof are connected to the n ⁺ -type drain region 99, and branch from the n ⁺ -type drain 99 side to form a parallel-connected parallel drift path group 100.
One end of each of the plurality of p-type partition regions 2 is connected to a p-type channel diffusion layer 77, and the other end thereof is pn-junction with an n ⁺ -type drain region 99. It branches from the side and is connected in parallel.

In this embodiment, the on-resistance can be reduced and the withstand voltage can be increased as in the third embodiment. Note that the relationship between this example and the third embodiment shown in FIG.
Corresponds to the first embodiment shown in FIG. As in the embodiment of FIG. 3 with respect to the embodiment of FIG. 2, the present example is not SOI, and can reduce the cost.

[Fifth Embodiment] FIG. 6A is a sectional view showing a p-channel MOSFET having a horizontal structure according to a fifth embodiment of the present invention, and corresponds to an improved example of FIG. 11A.

The structure of the present embodiment comprises an n-type channel diffusion layer 3 formed on a p ⁻ type semiconductor layer 4 and a gate electrode with a field plate formed on the channel diffusion layer 3 via a gate insulating film 10. 11, a p ⁺ -type source region 18 formed at one end of the gate electrode 11 in the channel diffusion layer 3, and a p-type drain drift region 14 whose well end is located immediately below the other end of the gate electrode 11. An n-type end region 2b formed in the surface layer of the p-type drain drift region 14, a p ⁺ -type drain region 19 formed at a position separated from the other end of the gate electrode 11, and a p ⁺ -type It has an n ⁺ -type contact region 71 adjacent to the source region 18 and a thick insulating film 12 formed on the p-type drain drift 14.

In the case of this example, the number of divisions of the drain region is one.
The cross section of the p-type drain drift region 14 corresponds to a single split drain path region 1 on the cross section. The thickness of the n-type end region 2b above the p-type drain drift region 14 is formed thin to accelerate depletion. FIG.
Compared with the structure of FIG. 7A, in this example, the n-type end region 2b is formed, and the depletion layer from the channel diffusion layer 3 below the p-type drain drift region 14 and the upper n-type end region are formed. The depletion from the region 2a promotes depletion. While the net doping amount of the drain drift region 14 in FIG. 11A is about 1 × 10 ¹² / cm ² , in the present example, it is about 2 × 10 ¹² / cm ^2, which is twice as large. Therefore, the impurity concentration of the drain / drift region 14 can be increased by the amount that the withstand voltage can be increased, and the on-resistance can be reduced.

[Embodiment 6] FIG. 6B is a sectional view showing an n-channel MOSFET having a horizontal structure according to Embodiment 6 of the present invention, and corresponds to an improved example of FIG. 11B.

This example is a double diffusion type n-channel MOSFET.
The drain drift region 22 (first n-type split drift path region 1) formed on the p ⁻ type semiconductor layer 4 (p-type side end region 2a) and the gate insulating film 10 are formed. And a well-shaped p-type channel diffusion region 17 formed at one end of the gate electrode 11 in the drain drift region 22.
And an n ⁺ -type source region 8 formed in a well shape in the p-type channel diffusion region 17, and a p-type layer formed on a surface layer between the gate electrode 11 and the n ⁺ -type drain region 9 separated therefrom. -type top layer 24 (p-type partition regions 2), and a second n-type drift regions 1 formed in the surface layer of the p-type partition regions 2, the p ⁺ -type adjacent to the n ⁺ -type source region 8 It has a contact region 72 and a thick insulating film 12 formed on the p-type partition region 2.

The lower drain / drift region 22 and the upper divided drift path region 1 are connected in parallel with a p-type partition region 2 interposed therebetween. Compared to the structure shown in FIG. 11B, the present embodiment is different from the structure shown in FIG. As described above, since the depletion layer extends from the p-type partition region 2 to both the lower drain drift region 22 and the upper divided drift path region 1,
High breakdown voltage can be achieved, and accordingly, on-resistance can be reduced. While the net doping amount of the drift region 22 in FIG. 11B is about 2 × 10 ¹² / cm ² , in the present example, the lower drain / drift region 2
The total doping amount of the upper drift layer region 2 and the upper divided drift path region 1 can be increased to about 3 × 10 ¹² / cm ^2, that is, 1.5 times. According to the structure of this example, a trade-off relationship between the ideal withstand voltage and the ideal on-resistance shown in FIG. 13 can be obtained. Clearly, it has been found that the trade-off relationship between the ideal withstand voltage and the ideal on-resistance can be relaxed as compared with the conventional structure.

As a manufacturing method for obtaining the structures of the fifth and sixth embodiments, first, phosphorus ions are implanted into the p ⁻ type semiconductor layer 4 and heat treatment (thermal diffusion) is performed.
After the formation of (22), the p-type region 14 (24) is formed by selective ion implantation of boron on the surface of the n-type semiconductor layer 3 (22) and heat treatment (thermal diffusion), and thereafter, thermal oxidation A thin n-type side end region 2b (n-type split drift path region 1) is formed on the surface layer by applying a treatment to increase the concentration by segregation of phosphorus on the silicon surface and reduce the concentration by segregation of boron into the oxide film. To form Since the opposite conductivity type layer is not adjacent to the n-type side end region 2b or the upper layer of the n-type split drift path region 1, the thinner the layer, the easier it is to deplete. Therefore, the advantage that the n-type side end region 2b (the n-type divided drift path 1) can be formed only by the thermal oxidation process contributes to the reduction in the number of processes and enables mass production.

In the fifth embodiment, the n-type side end region 2b
Is separated from the gate insulating film 10 and the drain / drift region 14.
This is because the n-type side end region 2b is formed on the entire surface of the silicon. However, if the n-type side end region 2b is thin, no problem occurs because the drain / drift region 14 is conducted by the channel inversion layer formed immediately below the gate 10.

[Seventh Embodiment] FIG. 7A is a plan view showing a trench gate type n-channel MOSFET having a vertical structure according to a seventh embodiment of the present invention, and FIG. FIG. 8 is a sectional view showing a state cut along the line AA ′ of FIG.
7A is a sectional view showing a state cut along the line BB 'in FIG. 7A, and FIG. 8B is a sectional view taken along CC' in FIG. 7B.
9A is a cross-sectional view showing a state cut along a line, FIG. 9A is a cross-sectional view showing a state cut along a DD ′ line in FIG. 7A, and FIG. It is a sectional view showing the state where it cut | disconnected along EE 'line in a).

The structure of this embodiment is such that the n ⁺ -type drain layer 29 with which the back electrode (not shown) is in conductive contact, the drain drift layer 139 formed thereon, and the surface side of the drain drift layer 139 A trench gate electrode 21 buried in the dug trench via the gate insulating film 10, and a p-type channel layer formed as shallow as the depth of the trench gate electrode 21 on the surface of the drain drift layer 139. 27, an n ⁺ -type source region 18 formed along the upper edge of the trench gate electrode 21, and a thick insulating film 12 covering the gate electrode 21. It should be noted that if a single-layer n ⁺ -type drain layer 29 is replaced with a two-layer structure composed of an n ⁺ -type upper layer and a p ⁺ -type lower layer or a p-type layer, an n-type IGBT
Structure can be obtained.

The drain drift layer 139 in this embodiment
As shown in FIGS. 8 (b) and 9, a plate-shaped n-type divided drift path region 1 in the vertical direction and a plate-shaped p-type partition region 2 in the vertical direction are alternately and repeatedly adjacent to each other. Has become. A plurality of n-type split drift path regions 1
Have a pn junction with a p-type channel diffusion layer 27, and their lower ends are connected to an n ⁺ -type drain layer 29.
A parallel drift path group 100 connected in parallel is formed by branching from the n ⁺ type drain layer 29 side. Although not shown, a p-type side end region is provided outside the outermost divided drift path region 1 of the parallel drift path group 100, and all the divided drift path regions 1 are p-type along side surfaces. It is sandwiched by the partition region 2 or the p-type side end region. The upper ends of the plurality of p-type partition regions 2 are p-type channel diffusion layers 2.
7, and their lower ends are pn-junction with the n ⁺ -type drain layer 29, and are branched and connected in parallel from the p-type channel diffusion layer 27 side.

In the off state, the channel inversion layer 13 immediately below the gate insulating film 10 disappears, and the pn junction Ja, Ja of the n-type split drift path region 1 and the p-type channel diffusion layer 27 is caused by the drain-source voltage. n-type split drift path region 1
A depletion layer spreads from the pn junction Jb between the p-type partition region 2 and the p-type partition region 2 into the n-type split drift path region 1 and is depleted. The depletion end from the pn junction Ja spreads in the path length direction in the n-type split drift path region 1, but the depletion end from the pn junction Jb spreads in the path width direction in the n-type split drift path region 1 and both sides. Since the depletion edge extends from the surface, depletion is greatly accelerated. Also, the p-type partition region 2 is simultaneously depleted. In particular, since the depletion ends enter both the n-type divided drift paths 1 and 1 from both sides of the p-type partition region 2, the p-type partition region 2 for forming the depletion layer is formed.
Can be reduced by half, the cross-sectional area of the n-type divided drift path region 1 can be increased accordingly, and the on-resistance can be reduced as compared with the conventional case. As the number of the n-type divided drift paths 1 per unit area (the number of divisions) is increased, the trade-off relationship between the on-resistance and the withstand voltage can be greatly reduced.

An n-channel MOSFE having an ideal withstand voltage of 100 V
Compared to the ideal on-resistance at T (conventional structure shown in FIG. 12), in the case of the conventional structure, the ideal on-resistance R = about 0.6 (m ohm · cm ² ) according to FIG. , The n-type split drift path region 1 and the p-type partition region 2
Is assumed to be about 5 μm and β = ２, and n
When the thickness in the stacking direction of the mold-divided drift path region 1 and the p-type partition region 2 is calculated as a value of, for example, 10 μm, 1 μm, and 0.1 μm, 1.6 (m ohm · cm ² ) is obtained when the thickness is 10 μm. When the thickness is 1 μm, 0.16 (m ohm · cm ² ) When the thickness is 0.1 μm, 0.016 (m ohm · cm ² )
² ) Dramatically lower on-resistance is possible even on the order of μm. If the width of the p-type partition region 2 is made smaller than the width of the n-type divided drift path region 1, the effect will be more remarkable. n
The width of the mold-dividing drift path region 1 and the width of the p-type partition region are currently limited to about 0.5 μm by photolithography and ion implantation at the limit of mass production level. Is possible,
ON resistance can be significantly reduced.

As in the present example, the repetitive structure of the n-type divided drift path region 1 and the p-type partition region 2 arranged in the vertical direction is as follows.
Although there are some difficulties in the manufacturing method as compared with the case of the lateral semiconductor structure, for example, after forming an n-type layer on the drain layer 29 by epitaxial growth, the n-type layer is removed by etching at intervals in a stripe shape. Alternatively, a method of filling the etching groove by p-type epitaxial growth and polishing and removing unnecessary portions can be adopted. Also, a method of selectively forming a reverse conductivity type region deeply by selectively implanting neutron beams or high-energy particles having a large range and using the resulting transmutation can be considered.

The structure according to the present invention is based on MOSFET
IGBTs, bipolar transistors, diodes, JFETs, thyristors, MESFETs, HEMTs.
And so on can be applied to almost all semiconductor devices. Further, the conductivity type can be appropriately changed to a reverse conductivity type. Although FIG. 1 shows a layer-shape, fiber-shape, net-shape or honeycomb shape as the parallel division drift group, the present invention is not limited to this, and other repetitive shapes can be adopted.

[0060]

As described above, the drift region according to the present invention is composed of a parallel drift path group having a plurality of first conductivity type divided drift path areas connected in parallel, and a drift area adjacent to the first conductivity type divided drift path area. And a second conductivity type partition region interposed between the semiconductor layers, wherein the drift region is sandwiched between an insulating film on the semiconductor layer and a surface-side insulating film. According to such a configuration, the on-resistance can be reduced and the withstand voltage can be increased.

Further, according to the present invention, a second conductivity type side end region is provided outside the outermost first conductivity type split drift path region of the parallel drift path group, and the second conductivity type side end region is formed. The length and width are substantially equal to the length and width of the second conductivity type partition region. Further, a second conductivity type side end region is provided outside the outermost first conductivity type split drift path region of the parallel drift path group, and the length and width of the second conductivity type side end region are outermost. The first conductive type divided drift path region is substantially equal in length and width. With this configuration, it is possible to reduce the on-resistance and increase the withstand voltage.

[Brief description of the drawings]

FIGS. 1A to 1C are schematic views respectively showing the structure of a drift region in a semiconductor device according to the present invention.

FIG. 2A is a plan view showing an SOI-MOSFET having a lateral structure according to the first embodiment of the present invention, FIG. 2B is a cutaway view showing a state cut along a line AA ′ in FIG. (C) is a cut-away view showing a state cut along the line BB 'in (a).

FIG. 3A is a plan view showing a double diffusion type n-channel MOSFET according to a second embodiment of the present invention, and FIG.
FIG. 3C is a sectional view showing a state cut along a line AA ′ in FIG. 4C, and FIG. 4C is a sectional view showing a state cut along a line BB ′ in FIG.

FIG. 4A is a plan view showing an SOI-MOSFET having a horizontal structure according to a third embodiment of the present invention, FIG. 4B is a sectional view showing a state cut along line AA ′ in FIG. (C) is a cut-away view showing a state cut along the line BB 'in (a).

FIG. 5A is a plan view showing a MOSFET having a lateral structure according to a fourth embodiment of the present invention, and FIG.
FIG. 3 is a cutaway view showing a state cut along line A ′, and FIG. 3 (c) is a cutaway view showing a state cut along line BB ′ in FIG.

FIG. 6A is a cross-sectional view illustrating a lateral p-channel MOSFET according to a fifth embodiment of the present invention, and FIG. 6B is a lateral n-channel MOSFET according to a sixth embodiment of the present invention;
FIG.

FIG. 7A is a plan view illustrating a trench gate type n-channel MOSFET having a vertical structure according to a seventh embodiment of the present invention, and FIG. 7B is a view taken along line AA ′ in FIG. FIG. 4 is a cutaway view showing a cut state.

8A is a sectional view showing a state cut along the line BB 'in FIG. 7A, and FIG. 8B is a sectional view taken along line C-B in FIG. 7B.
It is a sectional view showing the state where it was cut along the line C '.

9 (a) is a cross-sectional view showing a state cut along the line DD ′ in FIG. 7 (a), and FIG. 9 (b) is a cross-sectional view taken along line E-
It is a sectional view showing the state where it was cut along the E 'line.

FIG. 10 (a) is a conventional SOI-MOSF having a horizontal structure.
FIG. 2B is a plan view showing ET, and FIG.

11A is a cross-sectional view showing another structure of a conventional MOSFET having a lateral structure, and FIG. 11B is a cross-sectional view showing the structure of a conventional double-diffusion n-channel MOSFET.

FIG. 12 shows a conventional trench gate type n-channel MOS.
FIG. 3 is a cross-sectional view showing an FET.

FIG. 13 is a graph showing a trade-off relationship between ideal withstand voltage and ideal on-resistance of various silicon n-channel MOSFETs.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... N-type split drift path area 1a ... Connection part 2 ... P-type partition area 2a ... P-type side end area 3 ... N-type channel diffusion layer 4 ... p ^- type semiconductor layer 5 ... Semiconductor base 6 ... Insulating film 7 ... p Type channel diffusion layer 8 n ⁺ type source region 9 n ⁺ type drain region 10 gate insulating film 11 gate electrode with field plate 12 thick insulating film 13 channel inversion layer 14 p-type low concentration region 17 p type channel diffusion region 18, 28 ... ^{p +} -type source region 19 ... ^{p +} -type drain region 21 ... trench gate electrode 22 ... n-type low-concentration drain layer 24 ... p-type top layer 27 ... p-type channel layer 29 ... ^{n +} -type drain layer 39 ... n-type low-concentration drain layer 71 ... ^{n +} -type contact region 72 ... ^{p +} -type contact region 77 ... p-type channel diffusion layer 88 ... ^{n +} -type source region 90 ... n-type low concentrated Drain regions (drain drift region) 99 ... p-type drain region 100 ... parallel drift path group 111 ... trench gate electrode 90,122,139,290 ... drain drift region e ... depletion end Ja, Jb ... pn junction.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/786 H01L 29/78 622 617K 301D 301X

Claims (6)

[Claims] 1. A semiconductor device having a drift region in which a drift current flows in a lateral direction in an on state and is depleted in an off state, wherein the drift region has a plurality of first conductivity type divided drift path regions connected in parallel. A structure having a parallel drift path group and a second conductivity type partition region interposed between adjacent ones of the first conductivity type split drift path region, wherein the drift region is formed by an insulating film on a semiconductor layer. A semiconductor device, which is interposed between a front-side insulating film and the insulating film. 2. The semiconductor device according to claim 1, wherein the insulating film on the semiconductor layer is formed to be thicker than the surface-side insulating film. 3. The drift region according to claim 1, wherein the drift region is formed by alternately repeatedly stacking the layered first conductivity type divided drift path region and the layered second conductivity type partition region. A semiconductor device having a superimposed parallel structure, wherein the superimposed parallel structure is interposed between an insulating film on the semiconductor layer and a surface-side insulating film. 4. The semiconductor device according to claim 1, wherein the drift region insulates the striped first conductivity type drift path region from the striped second conductivity type partition region on the semiconductor layer. A semiconductor device having a structure alternately arranged along a surface of a film. 5. The second conductivity type side end region according to claim 1, wherein the second conductivity type side drift region is provided outside the outermost first conductivity type divided drift path region of the parallel drift path group. And a length and a width of the second conductivity type side end region are substantially equal to a length and a width of the second conductivity type partition region. 6. The second conductivity type side end region according to any one of claims 1 to 4, wherein the second conductivity type side end region is provided outside the first conductivity type divided drift path region on the outermost side of the parallel drift path group. And a length and a width of the second conductivity type side end region are substantially equal to a length and a width of the outermost first conductivity type split drift path region.