JP2002095266A - Gate device of converter for power - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance reliability by preventing a wrong gate pulse due to a noise. SOLUTION: An NPC converter 4 is constituted by providing a plurality of semiconductor switching elements; a gate signal generation circuit 1 generating an on/off signal of a gate pulse signal in the semiconductor switching element; a gate logic circuit 2 making the gate pulse signal output from the gate signal generation circuit 1 serve as an input to apply work, so as to ensure a switching time of the semiconductor switching element relating to this gate pulse signal to be given to a gate circuit 3 of the NPC converter; and a non- conformed gate pattern removal circuit 5 provided between the gate signal generation circuit 1 and the gate logic circuit 2, to remove combination of a non-conformed gate pulse pattern signal of the semiconductor switching element in each arm of the NPC converter 4, are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a gate pulse signal from a gate signal generating circuit in a power converter comprising a plurality of power semiconductor switching elements (hereinafter simply referred to as semiconductor switching elements). And a gate device which is processed so as to secure the switching time of the semiconductor switching element and which is applied to the semiconductor switching element, and particularly to a gate device of a highly reliable power converter capable of preventing erroneous gate pulses due to noise. It is about.

[0002]

2. Description of the Related Art Conventionally, power converter equipment has become a very large equipment with an increase in power dose, and interconnection with each control circuit and device is performed by an electric signal line. .

However, as the power converter equipment becomes larger, the length of the electric signal line becomes longer, and noise may be carried on the electric signal line, which may cause a malfunction of the control system.

In particular, a gate pulse signal from the gate signal generating circuit of the semiconductor switching element to the gate circuit may cause malfunction of the semiconductor switching element due to malfunction due to noise, and it is necessary to be careful with respect to noise.

FIG. 6 is a block diagram showing a configuration example of a gate device of a conventional power converter of this kind.

In FIG. 6, a plurality (four in the figure) of semiconductor switching elements SW1, SW2, SW3, SW4
The gate device of the power neutral point clamp converter (hereinafter, referred to as an NPC converter) 4 including: a gate signal generation circuit 1, a gate logic circuit 2, and a gate circuit 3 I have.

The NPC converter is an NPC converter,
It is used as a generic term for NPC converter converters.

An on / off signal, which is a gate pulse signal of a semiconductor switching element output from the gate signal generation circuit 1, is input to a gate logic circuit 2, and is input to a gate circuit 3 after the gate pulse signal is formed. N
Semiconductor switching elements SW1 and SW of PC converter 4
2, SW3 and SW4.

The gate logic circuit 2 receives a gate pulse signal from the gate signal generation circuit 1 and secures a minimum pulse width, a dead time, a minimum zero time, and the like. SW
(3) The gate pulse signal is processed so as to secure the switching time of SW4.

Further, an interlock exists at the last stage of the gate logic circuit 2.

This interlock changes the gate pulse signal so as to avoid the switching state of the semiconductor switching element because the switching state of the semiconductor switching element is inappropriate in the circuit configuration of the NPC converter 4.

That is, for example, if the output of one phase is “1 → −
To shift to "1", the gate pulse signal is changed so that the interlock assumes a state of "1 → 0 → -1" and one end of 0.

[0013]

However, in such a conventional gate device of an NPC converter, as described above, noise is applied to the gate pulse signal,
The switching states are 1 (the semiconductor switching elements SW1 and SW2 are on in FIG. 6), 0 (the semiconductor switching elements SW2 and SW3 are on in FIG. 6), and -1 (the semiconductor switching elements SW3 and SW4 are on in FIG. 6). If a gate pulse pattern other than the three states is input to the gate circuit 3, the interlock becomes extremely difficult.

Such an inappropriate gate pulse pattern is caused not only by noise, but also by an unexpected pulse generated due to a switching delay or a switching speed difference of a logic element, a delay due to a capacity of an electric signal line, or a contact failure. Can occur.

An object of the present invention is to provide a highly reliable power converter gate device capable of preventing erroneous gate pulses due to noise.

[0016]

In order to achieve the above object, a gate device of a power converter according to the invention according to claim 1 is an NPC converter comprising a plurality of semiconductor switching elements. A gate signal generating circuit for generating an on / off signal that is a gate pulse signal of a semiconductor switching element, and a gate pulse signal output from the gate signal generating circuit as inputs, and switching of the semiconductor switching element with respect to the gate pulse signal A gate logic circuit that is processed so as to secure time and is provided to the gate circuit of the NPC converter, and is provided between the gate signal generation circuit and the gate logic circuit, and the semiconductor switching element of each arm of the NPC converter is incompatible. A non-conforming gate pattern elimination circuit that eliminates the combination of Eteiru.

Therefore, in the gate device of the power converter according to the present invention, the combination of the gate pulse pattern signal of the semiconductor switching element of each arm of the NPC converter that is not suitable is eliminated. At the input section of the pulse signal, the gate pulse pattern of each arm of the NPC converter can be removed from the gate pulse pattern other than the three possible switching states that the NPC converter can take. The signal processing is performed in a state where the malfunction signal has been removed, and a highly reliable gate device can be realized.

According to a second aspect of the present invention, there is provided a gate device of a power converter according to the first aspect of the present invention, wherein the semiconductor switching element of each arm of the NPC converter is provided. When it is determined that the gate pulse pattern signal is incompatible with the gate logic circuit, a gate pattern holding circuit that holds the gate pulse pattern signal of the previous stage is added between the mismatched gate pattern removal circuit and the gate logic circuit. I have.

Therefore, in the power converter gate device according to the present invention, when the gate pulse pattern signal of the semiconductor switching element of each arm of the NPC converter is determined to be incompatible with the gate logic circuit, ,
By holding the gate pulse pattern signal of the previous stage, an appropriate gate pulse pattern is output, and the operation can be continued without stopping the system.

On the other hand, a gate device for a power converter according to the invention according to claim 3 is an on / off gate which is a gate pulse signal of a semiconductor switching element in an NPC converter including a plurality of semiconductor switching elements. A gate signal generation circuit that generates an off signal as a 1-bit signal, and a gate pulse signal output from the gate signal generation circuit are input, and the gate pulse signal is processed so as to secure the switching time of the semiconductor switching element. Of a gate logic circuit provided to the gate circuit of the NPC converter and a bit pattern signal of an incompatible gate of the semiconductor switching element of each arm of the NPC converter provided between the gate signal generation circuit and the gate logic circuit And a digitally incompatible gate pattern removing circuit for removing the pattern.

Therefore, in the power converter gate device according to the third aspect of the present invention, the combination of the bit pattern signals of the inappropriate gates of the semiconductor switching elements of each arm of the NPC converter is eliminated. At the gate pulse signal input unit, the bit pattern of each arm of the NPC converter can be removed from the bit pattern other than the three possible switching states of the NPC converter. In the subsequent gate logic circuit, noise and malfunction signal of the control circuit can be removed. Signal processing is performed in a state where is removed, and a highly reliable gate device can be realized.

According to a fourth aspect of the present invention, there is provided a gate device for a power converter according to the third aspect of the present invention, wherein the semiconductor switching element of each arm of the NPC converter is provided. In the bit pattern signal of the gate of the above, when it is determined that the bit pattern signal of the next stage is incompatible with the gate logic circuit, the digital gate pattern holding circuit holding the bit pattern signal of the current stage is referred to as a digital incompatible gate pattern removal circuit. It is added between the gate logic circuit.

Therefore, in the gate device of the power converter according to the present invention, when the bit pattern signal at the next stage is determined to be unsuitable for the gate logic circuit, the bit pattern signal at the current stage is held. By doing so, an appropriate bit pattern is output, and the operation can be continued without stopping the system.

According to a fifth aspect of the present invention, there is provided a gate device for a power converter according to the third aspect of the present invention, wherein the semiconductor switching element of each arm of the NPC converter is provided. When it is determined that the bit pattern signal of the next stage is incompatible with the gate logic circuit, the bit pattern signal of the current stage is compared with the bit pattern signal of the next stage. A gate pattern estimating circuit for estimating and outputting a next-stage bit pattern signal suitable for the gate logic circuit from a signal change is added between the digitally incompatible gate pattern removing circuit and the gate logic circuit.

Therefore, in the gate device of the power converter according to the present invention, in the bit pattern signal of the gate of the semiconductor switching element of each arm of the NPC converter, the bit pattern signal of the next stage is a gate logic. If it is determined that the bit pattern signal is incompatible with the circuit, the current bit pattern signal is compared with the next-stage bit pattern signal, and the next-stage bit pattern signal suitable for the gate logic circuit is estimated from a signal change of at least 2 bits. Output, a 1-bit signal gives an erroneous signal due to a delay due to the capacitance of the electric signal cable or a poor contact of one line, and when a bit pattern is determined to be inappropriate, a signal change of 2 bits or more is generated. If there is, the bit pattern of one arm of the NPC converter can be inferred. Output to, can be performed to continue the operation without stopping the system.

[0026]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram showing a configuration example of a gate device of an NPC converter according to the present embodiment. The same parts as those in FIG. The description will be omitted, and only different portions will be described here.

That is, as shown in FIG. 1, the gate device of the NPC converter according to the present embodiment is provided between the gate signal generation circuit 1 and the gate logic circuit 2 in FIG. Is added.

The non-conforming gate pattern removing circuit 5
Semiconductor switching element SW of each arm of C converter 4
The combination of gate pulse pattern signals that are not suitable for SW1, SW2, SW3, and SW4 are eliminated.

Next, the operation of the gate device of the NPC converter according to the present embodiment configured as described above will be described.

In FIG. 1, a gate pulse signal from a gate signal generation circuit 1 is input to a gate logic circuit 2 and, after the gate pulse signal is formed, is input to a gate circuit 3 and a semiconductor switching element of an NPC converter 4 S
It is output to W1, SW2, SW3 and SW4.

The input section of the gate logic circuit 2 is provided with a non-conforming gate pattern removing circuit 5.

The gate pulse signal from the gate signal generation circuit 1 is input to the gate logic circuit 2 through a relatively long electric signal line.

During this period, the gate pulse pattern may change due to noise or the like.

In the NPC converter 4, there are only three possible gate pulse patterns for each arm.

Therefore, immediately before the gate pulse signal is input to the gate logic circuit 2, the non-conforming gate pattern removing circuit 5 is provided, and it is determined whether or not there is a non-conforming gate pulse pattern other than the three types of gate pulse patterns. .

As a result, in the case of a non-conforming gate pulse pattern, the gate pulse signal in the previous stage is maintained as it is, or the non-conforming gate pulse pattern is converted into three predetermined conforming gate pulse patterns to form a new gate pulse signal. Conversion such as a pulse signal is performed.

As described above, the NP according to the present embodiment
In the gate device of the C converter, as for the gate pulse pattern of each arm of the NPC converter 4 at the gate pulse signal input portion of the gate logic circuit 2, a gate pulse pattern other than the three possible switching states that the NPC converter 4 can take is determined. The signal processing is performed in a state where noise and a malfunction signal of the control circuit have been removed in the gate logic circuit 2 thereafter, so that a highly reliable gate device can be realized.

(Second Embodiment) FIG. 2 is a block diagram showing a configuration example of a gate device of an NPC converter according to the present embodiment. The same parts as those in FIG. The description will be omitted, and only different portions will be described here.

That is, the gate device of the NPC converter according to the present embodiment comprises a gate pattern holding circuit 6 between the non-conforming gate pattern removing circuit 5 and the gate logic circuit 2 in FIG. Is added.

The gate pattern holding circuit 6 includes semiconductor switching elements SW1 and SW of each arm of the NPC converter 4.
When it is determined that the gate pulse pattern signals of SW2, SW3, and SW4 are incompatible with the gate logic circuit 2, the gate pulse pattern signal of the previous stage is held.

Next, the operation of the gate device of the NPC converter according to the present embodiment configured as described above will be described.

The description of the operation of the same parts as in FIG. 1 is omitted, and only the operation of the different parts will be described here.

In FIG. 2, when the non-conforming gate pattern removing circuit 5 determines that the gate pulse signal from the gate signal generating circuit 1 is a non-conforming gate pulse pattern, it is held as a gate pulse pattern by the gate pattern holding circuit 6. The gate pulse pattern of the previous stage is output as a gate pulse signal.

As a result, an appropriate gate pulse pattern is output, and the operation can be continued without stopping the system.

If the non-conforming gate pulse pattern continues to be generated and the gate pattern holding circuit 6 keeps outputting the same gate pulse pattern, the operation of the converter becomes abnormal and the whole system stops.

As described above, the NP according to the present embodiment
With the gate device of the C converter, in addition to obtaining the same effects as in the first embodiment described above, it is possible to continue the operation without stopping the system.

(Third Embodiment) FIG. 3 is a block diagram showing a configuration example of a gate device of an NPC converter according to the present embodiment. The same parts as those in FIG. The description will be omitted, and only different portions will be described here.

That is, the gate device of the NPC converter according to the present embodiment is, as shown in FIG. 3, provided between the gate signal generation circuit 1 and the gate logic circuit 2 in FIG. 7 is added.

The digitally incompatible gate pattern removing circuit 7 removes a combination of bit pattern signals of incompatible gates of the semiconductor switching elements SW1, SW2, SW3, SW4 of each arm of the NPC converter 4.

Next, the operation of the gate device of the NPC converter according to the present embodiment configured as described above will be described.

In FIG. 3, in gate signal generating circuit 1, semiconductor switching elements SW1, SW2, SW
3, the switching state of SW4 is digitized as a 1-bit signal (for example, ON is 1 and OFF is 0), and one arm has 4 bits.

The digitized gate pulse signal from the gate gate signal generation circuit 1 is input to the gate logic circuit 2, where the gate pulse signal is formed, and then input to the gate circuit 3. Output to the switching elements SW1, SW2, SW3, SW4.

At the input of the gate logic circuit 2, a digitally incompatible gate pattern removing circuit 7 is provided.

The gate pulse signal from the gate signal generation circuit 1 is input to the gate logic circuit 2 through a relatively long electric signal line.

The bit pattern may change during this period due to noise or the like.

In the NPC converter 4, each arm can have only three possible bit patterns (SW1-SW).
4: 1100, 0110, 0011).

Therefore, immediately before the gate pulse signal is input to the gate logic circuit 2, the digital non-conforming gate pattern removing circuit 7 is provided to determine whether there is a non-conforming bit pattern other than the three types of bit patterns.

As a result, in the case of an unsuitable bit pattern, the gate pulse signal of the previous stage is maintained as it is,
Alternatively, conversion is performed such as converting the non-conforming bit pattern into three predetermined conforming bit patterns to obtain a new gate pulse signal.

As described above, the NP according to the present embodiment
In the gate device of the C converter, the bit pattern of the gate of each arm of the NPC converter 4 at the gate pulse signal input portion of the gate logic circuit 2 is different from the possible switching state that the NPC converter 4 can take. The gate logic circuit 2 performs signal processing in a state where noise and a malfunction signal of the control circuit have been removed, and a highly reliable gate device can be realized.

Also, since it is digital, a circuit can be assembled very easily.

(Fourth Embodiment) FIG. 4 is a block diagram showing a configuration example of a gate device of an NPC converter according to the present embodiment. The same parts as those in FIG. The description will be omitted, and only different portions will be described here.

That is, the gate device of the NPC converter according to the present embodiment, as shown in FIG. 4, has a digital gate pattern holding circuit between the digital incompatible gate pattern removing circuit 7 and the gate logic circuit 2 in FIG. The circuit 8 is added.

The digital gate pattern holding circuit 8
Semiconductor switching element S of each arm of NPC converter 4
When it is determined that the bit pattern signal of the gate of W1, SW2, SW3, and SW4 is not suitable for the gate logic circuit 2, the bit pattern signal of the current stage is held.

Next, the operation of the gate device of the NPC converter according to the present embodiment configured as described above will be described.

The description of the operation of the same parts as in FIG. 3 is omitted, and only the operation of the different parts will be described here.

In FIG. 4, when the gate pulse signal from the gate signal generation circuit 1 is determined to be an incompatible bit pattern by the incompatible digital gate pattern removing circuit 7, the digital gate pattern holding circuit 8 holds it as a bit pattern. The previous bit pattern is output as a gate pulse signal.

As a result, an appropriate bit pattern is output, and the operation can be continued without stopping the system.

If an incompatible bit pattern continues to be generated and the digital gate pattern holding circuit 8 keeps outputting the same bit pattern, the operation becomes abnormal as a converter, and the whole system stops.

As described above, the NP according to the present embodiment
With the gate device of the C converter, in addition to obtaining the same effects as in the third embodiment described above, it is possible to continue the operation without stopping the system.

(Fifth Embodiment) FIG. 5 is a block diagram showing a configuration example of a gate device of an NPC converter according to the present embodiment. The same parts as those in FIG. The description will be omitted, and only different portions will be described here.

That is, the gate device of the NPC converter according to the present embodiment comprises a gate pattern estimating circuit between the digital non-conforming gate pattern removing circuit 7 and the gate logic circuit 2 in FIG. 9 is added.

The gate pattern estimating circuit 9 includes the semiconductor switching elements SW 1 and SW of each arm of the NPC converter 4.
In the bit pattern signals of the gates of SW2, SW3 and SW4, when it is determined that the bit pattern signal of the next stage is not suitable for the gate logic circuit 2, the bit pattern signal of the current stage is compared with the bit pattern signal of the next stage. hand,
A next-stage bit pattern signal suitable for the gate logic circuit 2 is estimated and output from a signal change of at least 2 bits.

Next, the operation of the gate device of the NPC converter according to the present embodiment configured as described above will be described.

The description of the operation of the same parts as in FIG. 3 is omitted, and only the operation of the different parts will be described here.

In FIG. 5, when a 1-bit signal generates an erroneous signal due to a delay due to a capacitance of an electric signal line, a one-line contact failure, or the like, and it is determined that the bit pattern is inconsistent, a signal change of at least 2 bits occurs. For example, a bit pattern of one arm of the NPC converter 4 is estimated.

That is, for example, although the gate signal generation circuit 1 outputs (1100), (100) is output due to a contact failure of the electric signal line of the semiconductor switching element SW2.
It is assumed that the gate pulse signal 0) is input to the gate logic circuit 2.

At this time, the output of the NPC converter 4 is changed from “1 →
0 ", the semiconductor switching element S
W1 is turned off, the semiconductor switching element SW3 is turned on, and the bit pattern changes to (0110).

However, (0010) is actually input due to the contact failure.

Then, (1000) → (0010)
From the change of the two bits of the semiconductor switching elements SW1 and SW3, it can be inferred that the semiconductor switching element SW2 is 1 instead of 0.

As described above, even when the bit pattern is determined to be inconsistent, NP
The bit pattern of one arm of the C converter 4 can be estimated, and a suitable bit pattern can be output.

As described above, the NP according to the present embodiment
With the gate device of the C converter, in addition to obtaining the same effects as in the third embodiment described above, the operation is continued without stopping the system by outputting a suitable estimated bit pattern. It becomes possible.

[0083]

As described above, according to the present invention, the gate pulse pattern or bit pattern of each arm of the NPC converter at the gate pulse signal input unit is set to NP.
Since the gate pulse pattern or the bit pattern other than the three switching states that can be taken by the C converter are removed, the signal processing is performed in the subsequent gate logic circuit in a state where noise and a malfunction signal of the control circuit are removed. This makes it possible to realize a highly reliable gate logic circuit of the power converter.

[Brief description of the drawings]

FIG. 1 shows a first embodiment of a gate device for an NPC converter according to the present invention.
FIG. 2 is a block diagram showing an embodiment.

FIG. 2 shows a second embodiment of the gate device of the NPC converter according to the invention.
FIG. 2 is a block diagram showing an embodiment.

FIG. 3 shows a third embodiment of the gate device of the NPC converter according to the present invention.
FIG. 2 is a block diagram showing an embodiment.

FIG. 4 shows a fourth embodiment of the gate device of the NPC converter according to the present invention.
FIG. 2 is a block diagram showing an embodiment.

FIG. 5 shows the fifth embodiment of the gate device of the NPC converter according to the present invention.
FIG. 2 is a block diagram showing an embodiment.

FIG. 6 is a block diagram showing a configuration example of a gate device of a conventional NPC converter.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Gate signal generation circuit 2 ... Gate logic circuit 3 ... Gate circuit 4 ... NPC converter 5 ... Incompatible gate pattern removal circuit 6 ... Gate pattern holding circuit 7 ... Digital incompatible gate pattern removal circuit 8 ... Digital gate pattern holding circuit 9 ... Gate pattern estimating circuit SW1, SW2, SW3, SW4 ... Semiconductor switching element.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Hironobu Kim 1 Toshiba-cho, Fuchu-shi, Tokyo F-term in Fuchu Works, Toshiba Corporation (reference) 5H007 AA01 AA06 CA03 CB05 CC04 CC06 CC14 DB03 DB07 5H740 BA01 BB05 BB08 BB09 JA25 NN01

Claims (5)

[Claims] 1. An NPC (neutral point clamp) converter including a plurality of semiconductor switching elements, a gate signal generation circuit for generating an on / off signal as a gate pulse signal of the semiconductor switching elements, and A gate logic which receives a gate pulse signal output from the gate signal generation circuit, processes the gate pulse signal so as to secure a switching time of the semiconductor switching element, and provides the gate pulse signal to a gate circuit of the NPC converter. A non-conforming gate pattern removing circuit provided between the gate signal generating circuit and the gate logic circuit for removing a combination of non-conforming gate pulse pattern signals of the semiconductor switching elements of each arm of the NPC converter. A gate of a power converter, comprising: apparatus. 2. The gate device for a power converter according to claim 1, wherein a gate pulse pattern signal of a semiconductor switching element of each arm of the NPC converter is determined to be incompatible with the gate logic circuit. And a gate pattern holding circuit for holding a gate pulse pattern signal at a previous stage is added between the incompatible gate pattern removing circuit and the gate logic circuit. 3. An NPC (neutral point clamp) converter comprising a plurality of semiconductor switching elements, a gate for generating an ON / OFF signal as a gate pulse signal of said semiconductor switching elements as a 1-bit signal. A signal generation circuit; a gate pulse signal output from the gate signal generation circuit; and a gate circuit for the NPC converter by processing the gate pulse signal so as to secure a switching time of the semiconductor switching element. A gate logic circuit provided between the gate signal generation circuit and the gate logic circuit for removing a combination of a bit pattern signal of an inappropriate gate of the semiconductor switching element of each arm of the NPC converter. And a non-conforming gate pattern removing circuit. The gate logic circuit of the power converter. 4. The gate device for a power converter according to claim 3, wherein, in a bit pattern signal of a gate of a semiconductor switching element of each arm of the NPC converter, a bit pattern signal of a next stage is the gate logic. A digital gate pattern holding circuit that holds a bit pattern signal at the present stage when it is determined that the circuit is incompatible with the circuit, is added between the digital incompatible gate pattern removing circuit and the gate logic circuit. Power converter gate device. 5. The gate device for a power converter according to claim 3, wherein, in the bit pattern signal of the gate of the semiconductor switching element of each arm of the NPC converter, the next bit pattern signal is the gate logic. When it is determined that the bit pattern signal is incompatible with the circuit, the bit pattern signal at the current stage is compared with the bit pattern signal at the next stage. A gate device for a power converter, wherein a gate pattern estimating circuit for estimating and outputting is added between the digitally incompatible gate pattern removing circuit and the gate logic circuit.