JPS63288499A - Reset circuit - Google Patents

Abstract

PURPOSE:To automatically and instantaneously reset a shift register by detecting the error due to noise, etc., of a data accumulated in the shift register by means of an error detection circuit, and supplying its output to a NAND circuit together with an output from a pulse generator. CONSTITUTION:The titled circuit is provided with the shift register 20, the error detection means 30 to detect an error in a data accumulated in the shift register 20, the pulse generator 40 to generate repetitious pulses representing '1' and '0', and a reset signal generation means 50 to which an output from the means 30 and output from the means 40 are inputted and which outputs a signal to reset the data accumulated in the shift register 20. Therefore, in the event of an error in the data held in the shift register 20, the error is detected by the error detection means 30. By supplying the output from this means 30 and that from the pulse generation means 40 to the reset signal generation means, a signal to reset the shift register 20 is outputted. In such a way, the data held in the register 20 can be reset automatically and instantaneously.

Description

[Detailed Description of the Invention] C Overview] An error detection circuit detects errors due to noise etc. in the data accumulated in the shift register, and outputs a reset pulse by applying the output to the NAND circuit together with the output of the pulse generator. The shift register is automatically and instantaneously reset.

[Industrial application field]

The present invention relates to a circuit equipped with a shift register, and relates to an improvement of a circuit that regenerates data accumulated in the shift register.

It is desirable for such a reset circuit to be a circuit that can be automatically and instantaneously performed without requiring any human operation in terms of cost and the like.

[Conventional technology]

FIG. 3 is a diagram illustrating a conventional shift register centration method.

In FIG. 3, four flip-flops (hereinafter referred to as pp), FFI, FF2, FF3, and FF
A reset circuit for a shift register consisting of four components will be explained.

Connect the Q output of FFI to the D input of FF2, and
Connect the Q output of FF3 to the D input of FF3. And F
The Q output of F3 is connected to the D input of FF4, and the Q output of FF4 is connected to the D input of FFI.

Then, by inputting a clock to the C input of each FFI to FF4, the data held in the FFI is transferred to the FF2, and the data held in the FF2 is transferred to the FF3.

In this way, data is transferred sequentially, and the data held in the FF4 is transferred back to the FFI.

Then, outputs 1 to 4 are extracted from the Q output of each FPI-FF4 and used as switching signals for line switching in maintenance of telephones, etc.

Now, assume that this shift register holds data of "1000". That is, “1” for FFI, FF2 to FF4
Assume that the data “0” is held in the “0” data. Suppose, for example, that the data held in FF3 becomes "l" due to noise or the like.

This error is detected by a subsequent circuit (not shown) and reset by human operation.

That is, this is performed by applying a predetermined voltage to the cent terminal (hereinafter referred to as S) and reset terminal (hereinafter referred to as R) of the FFI to PP4. In this case, FPI's Sl
And R of FF2 to FF4 is grounded.

On the other hand, by adding 5V as vl to R of FFI, for example,
The data “l” is held in Fl. Also, FF
O2 is added as v2 to S of FF2 to FF4 (that is, grounded) so that data of "0" is held.

After that, the voltage of vl is disconnected from R, and the voltage of ν2 is disconnected from S.

In this way, the shift register was reset.

[Problem that the invention seeks to solve]

However, the above-mentioned conventional reset method requires manual operation, which increases the number of operating points and increases costs.

[Means for solving problems]

The above problem is caused by the shift register 20 as shown in FIG.
, an error detection means 30 that detects errors in data stored in the shift register 20, a pulse generation means 4o that generates pulses repeating "1" and "0", and an output of the error detection means 30 and the pulse generation means 4o. Enter the output of
This problem is solved by the reset circuit of the present invention, which includes a reset signal generating means 50 that outputs a signal for resetting the data stored in the shift register 20.

[Effect]

In FIG. 1, when an error occurs in the data held in the shift register 20, the error detection means 3° detects the error. By applying the output of the error detection means 3o and the output of the pulse generation means 40 to the reset signal generation means, a signal for resetting the shift register 20 is output.

By applying this reset signal to the shift register 20, the data held in the shift register 20 can be automatically and instantaneously reset.

〔Example〕

FIG. 2 is a block diagram showing the configuration of a reset circuit according to an embodiment of the present invention.

The same reference numerals indicate the same objects throughout the figures.

In FIG. 2, the shift register 2 is F as in the conventional example.
It is assumed that it consists of four OFFs, FI to FF4, and has the same characteristics as the FP. Further, the ζ outputs of FFI to FF4 are the inverted Q outputs.

Then, the Q and Q outputs of PFI to FF4 are applied to NAND circuits 3-1 to 3-4 in the error detection circuit 3 by the wiring method shown in FIG.

The NAND circuit outputs “0” only when all input signals are “1”.
”, and when the input signal contains even one “0”, the output becomes “1”.

For this reason, for example, if the FFI holds the "1#" signal, the FFI
Considering the case where “0” signals are held in FF2 to FF4,
The Q output of FFI is "1#" and the ζ output is "0", while the Q output of FF2 to FF4 is "05" and the ζ output is "1", and the outputs of the NAND circuits 3-1 to 3-3 are "l",
The output of 3-4 becomes "0". When the outputs of these 3-1 to 3-4 are added to the NAND circuit 3-5, the output becomes "1" in this case. This is inverted via the inverter 3-6 and "02" is applied to one input a of the NAND circuit 5-1 in the reset signal generating circuit 5. The pulse generator 4 applies pulses that alternately repeat "1" and "0" over time.

Then, in this case, since "0" is added to the a input, 5
The output of -1 becomes "l". This is the case of normal operation. The output "1" of this NAND circuit 5-1 is inverted by the impark 5-2, set to "0", and added to R1 of PFI and S of FF2 to FP4 in the shift register 2.

In this case, FFI to FF4 do not change the signals held.

Now, assume that, in addition to the FPI, PF3 also holds "1" due to circuit noise or the like. Then, all outputs of NAN [1 circuit 3-1 to 3-4 become 41", and NAN
The output of the O circuit 3-5 becomes "0". Then, it is inverted via the inverter 3-6 to become "1m", and the NAND
Add to input a of circuit 5-1.

Then, in the NAND circuit 5-1, since the pulse of the output of the pulse generator 4 is added to the input, in this case, the output of the NAND circuit 5-1 becomes 0'' at the moment of l+1# of the pulse, and the inverter 5-2 is It is inverted to become “l” through FFI.
By adding to R1 and S of FF2 to FF4, F
FI is reset to hold a 1'' signal, and FF2 to FF4 are reset to hold a 0'' signal.

In addition, in the above explanation, “FFI to FF4 are set as initial values.
1000" signal, but the NAN
By changing the connection between the D circuit and the shift register, and between the output of the reset signal generation circuit and the S, R, etc. of each FF,
For example, it is also possible to set the initial value to "1001".

〔Effect of the invention〕

As described above, according to the present invention, the shift register can be reset automatically and instantaneously.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a block diagram showing the configuration of a reset circuit according to an embodiment of the present invention, and FIG. 3 is a diagram explaining a conventional shift register reset method. In the figure, 20 is a shift register, 30 is an error detection means, 40 is a pulse generation means, and 50 is a reset signal generation means. & Inui 9B fishing rule, grip 1st side 9 foot, Shube φ's shift ratio 9 lyse, 7H Ji is also begging 9
Tsukizurokuni 3 illustration

Claims (1)

[Claims] A shift register (20), an error detection means (30) for detecting errors in data accumulated in the shift register (20), and a pulse for generating repetitive pulses of "1" and "0". generation means (40), the output of the error detection means (30) and the pulse generation means (40);
1. A reset circuit comprising: a reset signal generating means (50) which inputs the output of the shift register (20) and outputs a signal for resetting data accumulated in the shift register (20).