JPH02137015A - Analog/digital converter - Google Patents

Abstract

PURPOSE:To minimize the influence of the noises produced from a control circuit of a large scale and an output buffer by preparing an A/D conversion circuit, a control circuit, a clock delay circuit, and a noise detecting circuit onto the same semiconductor substrate and securing a noise detecting period before the A/D conversion via those circuit blocks. CONSTITUTION:When an A/D conversion instruction is given to a control circuit 4 of an A/D converter, the analog input of an A/D conversion circuit 7 is con nected to an earth potential in the circuit 4. While the delay value of a clock delay circuit 6 is set at A, and the conversion result of the circuit 7 is outputted to the circuit 4 from the digital output 11 to be stored in a noise detecting circuit 5. Furthermore the delay value of the circuit 6 is set at B, C..., and the conversion result of the circuit 7 is repetitively stored in the circuit 5. When all delay values of the circuit 6 are set, the delay value stored in the circuit 5 with the least noise value of the A/D conversion is detected. Then the noise of the detected delay value is minimized for execution of the A/D conversion.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an A/D converter, and in particular to an A/D converter that can be used with a large-scale control circuit (for example, a 4-bit or 8-bit microcomputer) using semiconductor integrated circuit technology. A integrated on the same substrate
/D converter.

[Conventional technology]

An example of a conventional A/D converter is an A/D converter that uses a sequential comparison method and has an eight-person multiplexer.
A D converter has been realized. The conversion time of this A/D converter was 26.7 microns.

[Problem to be solved by the invention]

The conventional A/D converter described above is sensitive to noise generated from control circuits as process technology advances.

An example of what kind of noise is generated is Yisivi.
'DESIGN OF MOSVLS!' by dis et al.
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IONS”R-entice-Hall Inc 19
85 PP 321-324. When 8-bit output buffers operate simultaneously, a current of about 25 mA flows, and if the lead inductance is 50 nH, a noise of 250 mV is generated in the power supply line.

Such power supply noise is caused by the refinement of the process, which improves the driving ability of the MOS transistors used, and the internal gates increasingly generate large noise.

Conventionally, methods to prevent this power supply noise include separating the power supply wiring between the control circuit (microcomputer) and the A/D converter to prevent mutual interference, or terminating the substrate potential and well potential with low impedance to prevent noise induction. Methods were considered to prevent this from occurring and to adopt a fully differential configuration.

However, as the clock speed increases, there are problems such as deterioration of noise resistance and an increase in the amount of noise generated as the scale of integration increases.

[Means to solve the problem]

The A/D converter of the present invention has an A/D conversion circuit, a control circuit, a clock delay circuit, and a noise detection circuit on the same semiconductor substrate. These circuit blocks are interconnected to form a noise detection period prior to A/D conversion.

That is, in the present invention, a noise detection period is provided before the A/D conversion circuit operates, and F) the operating clock of the A/D conversion circuit is optimized by the control circuit, the clock delay circuit, and the noise detection circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is an explanatory diagram of a block equivalent circuit according to an embodiment of the present invention.

If the control circuit 4 is provided with an analog multiplexer (not shown), the analog input terminal 1 becomes a plurality of terminals. The digital input/output terminal 2 is shown as a representative, and represents a plurality of terminals including a digital input terminal and a digital output terminal, and is used for inputting and outputting digital signals to the control circuit 4. Clock terminal 3 is the control circuit 4
It is used as an operation clock for the A/D operation clock 8 and is supplied to the A/D conversion circuit 7 as an A/D operation clock 8 via a clock delay circuit 6.

The A/D conversion circuit 7 is selected by an analog multiplexer (not shown) in the control circuit 4 and receives an analog signal from an analog input 9 . The operation of the A/D conversion circuit 7 is controlled by a control signal 10, and the A/D converted digital signal is outputted from the digital output 11 to the control circuit 4, and the A/D converted from the digital input/output terminal 2 as necessary. Output to the outside of the converter.

The noise detection circuit 5 has a function of detecting and storing the amount of delay of the clock delay circuit that minimizes the noise level during the noise detection period.

The A/D converter of FIG. 1 operates as follows.

■ An A/D conversion command is input to the control circuit 4.

(2) Connect the analog input of the A/D conversion circuit 7 in the control circuit 4 to the ground potential.

(2) Set the delay amount of the clock delay circuit 6 to A.

■ Digital output 11 of the conversion result of the A/D conversion circuit 7
The signal is outputted to the control circuit 4 and stored in the noise detection circuit 5.

■ Set the delay amount of the clock delay circuit 6 to B, C, etc., and repeat steps ■ and ■.

(2) When all the delay amounts of the clock delay circuit 6 are completed, the delay amount that minimizes the amount of A/D conversion noise stored in the noise detection circuit 5 is detected.

■ A/
Start D conversion operation.

In this way, before starting the A/D conversion operation, the A/D operation clock 8 that causes the minimum noise in the noise detection period is It can be supplied to the D conversion circuit 7 and operated.

Incidentally, an explanatory diagram of an equivalent circuit of a commonly used clock delay circuit is shown in FIG. The operating clock is input from input 21. In this example, the delay circuit 23 is composed of two stages of inverters, and a transfer gate 24 is provided at each output. For example, the amount of inverter delay is 2n per stage.
When s is set, the delay amount of Ons, 4ns, 8ns, and 16ns can be selected. Moreover, any number of stages is possible, and the required delay step and delay range can be selected. Furthermore, A/
When the wiring of the D-operation clock 8 is long, it is preferable to provide a buffer after the transfer gate.

FIG. 3 is an explanatory diagram of a block equivalent circuit of another embodiment of the present invention.

This embodiment is a modification of the noise detection circuit 5 in the embodiment of the present invention.

In the embodiment shown in FIG. 1, when the optimum delay amount is detected during the noise detection period, the delay amount is selected immediately and the A/D
Conversion operation has started.

In the embodiment shown in FIG. 3, the configuration shown in FIG.
to be memorized. This is an example where there are four types of delay amounts explained in FIG. 2, and when the number of types of delay amounts increases, only those types are prepared.

With this configuration, the register groups 33, 34, 35, and 36 are transferred to the rear of the register group of each A/D conversion converter, so that three sets of A/D conversion outputs are always provided. In this way, it is possible to determine the amount of delay that minimizes the amount of noise by summing the register groups 33, 34, 35 and 36.

Since it is possible to detect the average value of the noise amount in this way, noise resistance against impulse noise can be enhanced.

Furthermore, in certain applications, it may be effective to make a determination based on three-value peak values instead of average value detection, and this can be achieved by simply changing the detection circuit.

〔Effect of the invention〕

As explained above, the present invention provides a noise detection period consisting of a control circuit, a clock delay circuit, and a noise detection circuit before A/D conversion, thereby reducing power supply noise generated from large-scale control circuits and output buffers. This has the advantage of providing an A/D converter with excellent accuracy and minimal influence.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of a block equivalent circuit of an embodiment of the present invention,
FIG. 2 is an explanatory diagram of an equivalent circuit of a clock delay circuit, and FIG. 3 is an explanatory diagram of a block equivalent circuit of a second embodiment of the present invention. 1...Analog input terminal, 2...Digital input/output terminal, 3...Clock terminal, 4...
...control circuit, ...noise detection circuit, 6.
... Clock delay circuit, 7 ... A/D conversion circuit, 8 ... A/D operation clock, 9 ...
... Analog input, lO ... Control signal, 11
...Digital output, 21...Input,
22...Output, 23...Delay circuit, 2
4...Transfer gate, 31...
・Digital output, 32...Multiplexer,
33, 34, 35. 36... Register group.

Claims (1)

[Claims] An A/D converter comprising an A/D conversion circuit, a control circuit, a clock delay circuit, and a noise detection circuit, and having a noise detection period before A/D conversion.