JPS5999270A - Testing input circuit - Google Patents

Abstract

PURPOSE:To eliminate the need for a terminal exclusive to a test, to reduce the cost of the test, and to input a testing input without malfunction by inputting an expectated waveform which is set previously by a waveform generating circuit through a comparing circuit, and invalidating and fixing the output of an input circuit in normal operation. CONSTITUTION:Respective expectated pulses of the testing input circuit 10 are inputted from testing input signal terminals IN1 and IN2 to stop input/output functions in normal operation to the testing input signal terminals IN1 and IN2. Then, a testing input signal is inputted from the testing output terminal IN1 to the testing input terminal 10 so as to switch composite gates 14 and 15 for switching to a test mode, and the output of a testing output terminal TO1 is set to 1. A circuit 12 to be tested is controlled directly by inputting the testing signal from the testing input signal terminal IN2, and the output of the circuit 12 to be tested is outputted to a terminal OUT directly. Input signals to the testing input signal terminals IN1 and IN2, however, should be synchronized with a clock signal CLK.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a test input circuit for a logic integrated circuit in which input/output terminals in a normal operating state can be used as test input terminals in a test state.

(Conventional configuration and its problems) Testing costs are extremely important in semiconductor integrated circuits, and in the past, dedicated terminals were provided for testing in order to increase testing efficiency, but increasing the number of terminals reduced assembly costs. Furthermore, when a semiconductor integrated circuit is packaged in a package with a limited number of terminals, it may not be possible to provide terminals exclusively for testing. On the other hand, conventionally, input/output terminals are used as test input terminals. In that case, the test input itself is “1” or !
The test input circuit makes a judgment every time θ'', but the input circuit during normal operation also judges the test input in 1-bit units, so a 1-bit erroneous input may cause the input circuit output during normal operation to change. The drawback is that there is a risk of malfunction.

(Objective of the Invention) The present invention eliminates the above-mentioned drawbacks, and makes it possible to input test inputs to input/output terminals during normal operation without malfunction, without providing test-only terminals and therefore without increasing assembly costs. hand,
Its purpose is to test logic integrated circuits.

(Structure of the Invention) The present invention provides an n-ary system (however,
n≧2) a counter, a waveform generation circuit that generates periodic pulses divided into n bit units, and m pieces (however, 2 ≦m≦n), a clock circuit that generates a lock signal necessary for detecting the output of the comparison circuit every n bits, and a clock circuit that generates a lock signal necessary for detecting the output of the comparison circuit every n bits; It is composed of m waveform conversion circuits that determine waveforms, and an output control circuit that controls the output of the input/output circuit during normal operation based on the output of the waveform conversion circuits.

(Description of Embodiment) FIG. 1 is a block diagram showing the configuration of an embodiment of the test input circuit of the present invention, in which 1 is an n-ary counter, 2 is a waveform generation circuit, 3 is a clock circuit, and 4 is a comparison circuit. , 5 is a waveform conversion circuit, 6 is an output control circuit, CLK is a PTS signal or its terminal, IN, ~Nm is a test input signal or its input terminal, NT, ~NTm is an output control signal or its terminal. Output terminals To and Ton1 indicate test output signals or their output terminals.

FIG. 2 shows an embodiment of the test input circuit of the present invention in which n=4, in which seven input circuits are used in normal operation, 8 is a depletion type transistor, and 9 is an enhancement type transistor.

The operation will be explained below with reference to FIG.

During the test, after resetting the n-ary counter 1 and the output control circuit 6 using the reset signal R and setting the initial values, the n-ary counter is operated using the external clock signal CLK, and the output control circuit 2 is set in advance by the external clock signal CLK. Expected value waveform P of test input signal IN, ~■Nm, ~P4. to occur. Further, the clock circuit 3 synchronizes with the clock signal CT and generates the p clock signals φ1 to φ4. The inputs IN and ~IN4 from the input terminals IN and ~IN4 and the outputs P+1 to PI4 of the waveform generation circuit 2 are compared by the corresponding comparison circuits 4, and the outputs of the comparison circuits 4 are sent to the waveform conversion circuit 5.
The output is determined bit by bit using the output clock signals φ, .about.φ4, and then output as test output signals To, .about.To4 of 71++ or "θ" in units of n bits. Further, the output control circuit 6 receives the test output signals To, .
and its output N, ~N4 is here LI
Fixed to M.

As described above, during testing, first of all, the expected value waveforms P1 to P4 are set in advance by the waveform generation circuit 2 through the comparison circuit 4.
By inputting , the output of the input circuit 7 during normal operation is controlled and disabled. ), then the test input signal is input to the input terminals IN, .

~TOm allows logic integrated circuits to be tested.

Figure 3 shows the waveforms at each point in Figure 2, where the test input signal IN and the expected value P of the waveform generation circuit 2
The process of determining 1 and 1 in units of 4 bits is shown.

If the input is as expected, there will be a delay of 4 bits and 4 bits will be 1'', and if the input is different from the expected value, it will be '0'.
” is output from the output terminal To of the waveform conversion circuit 5.

If it is not during a test, the test input signals IN, ~IN4 are outputs To, ~To4 from the waveform conversion circuit 5 as long as they are signals synchronized with the expected values P1 to P1 and the external clock CI.
Since it is 10l+, it will not cause malfunction during normal operation.

FIG. 4 shows an embodiment in which the test input circuit of the present invention is incorporated into a watch integrated circuit, where 10 is the test input circuit of the present invention, 11 and 13 are non-test circuits, and 12 is the test input circuit of the present invention. Test circuits 14 and 15 are switching composite gates.

First, each expected value pulse of the test input circuit 10 is inputted from the test input signal terminals IN and 1N2, and the normal input/output functions of the test input signal terminals IN and IN2 are stopped. Next, a test input signal is input from the test input signal terminal IN to the test input circuit 10 so as to switch the switching complex 6-gates 14 and 15 to the test mode, and the output from the test output terminal TO is set to 11.
When set to 1, the circuit under test 2 can be directly controlled by inputting from the test input signal terminal IN2, and the output of the circuit under test 12 can be directly output to the 0TJT terminal. In this case, as described above, the input signals of the test input signal terminals IN and N2 must be synchronized with the p-clock signal CLK.

(Effects of the Invention) As described above, according to the present invention, the logic circuit of the main body can be easily tested using only an external clock signal, and thereby the number of external terminals for testing does not increase.
Further, there are advantages such as reduction in test costs.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the test input circuit of the present invention, and FIG. 2 is a block diagram showing the configuration of an embodiment of the test input circuit of the present invention.
FIG. 3 is a diagram showing waveforms at each point in FIG. 2, and FIG. 4 is a diagram showing an example in which the test input circuit of the present invention is incorporated into a watch integrated circuit. It is. 1...N-ary counter, 2...
Song/waveform generation circuit, 3...Clock circuit, 4... River/comparison circuit, 5... Song/waveform conversion circuit, 6... Song/output control Circuit, 7...
Yamakawa: Input circuit during normal operation, 8: Depression type transistor, 9: Enhancement type transistor, 10: Input circuit for testing of the present invention , 11.13...
- Non-test circuit, 12... River... Circuit under test, 14° 15... Composite gate for switching.

Claims (1)

[Claims] An n-ary (however, n≧2) counter that receives an external clock signal as input, a waveform generation circuit that generates periodic pulses divided into n bits, and a waveform generator that generates the pulse input divided into n bits into the waveform. m pieces to be compared with the output of the generating circuit (however,
n≧m≧2), a 922 circuit that generates a signal with the power necessary to detect the output of the comparison circuit every n bits, and a 922 circuit that generates the output waveform of the comparison circuit and the output waveform of the comparison circuit of the clock circuit. 1. A test input/output circuit comprising: m waveform conversion circuits that perform determination based on output signals; and an output control circuit that controls input/output circuit output during normal operation based on the output of the waveform conversion circuits.