RU2010363C1 - Device for controlling permanent memory - Google Patents

Abstract

FIELD: computer technology. SUBSTANCE: AND gate 13, the fifth switch 16, the second comparison unit 15 which has to be current comparator, are brought into the device additionally. Output stage leakage current may be put under control in the third condition. Unit 5 provides logic operation of the device. When signal is detected in control output 14 of the device, the error is indicated and process of programming is interrupted. EFFECT: improved precision of control after effect of higher voltage programming pulses. 1 dwg

Description

 The invention relates to computer technology and can be used to control the correct programming of memory chips in programmers.

 A device similar to the invention controls the amplitude and duration of programming pulses. In addition, the use of an analog-to-digital converter for measuring the levels of output signals allows the rejection of programmed microcircuits according to specified levels of output signals. In this case, rejection can be carried out by changing the supply voltage of the microcircuits in a given tolerance field. The disadvantages include the fact that monitoring at given levels of output signals is carried out without connecting to a programmed load microcircuit, and that for an EPROM with a three-state type output (ZS), it is not possible to control a third state.

 The drawing shows a diagram of the proposed device and logical expressions explaining the operation of the control unit.

 The device for monitoring permanent memory contains the first 1, second 2, third 3 and fourth 4 keys, a control unit 5, a first power bus 6, a first 7, a second 8 and a third 9 restrictive elements, information input-output 10, the first comparison unit 11, the first group of 12 control inputs, the OR element 13, the control output 14, the second comparison unit 15, the fifth key 16 and the second group of 17 control inputs.

 The device operates as follows.

 In order for the permanent memory chip to perform a specific function in any device, certain information must be recorded in it. For this, programming pulses of the required amplitude and duration are generated, which are supplied in the programming mode to the information input of the microcircuit. After programming, it is necessary to check the microcircuit to make sure that the recorded information is correct, that the read signal levels correspond to the required values, that the output stages of the microcircuits are safe, which can be violated when programming with high voltage.

 Since the proposed device is designed to generate programming pulses and to control the microcircuit after programming, it works in two modes: shaping and control. In the general case, these modes follow one after another, i.e., after the code is written to any bit of the microcircuit, this discharge is monitored. If the control results are satisfactory, then the code is written to the next bit, and then its control. The actions are repeated until the entire memory chip (or its required part) is programmed and monitored. If the results of the control turn out to be unsatisfactory, then further programming of this microcircuit may not be continued, and the microcircuit itself should be discarded.

 The diagram and logical expressions in the drawing give an idea of the operation of the device.

 At the first input of the control unit 5, during programming and control, a level corresponding to the value of the information bit is set. When programming microcircuits like OK or ZS, the level “1” is set at the second input of the control unit 5, and the level “0” is set during control.

 When programming and monitoring microcircuits having an output of type OK, the level “0” is set at the third input of the control unit 5, and when programming and monitoring microcircuits with an output of type ЗС - level “1”.

 The control of the third state occurs if the level "0" is set at the second and fourth inputs of the control unit 5. If the second input is set to "1", and the fourth - level "0", then the entire device is reset.

 When programming and monitoring, the memory chip is connected with its information output to the information input-output 10 of the device.

 Programming pulse generation mode. In this mode, it is necessary to form a pulse of programming voltage at the information input-output 10 of the device, the magnitude of which depends on the recorded code of the number (0 or 1) and the type of memory chip. At the same time, the level “1” is set at the second input of the control unit 5, which corresponds to the recording mode of the number code in the memory chip.

 Before starting the operation of the device and before applying the programming voltage to the information input-output 10 of the device, all its elements are set to their original state. In this case, the key 3 is opened by the level "1", coming from the third output of the control unit 5, and the keys 1, 2, 4 and 16 are closed by the level "0", coming to the control inputs of the keys from the first, second, fourth and fifth outputs of the control unit, respectively (since at the second input of the control unit the level is set to "1", and at the fourth input it is set to level "0"). Thus, the information input-output 10 is connected to the bus zero potential.

 When applying to the bus 6 power corresponding to the type of memory chip programming voltage at the fourth input of the control unit 5, the level is set to "1". In this case, the key 3 is closed, disconnecting the information input-output 10 of the device from the zero potential bus. Now the state of the key 1 depends on the signal level at the first input of the control unit 5. If the number code corresponding to level "1" is supplied to the first input of the control unit 5, then the key 1 is opened and the voltage from the power bus 6 through the restrictive element 7 is supplied to the information input-output 10 of the device. If the number code corresponding to the level “0” is received at the first input of the control unit, then key 1 is closed and key 3 is open. In this case, the information input-output 10 of the device is connected to the bus of zero potential. Thus, depending on the code of the number entering the first input of the control unit 5, either the zero level or the corresponding level of programming voltage is present at the information input-output 10 of the device. The duration of the programming pulses generated at the input-output 10 of the device is determined by the duration of the signals supplied to the second input of the control unit 5.

 Control mode. In this mode, it is necessary to connect the corresponding limiting elements to the input-output 10 of the device, which specify the maximum load currents for this type of memory chip. In this case, the levels of the signals read from the memory microcircuit are estimated, and the safety of the output stages of the microcircuits that can be violated during programming is checked. In this mode, the level “0” is set at the second input of the control unit 5, which corresponds to the reading mode from the memory chip. Since the control mode in the device follows the formation mode and serves to verify the result of writing to a given bit of the memory microcircuit, the number code established at the first input of the control unit 5 in the formation mode continues to remain the same in the control mode.

 Consider the operation of the device when monitoring a memory chip with an output of type OK. When monitoring code 0, key 2 is opened with level "1", which is received at the control input of the key. In this case, a limiting element 8 is connected to the information input-output 10 of the device, which sets the maximum load current when reading code 0. The signal from the output of the memory chip through the information input-output 10 and the public key 16 (since the level 1 ", which allows simultaneous operation of the comparison unit 11) is fed to the input of the comparison unit 11, where it is compared with the reference voltage supplied via the bus 12 from the reference voltage source. The output of the comparison unit generates a signal of the result of the comparison, which through the element OR 13 enters the control output 14 of the device. If the level of the signal coming from the memory chip exceeds the level of the reference voltage, then a zero level error signal appears at the control output 14 of the device. When monitoring code 1, keys 2 and 16 are open (similar to that described) and key 4 with level "1", coming from the fourth output of control unit 5. In this case, using these keys, limiting elements 8 and 9 are connected to the information input-output 10 of the device. If the leakage currents of the memory microcircuit are more than acceptable, then the signal level from the microcircuit is lower than the reference voltage, which is recorded by the comparison unit 11, and on the control output 14 of the device a zero level error signal appears.

 Consider the operation of the device when monitoring memory chips with an output of type ZS. Here, control is carried out in two stages: control of the output signals of the memory microcircuit and control of the third state.

 When monitoring code 0, key 2 is opened, since the level “0” is set at the first and second inputs of the control unit 5, and level “1” is set at the third and fourth inputs (see logical expressions in the drawing). In this case, a limit element 8 is connected to the information input-output 10 of the device, which sets the limit value of the load current, when controlling code 1, the key 4 is opened (similar to that described) and with its help a limit element 9 is connected to the information input-output of the device 9. Signal control, coming from the output of the memory chip, and the formation of an error signal is carried out in the same way as in the control of chips with an output of type OK.

 The third state is monitored when the level “0” is set at the second and fourth inputs of the control unit 5, and the level “1” is set at the third input. At the same time, the level “1” is set at the sixth output of the control unit 5, and the level “0” is set at all other outputs. Thus, all keys are closed, the comparison unit 11 is inoperative, and the comparison unit 15 is in operation. The output of the memory chip through the information input-output 10 of the device is connected only to the block 15 comparison. The leakage current of the memory chip is supplied to the input of the comparison unit 15, which is a current comparator, for comparison with the reference value supplied via the bus 17 from the reference current source. If the current coming from the memory microcircuit exceeds the reference level, then the level 1 error signal from the output of the comparison unit 15 through the OR element 13 is fed to the control output 14 of the device.

 (56) Copyright certificate of the USSR N 1381593, cl. G 11 C 29/00, 1987.

 USSR copyright certificate N 1324068, cl. G 11 C 29/00, 1987.

Claims (1)

 A device for monitoring the read-only memory containing the first, second, third and fourth keys, the first control inputs of which are connected respectively to the first, second, third and fourth outputs of the third, third and fourth key outputs the key are connected respectively to the first and second power bus, and the outputs of the first and second key to the first conclusions of the first and second limiting elements, respectively, the second conclusions of which are interconnected, as well as with the third input of the third key and the first output of the third limiting element is the information input / output of the device, the second output of the third limiting element is connected to the second input of the fourth key, the first input of the control unit is connected to the first input of the second devices, characterized in that in order to increase the accuracy of the control, the fifth key, the second comparison unit and the OR element, the output of which is the control output of the device, are entered into it two, and the inputs are connected to the outputs of the first and second comparison blocks, the first input of the second comparison block and the first input of the fifth key are connected to the information input / output of the device, and the output of the fifth key is connected to the second input of the first comparison block, the fifth output of the control block the control input of the fifth key and the third input of the first comparison unit, the sixth output of the control unit is connected to the second input of the second comparison unit, the input group of which is the second group of control inputs of the device.