KR100487487B1 - Analog digital converter for reducing noise - Google Patents

Abstract

The present invention relates to an analog digital converter, and more particularly, to an analog digital converter having a latch circuit, comprising: a preamplifier for receiving an analog signal from the outside and amplifying the analog signal to a predetermined level; A first input terminal and a second input terminal receiving an analog signal generated by being amplified from the preamplifier; First latch means for storing and amplifying a signal transmitted to the first and second input terminals in response to a clock signal applied from the outside and outputting a first digital signal; Second latch means for storing and amplifying the signals transmitted to the first and second input terminals to output a second digital signal; Selection means for receiving the first digital signals and the second digital signals and selecting one of them; And an encoder for encoding and outputting digital signals generated through the selection means in synchronization with a system clock signal applied from the outside.

Such a device can reduce the effects of kickback noise.

Description

Analog-to-digital converter for reducing noise

The present invention relates to an analog-to-digital converter, and more particularly to an analog-to-digital converter for reducing noise.

An analog digital converter uses a latch circuit, and a latch circuit is a positive feedback operation. The difference between the analog signals is a power supply voltage (Vdd) or a ground voltage (Vss). As a circuit for amplifying at a level, an analog signal is converted into a digital signal and output.

1 is a circuit diagram showing the configuration of an analog-to-digital converter.

Referring to FIG. 1, the analog-to-digital converter includes a preamplifier 10, a latch circuit 20, and an encoder 30, and the latch circuit includes a switching circuit 21 and a positive feedback circuit 22. It is included. The preamplifier 10 amplifies the analog signal Ain applied from the outside, and the switching circuit 21 is turned on and off in response to the system clock signal QS. The positive feedback circuit 22 latches and amplifies and outputs an amplified analog signal when the switching circuit 20 is turned on. The encoder 30 receives a system clock signal QS and outputs the latched signal from the latch circuit 30. The encoded digital signals are encoded and output.

2A and 2B are voltage waveform diagrams of latch circuit input terminals in a normal case.

As shown in FIG. 2A, input signals complementary to each other are transmitted to the input terminals TP and TN of the latch circuit 30, and when it is set as a common mode, (TP + TN) / 2 As shown in Figure 2b. It should be noted that these are voltage waveform diagrams in the normal case.

3A is a waveform diagram of a system clock signal, and FIGS. 3B and 3C are voltage waveform diagrams of latch circuit input terminals in an abnormal case.

In the latch circuit 30 as described above, current flows rapidly due to on / off of the switch. Since the latch circuit 30 is composed of a positive feedback circuit including inverters and transistors M1 and M2, the voltages of the input terminals TP and TN are reduced by capacitor coupling of the transistors. As shown in the following figure, it moves along the system clock signal QS. This is kick back noise, and since the kick back noise affects the input stage rather than the output stage of the latch circuit 30, the operation accuracy of the circuit depends on the reduction of noise propagation to the input stage. This occurs equally even when the two input terminals TP and TN are in the common mode.

Another problem is that if the digital signal (Dout) level of the output terminal becomes smaller than a few mmV or less before the latch circuit 30 completes the positive feedback operation, it is not determined whether the digital output signal (Dout) is HIGH or LOW. A metastable period that does not occur will occur. This becomes more serious as it operates at higher speeds, since the latching period ends before the metastable period is over. This leads to an increase in the bit error rate (BER), which determines how well the latch operation is performed, along with an error in the output, thereby causing a problem of degrading the performance of the analog-to-digital converter. The above problems of kickback noise and metastable periods become more severe in devices requiring high speed operation of 100MHZ or more.

Accordingly, an object of the present invention is to provide an analog-to-digital converter having a latch circuit operating more stably by reducing the effects of kickback noise generation and metastable sections of the latch circuit.

(Configuration)

According to one aspect for achieving the above object, a pre-amplifier for receiving an analog signal from the outside and amplifying the signal to a predetermined level; A first input terminal and a second input terminal receiving an analog signal generated by being amplified from the preamplifier; First latch means for storing and amplifying signals transmitted to the first and second input terminals in response to a clock signal applied from the outside to output a first digital signal; Second latch means for storing and amplifying signals transmitted to the first and second input terminals in response to an inverted clock signal applied from the outside to output a second digital signal; Selection means for receiving the first digital signals and the second digital signals and selecting one of them; And an encoder for encoding and outputting digital signals generated through the selection means in synchronization with a system clock signal applied from the outside.

In this embodiment, the first latch means comprises: first switching means turned on in response to the clock signal; First positive feedback means for receiving signals generated from the preamplifier when the first switching means is turned on, latching them, and outputting first digital signals; Transistors connected in parallel between the first switching means and the first positive feedback means.

In this embodiment, the second latching means comprises: second switching means turned on and off in response to the inverted clock signal; Second positive feedback means for receiving a signal transmitted from the preamplifier when the second switching means is turned on, and latching it to output second digital signals; Transistors connected in parallel between the second switching means and the second positive feedback means.

In this embodiment, the first and second latch means are alternately operated by clock signals and inverted clock signals whose phases are only reversed.

In this embodiment, the clock signal and the inverted clock signal is characterized in that half the speed of the system clock signal.

By such a device, the kickback noise can be reduced and at the same time the influence of the metastable period can be reduced.

(Example)

Referring to the drawings according to the preferred embodiment of the present invention 4a to 4b, 5a, 5b as follows.

4A is a circuit diagram showing the configuration of an analog-digital converter according to a preferred embodiment of the present invention.

The analog-to-digital converter includes a preamplifier 110, a first latch circuit 120, a second latch circuit 130, a selection circuit 140, and an encoder 150. The preamplifier 110 amplifies and outputs an analog signal Ain applied from the outside, and if it is transmitted without being amplified, the signal level is too small, which makes conversion of the analog signal difficult. The first latch circuit 120 includes input terminals TP including a first switching circuit 121 turned on and off in response to an external clock signal Q and a first precious circuit 122 performing a positive feedback operation. , And latch and amplify the signals transmitted to TN to output first digital signals.

)에 응답하여 온오프 동작을 수행하는 제 2 스위칭 회로(131)와 정귀환 동작을 수행하는 제 2 정귀환 회로(132)를 구비하고 있다. 제 2 래치 회로는 상기 제 2 스위칭 회로(131)가 온될 때, 입력 단자들(TP, TN)로 전달된 신호들을 래치 및 증폭하여 제 2 디지털 신호들을 출력한다.And the second latch circuit 130 is an inverted clock signal (

A second switching circuit 131 performing an on-off operation and a second positive feedback circuit 132 performing a positive feedback operation. When the second switching circuit 131 is turned on, the second latch circuit latches and amplifies signals transmitted to the input terminals TP and TN to output second digital signals.

The selection circuit 140 selects and outputs a pair of two pairs of digital signals Dout generated from the first latch circuit 120 and the second latch circuit 130. The encoder 150 encodes digital signals generated from an output terminal of the selection circuit 140, which operates by receiving a system clock QS for a digital system process.

Hereinafter, the operation of the analog-to-digital converter having the configuration as described above will be described with reference to FIGS. 4A and 4B.

4B is an output waveform diagram of a clock signal.

)는 시스템 클럭 신호(QS)의 1/2 속도를 갖는다. 그리고 상기 클럭 신호(Q)와 반전 클럭 신호(

)는 위상만 반대인 신호들이므로 제 1 스위칭 회로(121)와 제 2 스위칭 회로(131)가 동시에 온되는 일은 발생하지 않는다. 예를 들어 설명하면, 클럭 신호(Q)가 하이레벨이고 반전 클럭 신호 (

)가 로우레벨인 제 1 구간(T1)에서는 제 1 스위칭 회로(121)만이 온되어 제 1 정귀환 회로(122)가 동작되고, 클럭 신호(Q)가 로우레벨이고 반전 클럭 신호 (

)가 하이레벨인 제 2 구간(T2)에서는 제 2 스위칭 회로(131)만이 온되어 제 2 정귀환 회로(132)가 동작을 수행한다.Referring to FIG. 4A, analog signals amplified and output from the preamplifier 110 are applied to the first input terminal TP and the second input terminal TN, and analog signals of the input terminals TP and TN. Is transmitted to the first and second latch circuits 120 and 130, respectively. In this case, referring to FIG. 4B, the clock signal Q and the inverted clock signal applied to the first switching circuit 121 and the second switching circuit 131 may be described.

) Has a half speed of the system clock signal QS. And the clock signal Q and the inverted clock signal (

) Are only reversed signals, so that the first switching circuit 121 and the second switching circuit 131 are not turned on at the same time. For example, if the clock signal Q is high level and the inverted clock signal (

In the first period T1 where) is low level, only the first switching circuit 121 is turned on to operate the first positive feedback circuit 122, and the clock signal Q is low level and the inverted clock signal (

In the second period T2 where) is the high level, only the second switching circuit 131 is turned on to perform the operation of the second positive feedback circuit 132.

5A is a voltage waveform diagram of input terminals of a latch circuit, and FIG. 5B is a voltage waveform diagram of a common mode input terminal.

Since the first and second switching circuits 121 and 131 are turned on to perform a latch operation, kickback noises generated from the first latch circuit 120 and the second latch circuit 130 may be input terminals TP,. TN). In this case, the kickback noise generated from the first latch circuit 130 and the kickback noise generated from the second latch circuit 140 are transmitted to the input terminal with a delay corresponding to half the period. Therefore, since the kickback noises have opposite levels, the kickback noises are added to each other at the input stage, thereby reducing the overall noise. As a result, the overall swing width at which the voltages of the input terminals TP and TN move along the clock signal may be reduced from about 2V to about 0.2V.

)는 시스템 클럭 신호(QS)의 1/2 속도를 갖고 래치 회로들(130, 150)이 교대로 동작하기 때문에 각각의 래치 회로(130, 150)에 대해 래칭 시간(latching time)이 존재하게 된다. 즉 시스템 클럭 신호(QS)가 100MHZ의 속도를 갖고 회로를 동작하게 한다면, 상기 클럭 신호(Q)와 반전 클럭 신호 (

)는 절반인 50MHZ 만으로도 동작을 가능하게 한다. 그러므로 두 개의 래치 회로들로부터 두배의 래칭 시간을 확보하여 고속 동작시에도 준안정 기간의 영향에 의한 출력 신호들의 오류 발생을 막을 수 있다.The clock signal Q and the inverted clock signal applied to the first switching circuit 121 and the second switching circuit 131

) Has a half speed of the system clock signal QS and latching times 130 and 150 operate alternately so that a latching time exists for each latch circuit 130 and 150. . That is, if the system clock signal QS operates at a speed of 100 MHz, the clock signal Q and the inverted clock signal (

) Can be operated with only half the 50MHZ. Therefore, a double latching time can be secured from the two latch circuits to prevent the occurrence of errors in the output signals due to the metastable period even during high speed operation.

As described above, by providing two latch circuits, the kickback noises can be canceled out to reduce the overall noise, and the influence of the metastable period by adjusting the speed of the clock signals of the latch circuits to be half the speed of the system clock signal. There is an effect to reduce.

1 is a circuit diagram showing the configuration of an analog-to-digital converter according to the prior art;

2A and 2B are input voltage waveform diagrams of the latch circuit of FIG. 1;

3A is a waveform diagram of a clock signal;

3B and 3C are input voltage waveform diagrams of the latch circuit of FIG. 1;

4A is a circuit diagram showing a configuration of an analog to digital converter according to an embodiment of the present invention;

4B is an output waveform diagram of a clock signal;

5A and 5B are input voltage waveform diagrams of the latch circuit of FIG. 4A;

* Explanation of symbols on the main parts of the drawings

110: preamplifier 120: first latch circuit

121: first switching circuit 122: first positive feedback circuit

130: second latch circuit 131: second switching circuit

132: positive feedback circuit 140: selection circuit

150: encoder

Claims (5)

A preamplifier that receives an analog signal from the outside and amplifies it to a predetermined level and outputs the amplified signal; A first input terminal and a second input terminal receiving an analog signal generated by being amplified from the preamplifier; First latch means for storing and amplifying signals transmitted to the first and second input terminals in response to a first clock signal applied from the outside to output a first digital signal; Second latch means for storing and amplifying signals transmitted to the first and second input terminals in response to a second clock signal applied from the outside to output a second digital signal; Selection means for receiving the first digital signal and the second digital signal, and selecting one of the first digital signal and the second digital signal; And an encoder for encoding and outputting digital signals generated through the selection means in synchronization with a system clock signal applied from the outside. And the first clock signal and the second clock signal are clock signals having opposite phases to each other. The method of claim 1, The first latch means First switching means turned on and off in response to the clock signal; First positive feedback means for receiving signals generated from the preamplifier when the first switching means is turned on, latching them, and outputting first digital signals; An analog-to-digital converter comprising transistors connected in parallel between the first switching means and the first positive feedback means. The method of claim 1, The second latch means Second switching means turned on and off in response to the inverted clock signal; Second positive feedback means for receiving a signal transmitted from the preamplifier when the second switching means is turned on, and latching it to output second digital signals; And transistors connected in parallel between said second switching means and said second positive feedback means. The method of claim 1, And the first and second latch means are alternately operated by the first clock signal and the second clock signal which are only in reverse phase. The method of claim 1, The clock signal and the inverted clock signal are And at half the speed of said system clock signal.