JP2002091398A - Liquid crystal driving circuit and liquid crystal display device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal driving circuit to be formed integrally with a pixel area on an insulating substrate, in which the number of elements is reduced and which has a redundancy circuit whose circuit scale is small. SOLUTION: A driving block has DFFs(dynamic flip-flops) 11, 13, 15 and DFFs(dynamic flip-flops) 12, 14, 16 of two systems and RSFFs(reset-set flip-flops) 21, 22 provided respectively by one in respective systems. Moreover, in the driving block, AND circuits 31, 33, 35 outputting logical products among respective outputs of the DFFs(dynamic flip-flops) 11, 13, 15 and the output of the RSFF 21 and AND circuits 32, 34, 36 outputting logical products among respective outputs of the DFFs(dynamic flip-flops) 12, 14, 16 and the output of the RSFF 22 are provided. Furthermore, OR circuits 41, 42, 43 outputting respective logical sums between the AND circuits 31, 32, between the AND circuits 33, 34 and between the AND circuits 35, 36 are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal drive circuit such as a gate driver and a data driver and a liquid crystal display device using the same. The present invention relates to a liquid crystal drive circuit and a liquid crystal display device using the same.

[0002]

2. Description of the Related Art A liquid crystal display device has an array substrate and a counter substrate bonded together at a predetermined gap, and liquid crystal sealed in the gap. In the case of an active matrix type liquid crystal display device, a plurality of data bus lines are formed on an array substrate in parallel with each other, and a plurality of gate bus lines extending in a direction substantially orthogonal to the data bus lines are formed in parallel with each other. Each data bus line is connected to a data bus line drive circuit, and a predetermined gradation voltage is applied to each data bus line. Each of the plurality of gate bus lines is connected to a gate bus line driving circuit. The gate bus line driving circuit outputs gate pulses sequentially on a plurality of gate bus lines in synchronization with a bit output output from a built-in shift register.

A pixel area is formed in an area defined by a gate bus line and a data bus line. A thin film transistor and a display electrode are formed in each pixel region arranged in a matrix. Each gate bus line is connected to the gate electrodes of a plurality of thin film transistors arranged in the row direction. Each data bus line is connected to drain electrodes of a plurality of thin film transistors arranged in the column direction.

When a gate pulse is output to any one of a plurality of gate bus lines by a gate bus line driving circuit, a plurality of thin film transistors connected to the gate bus line are turned on. As a result, the gradation voltage applied from the data bus line driving circuit to each of the plurality of data bus lines is applied to each pixel electrode.

[0005] With the recent development of low-temperature polysilicon manufacturing process technology, a peripheral circuit integrated type liquid crystal display device that forms a peripheral circuit on an array substrate simultaneously with the formation of a pixel region has been manufactured. . The peripheral circuit includes the above-described gate bus line driving circuit and data bus line driving circuit.

Generally, a liquid crystal display device with an integrated peripheral circuit has
Even if a defect such as a disconnection or a short-circuit occurs in a peripheral circuit formed integrally on a glass substrate, a redundant circuit for defect correction for correcting the defect is provided. By providing the redundant circuit, it is possible to prevent waste of discarding the array substrate having a defect, and it is possible to minimize a decrease in manufacturing yield.

A redundancy circuit for relieving defects is also provided in a gate bus line driving circuit and a data bus line driving circuit which are one of the peripheral circuits. As a redundant circuit, there is a manual repair method in which a plurality of extra shift registers are provided in a drive circuit, and a defective shift register is cut with a laser or the like to switch to a normally operating shift register. On the other hand, as a method of automatic repair, for example, Japanese Patent Laid-Open No.
The following are disclosed in Japanese Patent Publication No. 24651.

FIG. 10 shows a conventional redundancy circuit 100 for automatically relieving a defect of a shift register in a gate bus line driving circuit. Although the redundant circuit 100 is provided for each gate bus line, FIG. 10 typically shows the redundant circuit 100 of the drive system Xn that drives the n-th stage gate bus line Gn. The drive system Xn including the redundant circuit 100 includes three shift registers (SR1) 102,
(SR2) 104 and (SR3) 106 are provided. The start input signal SI output from the preceding drive system Xn-1 is simultaneously input to these shift registers 102, 104, and 106. A bit output line A is drawn from the shift register 102. A bit output line B is drawn from the shift register 104, and a bit output line C is drawn from the shift register 106.

The bit output line A is connected to the drain electrode of an N-channel MOSFET (metal oxide semiconductor type field effect transistor) 128 in the selection circuit 110 indicated by the dashed block, and is connected to one input terminal of the judgment circuit 124. It is connected. The bit output line B is connected to another input terminal of the determination circuit 124. The bit output line C is connected to the drain electrode of the N-channel MOSFET 130 in the selection circuit 110. MOSF in selection circuit 110
The source electrodes of the ETs 128 and 130 are commonly connected and connected to the gate bus line Gn. The output terminal of the determination circuit 124 is connected to the gate electrode of the MOSFET 130 and also connected to the gate electrode of the MOSFET 128 via the inverter 126 in the selection circuit 110.

The redundant circuit 1 having such a configuration will now be described.
At 00, the operation when there is no defect in the circuit will be described. Here, the determination circuit 124 determines whether the exclusive OR (EXO
R) circuit. If the output levels of the bit output lines A and B are the same, the determination circuit 124 outputs an “L (low)” level. Thereby, the N-channel MOSFET 1
28 is turned on, and the N-channel MOSFET 130
Is turned off. Therefore, the state level of the bit output line A is output to the gate bus line Gn.

Next, the operation of the redundant circuit 100 when a circuit is defective will be described. First, a case will be described in which a circuit in the shift register 102 is disconnected, and there is an “L” fixing failure in which the output of the bit output line A is always at the “L” level. Gate bus line G
When a gate pulse is output to n, the bit output line B
As a result, "H (high)" is output from the determination circuit 124, "H" is output from the determination circuit 124, and the MOSFET 128 is turned off and the MOSFET 130 is turned on. As a result, the bit output line A is cut off, and the output “H” of the bit output line C is selected.

When a gate pulse is not output to the gate bus line Gn, "L" is output to the bit output line B. As a result, "L" is output from the decision circuit 124, and M
OSFET 128 is turned on and MOSFET 13
0 turns off. As a result, the output “L” of the bit output line A is selected.

Next, an operation in the case where there is an "H" fixing defect in which the bit output line A always becomes "H" due to a short defect in the shift register 102 will be described. When a gate pulse is output to the gate bus line Gn, “H” is output to the bit output line B, so that the determination circuit 12
4 outputs “L”, turning on the MOSFET 128 and turning off the MOSFET 130. As a result, the output “H” of the bit output line A is selected.

When a gate pulse is not output to the gate bus line Gn, "L" is output to the bit output line B. As a result, "H" is output from the decision circuit 124, and M
OSFET 128 turns off and MOSFET 13
0 turns on. As a result, the bit output line A is cut off, and the output “L” of the bit output line C is selected. According to the above-described redundant configuration, the gate bus line Gn can be driven without error regardless of whether an "H" fixing defect or an "L" fixing defect occurs.

The redundant circuit 100 described with reference to FIG. 10 has three shift registers 102, 104,
106 is prepared, the state of the output lines A and B among the bit output lines A, B and C for selecting the same gate bus line Gn is compared by the determination circuit 124 to switch between the bit output lines A and C. As a result, the shift register “H”,
Any "L" fixing failure can be remedied.

[0016]

However, in the conventional redundant circuit, in the case of the manual repair method, although a redundant configuration can be obtained with a relatively small circuit scale, the introduction of a laser repair device requires a cost, and Since the handling is troublesome, there arises a problem that an increase in manufacturing cost and a prolonged manufacturing time are inevitable.

On the other hand, the redundant circuit 10 by the automatic repair method
When 0, three stages of shift registers 102, 10
4 and 106, and a comparison circuit such as an EXOR circuit for comparing the levels of the bit output lines of the two shift registers is provided for each gate bus line. As the number of elements increases, the circuit scale (occupied area) for arranging the redundant circuits increases. For this reason, although the fixing failure can be remedied, there is a problem that the occupied area on the array substrate integrated with the peripheral circuit increases and the manufacturing yield decreases.
In addition, an increase in the area occupied by the redundant circuit on the array substrate is not preferable because the frame region is relatively larger than the display region.

An object of the present invention is to provide a liquid crystal drive circuit having a redundant circuit with a small circuit size by reducing the number of elements, and a liquid crystal display device using the same. SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal driving circuit that can improve the manufacturing yield and suppress the size of the frame region, and a liquid crystal display device using the same. The object of the present invention is
It is an object of the present invention to provide a liquid crystal drive circuit configurable on a circuit scale according to a process yield and a liquid crystal display device using the same.

[0019]

SUMMARY OF THE INVENTION The object of the present invention is to provide a plurality of shift registers which are provided for each bus line and which change the output state level in synchronization with a predetermined signal, and the output state levels of the plurality of shift registers. A plurality of storage circuits for storing and outputting a control signal corresponding to the output state level; and a plurality of enable circuits for respectively changing and outputting the output state levels of the plurality of shift registers according to the control signals of the plurality of storage circuits. This is achieved by a liquid crystal drive circuit having a circuit and an output selection circuit for selecting and outputting one of the outputs of the plurality of enable circuits.

In the liquid crystal driving circuit according to the present invention, an RS flip-flop circuit formed in each of the plurality of storage circuits, an AND circuit formed in each of the plurality of enable circuits, and a circuit formed in the output selection circuit. And an OR circuit provided.

Further, in the liquid crystal drive circuit of the present invention, a plurality of the bus lines are put together to constitute one block, and the storage circuit is provided for each of the blocks.

Further, the above object is to provide a liquid crystal display device having a liquid crystal driving circuit for sealing a liquid crystal between two substrates and controlling a plurality of bus lines formed on the substrates to drive the liquid crystal. In the liquid crystal display device described above, the liquid crystal driving circuit uses the liquid crystal driving circuit of the present invention. In the above liquid crystal display device of the present invention, the liquid crystal drive circuit is formed on a substrate on which the plurality of bus lines are formed.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A liquid crystal driving circuit and a liquid crystal display device using the same according to a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows a schematic configuration of a liquid crystal drive circuit according to the present embodiment and a liquid crystal display device including the same. On the array substrate 81, p-Si
A thin film transistor 82 having an operating semiconductor layer made of (polysilicon) and a display region 86 in which a large number of pixel regions 84 having a display electrode made of a transparent electrode such as ITO (indium tin oxide) are arranged in a matrix are defined. Have been.

Around the display area 86, peripheral circuits formed by a low-temperature polysilicon manufacturing process are arranged. A liquid crystal drive circuit is arranged as a peripheral circuit,
As a liquid crystal driving circuit, a gate bus line driving circuit 88 is arranged on the left side in the figure, and a data bus line driving circuit 90 is arranged on the upper side in the figure.

A dot clock from the system, a horizontal synchronizing signal (Hsync), a vertical synchronizing signal (Vs
input terminal 92 for inputting the input data (.ync) and RGB data is provided above the panel in the figure. The array substrate 81 is bonded to the opposing substrate 94 via a sealing agent (not shown). Liquid crystal lc is sealed in a cell gap between the array substrate 81 and the counter substrate 94. The display electrode on the array substrate 81, the counter electrode on the counter substrate 4, and the liquid crystal lc sandwiched therebetween form a liquid crystal capacitor Clc. On the other hand, on the array substrate 81 side, a storage capacitor electrode is formed via a display electrode and a gate insulating film (not shown) to form a storage capacitor Cs.

A plurality of data bus lines 96 extending in the vertical direction in the figure are formed in the display area 86 in parallel in the horizontal direction in the figure. Each of the plurality of data bus lines 96 is provided with a data bus line driving circuit 9 as a liquid crystal driving circuit.
0, and a predetermined gradation voltage is applied to each data bus line 96.

A plurality of gate bus lines 98 extending in a direction substantially perpendicular to the data bus lines 96 are formed in parallel in the vertical direction in the figure. Multiple gate bus lines 9
8 are connected to a gate bus line drive circuit 88 as a liquid crystal drive circuit. The gate bus line driving circuit 88 sequentially outputs gate pulses to a plurality of gate bus lines 98 in synchronization with a bit output output from a built-in shift register.

When a gate pulse is output to any one of the plurality of gate bus lines 98 by the gate bus line driving circuit 88, the plurality of thin film transistors 82 connected to the gate bus line 98 are turned on.
As a result, the gradation voltage applied from the data bus line driving circuit 90 to each of the plurality of data bus lines 96 is applied to each pixel electrode.

Next, a redundancy circuit for relieving defects in the gate bus line driving circuit 88 as the liquid crystal driving circuit according to the present embodiment will be described with reference to FIG. FIG.
A drive system Xn including a redundancy circuit for relieving a shift register defect in the gate bus line drive circuit 88 is shown.
The redundant circuit 20 is provided for each gate bus line, but typically, in FIG.
1 and a drive system X2 for driving the second-stage gate bus line G2.

The drive system X1 has D flip-flop (DFF) circuits 11 and 12 as two shift registers. The DFF circuits 11 and 12 have the same configuration as a DFF circuit used in a conventional drive system that does not form a redundant circuit. The start input signal SI is input to the input terminals of the DFF circuits 11 and 12. When the start input signal SI is input, the driving of the plurality of gate bus lines G by the gate bus line driving circuit 88 is started.

The signal DF11out output from the output terminal of the DFF circuit 11 is supplied to an RS flip-flop (RSF
F) An input terminal S of the circuit 21 and one input terminal of the two-input AND circuit 31 are inputted. A reset signal Reset is input to an input terminal R of the RSFF circuit 21. The reset signal Reset is output for each frame in display. RSFF circuit 21
Functions as a defect storage circuit that stores a defect of the DFF circuit 11 and stores the output signal DF11out of the DFF circuit 11. The signal RS11out output from the output terminal Q of the RSFF circuit 21 is input to another input terminal of the AND circuit 31 and used as a control signal for controlling the output of the AND circuit 31.

The two-input AND circuit 31 outputs the output signal DF11out of the DFF circuit 11 according to the signal level of the output signal RS11out of the defect storage circuit (RSFF circuit 21).
This is an enable circuit that outputs a signal q11 in which t has been changed. The signal q output from the output terminal of the AND circuit 31
Reference numeral 11 denotes an input to one input terminal of the two-input OR circuit 41.

Similarly, the signal DF12out output from the output terminal of the DFF circuit 12 is
, And one input terminal of the two-input AND circuit 32. The reset signal Reset is input to the input terminal R of the RSFF circuit 22. The signal RS12out output from the output terminal Q of the RSFF circuit 22 is input to another input terminal of the AND circuit 32 and used as a control signal for controlling the output of the AND circuit 32. The signal q12 output from the output terminal of the AND circuit 32 is input to the other input terminal of the two-input OR circuit 41. The two-input OR circuit 41 includes
The output selection circuit selects the output signal q11 of the D circuit 31 and the output signal q12 of the AND circuit 32. The output Q1 of this output selection circuit is used as a drive signal for the gate bus line G1, and the DFF circuit 1 of the next-stage drive system X2.
The signals are input to input terminals 3 and 14.

In the above configuration, the driving system X1 is
A set of the F circuit 11, the RSFF circuit 21, and the AND circuit 31, and the DFF circuit 12, the RSFF circuit 22, and the AND
A redundant configuration is formed with the set of the circuits 32.

The driving system X2 has the same configuration as that of the driving system X1, and a detailed description thereof will be omitted.
3, a set of the RSFF circuit 23 and the AND circuit 33, and D
FF circuit 14, RSFF circuit 24, and AND circuit 34
A redundant configuration is formed with the set. Also, two-input OR
The circuit 42 outputs the output signal q13 of the AND circuit 33 and the signal AN13.
An output selection circuit for selecting an output signal q14 of the D circuit 34. The output Q2 is used as a drive signal for the gate bus line G2, and is also used as an input terminal of two DFF circuits of a drive system X3 (not shown) at the next stage. Is input to

Next, the driving operation when the driving systems X1 and X2 shown in FIG. 2 are normal will be described with reference to FIG. FIG. 3 is a timing chart showing the operation timing of input / output signals in each circuit.

First, the RSFF circuits 21, 22, 23, 2
The reset signal Reset input to each input terminal R changes to “H” level. The RSFF circuits 21 to 24
The signal RS11out to RS1 output from the output terminal Q when the signal of the "L" level is input to the input terminal S at least once.
4out is at "H" level, otherwise it is at "L" level. At this time, since the output signals DF11out to DF14out of the DFF circuits 11 to 14 are at the “L” level, the output signals RS11 of the RSFF circuits 21 to 24 are output.
Out to RS14out all maintain the “H” level.

Next, the start input signal SI becomes DF.
Input to the F circuits 11 and 12 and output signal DF11ou
t, DF12out changes to “H” level. At this time, since the reset signal Reset of each input terminal R of the RSFF circuits 21 and 22 is at "L" level, the output signals RS11out and RS12out maintain "H" level. Next, DF11out and DF12out change to “L” level, but the reset signal Reset remains at “L” level, so that the output signal RS11out is output.
t and RS12out maintain the “H” level.

Thus, the signal D is output from the AND circuit 31.
A signal q11 synchronized with F11out is output, and AND
The signal q1 synchronized with the signal DF12out is output from the circuit 32.
2 is output, and both signals are input to the OR circuit 41. OR
In the circuit 41, the normally operating DFF circuits 11, 1
2 outputs a signal Q1 synchronized with the output signals DF11out and DF12out. This signal Q1 is used as a gate pulse in the gate bus line G1 and is input to the next-stage drive system X2.

In the driving system X2, when the signal Q1 is input to the DFF circuits 13 and 14, the output signal DF13out,
DF14out changes to “H” level. At this time,
Since the reset signal Reset of each input terminal R of the RSFF circuits 23 and 24 is at “L” level, the output signals RS13out and RS14out maintain “H” level. Next, DF13out and DF14out change to the “L” level, but the reset signal Reset remains at the “L” level, so that the output signal RS13out is output.
t and RS14out maintain “H” level.

Thus, the signal D is output from the AND circuit 33.
A signal q13 synchronized with F13out is output, and AND
The signal q1 synchronized with the signal DF14out is output from the circuit 34.
4 is output, and both signals are input to the OR circuit 42. OR
In the circuit 42, the normally operating DFF circuits 13, 1
4 outputs a signal Q2 synchronized with the output signals DF13out and DF14out. This signal Q2 is used as a gate pulse in the gate bus line G2 and is input to the next-stage drive system X3 (not shown). As described above, when the operation is normal, the output DFout of the DFF circuit is directly used as the output Q from the drive system X of each stage.

On the other hand, for example, the DFF of the drive system X1
A driving operation in which a defect is corrected when an “L” fixing defect occurs in the circuit 12 will be described with reference to FIG.
FIG. 4 is a timing chart showing the operation timing of input / output signals in each circuit.

As shown in FIG. 4, since an "L" fixing failure has occurred in the DFF circuit 12, the output DF12out of the DFF circuit 12 is always at the "L" level. R
In the SFF circuits 21 to 24, the signal RS11out output from the output terminal Q becomes "H" level when a signal of "L" level is input to the input terminal S even once, and otherwise becomes "L" level. Therefore, the output signal RS12out of the output terminal Q of the RSFF circuit 22 is always at the “H” level.

Even if the start input signal SI is input to the DFF circuit 12, the output signal DF12out remains at "L" level. At this time, since the reset signal Reset of the input terminal R of the RSFF circuit 22 is at the “L” level, the output signal RS12out does not change and maintains the “H” level.

As a result, the output signal DF12out which is always “L” and the output signal RS12out which is always “H” are input to the AND circuit 32. Therefore, the output signal q12 always “L” is output from the AND circuit 32. Is done. on the other hand,
As described with reference to FIG. 3, the signal q11 synchronized with the signal DF11out is output from the normal DFF circuit 11 at a predetermined timing. These two signals q11,
The signal q12 is input to the OR circuit 41, and a signal Q1 synchronized with the output signal DF11out of the normally operating DFF circuit 11 is output from the OR circuit 41. The drive system X
The driving operation in 2 is the same as that described with reference to FIG. As described above, even if the "L" fixing failure occurs, a normal output Q in which the defect is corrected can be obtained from the driving system X of each stage.

Next, for example, the DFF circuit 12 of the drive system X1
In FIG. 5, a driving operation in which a defect is corrected when an “H” fixing failure occurs will be described. FIG.
5 is a timing chart showing operation timings of input / output signals in each circuit.

As shown in FIG. 5, since the DFF circuit 12 has an "H" fixing failure, the output DF12out of the DFF circuit 12 is always at the "H" level. Therefore, the output signal RS of the output terminal Q of the RSFF circuit 22
12out is always at the "L" level.

Even if the start input signal SI is input to the DFF circuit 12, the output signal DF12out remains at "H" level. At this time, since the reset signal Reset of the input terminal R of the RSFF circuit 22 is at the “L” level, the output signal RS12out does not change and maintains the “L” level.

As a result, the output signal DF12out which is always “H” and the output signal RS12out which is always “L” are input to the AND circuit 32. Therefore, the output signal q12 always “L” is output from the AND circuit 32. Is done. on the other hand,
As described with reference to FIG. 3, the signal q11 synchronized with the signal DF11out is output from the normal DFF circuit 11 at a predetermined timing. These two signals q11,
The signal q12 is input to the OR circuit 41, and a signal Q1 synchronized with the output signal DF11out of the normally operating DFF circuit 11 is output from the OR circuit 41. The drive system X
The driving operation in 2 is the same as that described with reference to FIG. As described above, even if the "H" fixing failure occurs, a normal output Q in which a defect is corrected can be obtained from the driving system X of each stage.

As described above, by using the drive system having the redundant circuit shown in FIG. 2, any defect of "L" fixing defect or "H" fixing defect can be automatically repaired.
As is clear from this circuit configuration, even if a defect occurs in the RSFF circuits (defect storage circuits) 21 and 22, if the DFF circuits 11 and 12 operate normally, a correct output Q1 can be obtained. .

Next, a liquid crystal driving circuit according to a second embodiment of the present invention and a liquid crystal display device using the same will be described with reference to FIG.
This will be described with reference to FIGS. The liquid crystal display device provided with the liquid crystal driving circuit according to the present embodiment is the same as the liquid crystal display device described with reference to FIG. 1 in the first embodiment, and the description thereof will be omitted. A redundant circuit for relieving defects in a gate bus line driving circuit 88 as a liquid crystal driving circuit will be described with reference to FIG.

FIG. 6 shows a drive block Xn including a redundant circuit for relieving a shift register defect in the gate bus line drive circuit 88. The drive block Xn has three outputs Qn to Qn + 2 that supply gate pulses to three gate bus lines Gn to Gn + 2, respectively. FIG. 6 typically shows a drive block X1 that drives the first to third-stage gate bus lines G1 to G3.

The drive block X1 includes DFF circuits 11, 12 and
13, 14, 15, and 16. DFF circuit 11
16 have the same configuration as a DFF circuit used in a conventional drive system that does not form a redundant circuit. The input terminals of the DFF circuits 11 and 12 have a start input signal SI
Is to be entered. When the start input signal SI is input, the gate bus line driving circuit 8
8, the driving of the plurality of gate bus lines G is started.

The signal DF11out output from the output terminal of the DFF circuit 11 is input to the input terminal of the DFF circuit 13 at the next stage and one input terminal of the two-input AND circuit 31. The signal DF13out output from the output terminal of the DFF circuit 13 is input to the input terminal of the DFF circuit 15 at the next stage and one input terminal of the two-input AND circuit 33. Further, the DFF circuit 1
5, the signal DF15out output from the output terminal
The input is made to the input terminal S of the SFF circuit 21 and one input terminal of the two-input AND circuit 35. And R
Output signal RS1ou from output terminal Q of SFF circuit 21
t is input to the other input terminal of each of the AND circuits 31, 33, and 35.

On the other hand, the signal DF12out output from the output terminal of the DFF circuit 12 is input to the input terminal of the DFF circuit 14 at the next stage and one input terminal of the two-input AND circuit 32. The signal DF14out output from the output terminal of the DFF circuit 14 is output to the DFF of the next stage.
An input terminal of the circuit 16 and one input terminal of the two-input AND circuit 34 are inputted. Further, the signal DF16out output from the output terminal of the DFF circuit 16 is
An input terminal S of the RSFF circuit 22 and a two-input AND circuit 3
6 to one input terminal. And
Output signal RS2o from output terminal Q of RSFF circuit 22
ut is input to the other input terminals of the AND circuits 32, 34, and 36.

The reset signal Reset is input to the input terminals R of the RSFF circuits 21 and 22. The reset signal Reset is output for each frame in display. The RSFF circuit 21 functions as a defect storage circuit that stores a defect generated in any of the DFF circuits 11, 13, and 15. The signal RS1out output from the output terminal Q of the RSFF circuit 21 is input to the other input terminals of the AND circuits 31, 33, and 35, and
1, 33 and 35 are used as control signals for controlling the outputs.

The two-input AND circuits 31 to 36 output the output signal RS1o of the defect storage circuit (RSFF circuit 21 or 22).
output signals DF11out to DF of the DFF circuits 11 to 16 according to the signal level of the out signal or the RS2out signal.
This is an enable circuit that outputs signals q11 to q16 each having 16out changed.

The signal q11 output from the output terminal of the AND circuit 31 is input to one input terminal of the two-input OR circuit 41, and the signal q1 output from the output terminal of the AND circuit 32 is output.
2 is input to the other input terminal of the two-input OR circuit 41. The signal q13 output from the output terminal of the AND circuit 33 is input to one input terminal of the two-input OR circuit 42, and the signal q14 output from the output terminal of the AND circuit 34 is Input to the input terminal. Further, the signal q15 output from the output terminal of the AND circuit 35 is a two-input OR circuit 43
The signal q16 input to one input terminal and output from the output terminal of the AND circuit 36 is input to the other input terminal of the two-input OR circuit 43.

As described above, in the redundant configuration according to the present embodiment, two RSFF circuits are provided for each drive block, and two RSFF circuits are provided for each bus line as in the first embodiment. The circuit scale can be reduced as compared to the provided drive system. Further, according to this configuration, the number of bus lines driven by one drive block Xn can be changed arbitrarily, so that the number of drive blocks in the bus line drive circuit can be changed according to the production yield of the array substrate. . Therefore, the circuit scale of the redundant circuit,
An optimal redundant configuration can be adopted in consideration of cost and yield.

Next, a driving operation when the driving block X1 shown in FIG. 6 is normal will be described with reference to FIG. FIG. 7 is a timing chart showing operation timing of input / output signals in each circuit. The same operations as those in FIGS. 3 to 5 in the first embodiment will not be described again.

First, in normal operation, the RSFF circuit 2
Each of the output signals RS1out and RS2out 1 and 22 maintains the “H” level. The start input signal SI is input to the DFF circuits 11 and 12, and the output signals DF11out and DF12out change to “H” level. The output signal DF11ou changed to the “H” level
t is input to the DFF circuit 13 and the AND circuit 31. Next, the output signal DF13out of the DFF circuit 13 changes to “H” level and is input to the DFF circuit 15 and the AND circuit 33. As a result, the output signal DF13out of the DFF circuit 13 changes to “H” level and is input to the DFF circuit 15 and the AND circuit 33. Next, the output signal DF15out of the DFF circuit 15 changes to “H” level and is input to the RSFF circuit 21 and the AND circuit 35.

As a result, the signal D is output from the AND circuit 31.
A signal q11 synchronized with F11out is output, and AND
The circuit 33 outputs a signal q1 synchronized with the signal DF13out.
3 is output, and the signal DF15ou is output from the AND circuit 35.
Signals q15 synchronized with t are sequentially output.

On the other hand, DFF circuits 12, 14, 16 and R
The SFF circuit 22 operates in the same manner as described above, and the AND circuit 3
2, a signal q12 synchronized with the signal DF12out is output, a signal q14 synchronized with the signal DF14out is output from the AND circuit 34, and a signal q16 synchronized with the signal DF16out is sequentially output from the AND circuit 36.

The signal q11 and the signal q12 are supplied to the OR circuit 41.
To enter. In the OR circuit 41, the normally operating D
Output signals DF11out, DF1 of the FF circuits 11, 12
A signal Q1 synchronized with 2out is output. This signal Q1
Are used as gate pulses in the gate bus line G1.

Next, the signals q13 and q14 are input to the OR circuit 42 in the same manner as described above. In the OR circuit 42, the output signals DF13out of the normally operating DFF circuits 13 and 14, and the signal Q2 synchronized with the DF14out
Is output. This signal Q2 is used as a gate pulse on the gate bus line G2.

Next, in the same manner as described above, the signal q1
5 and the signal q16 are input to the OR circuit 43. The OR circuit 43 outputs a signal Q3 synchronized with the output signals DF15out and DF16out of the normally operating DFF circuits 15 and 16. This signal Q3 is used as a gate pulse on the gate bus line G3. in this way,
When operating normally, from the drive system X of each stage,
The output DFout of the DFF circuit is used as it is as the output Q.

On the other hand, a description will be given, with reference to FIG. 8, of a driving operation in which a defect is corrected, for example, when an "L" fixing defect occurs in the DFF circuit 13 of the driving block X1. FIG. 8 is a timing chart showing the operation timing of input / output signals in each circuit.

As shown in FIG. 8, since an "L" fixing failure has occurred in the DFF circuit 13, the output DF13out of the DFF circuit 13 is always at the "L" level. Therefore, the output signal DF15out of the DFF circuit 15 is always at the “L” level. As described above, all the DFF circuits after the DFF circuit in which the “L” fixing failure has occurred are “L”.
Fixation failure occurs. Further, in the RSFF circuit 21, the signal RS1out output from the output terminal Q becomes “H” level when the signal of “L” level is input to the input terminal S even once, so that the DFF circuit 13 is fixed to “L”. The output signal RS of the RSFF circuit 21 when a defect occurs
1out is always at "H" level.

As a result, the AND circuits 33 and 35 have
Output signal DF13out, DF15out always "L"
, The "H" output signal RS1out is always input, so the AND circuits 33 and 35 always output "L" output signals q13 and q15. On the other hand, as described with reference to FIG. 7, signals from the normal DFF circuits 12, 14, and 16 are output at predetermined timings from the signals DF12out and DF14.
out, signals q12, q1 synchronized with DF16out
4, q16 is output.

The signal q11 and the signal q12 are input to the OR circuit 41, and the normally operating DFF circuit 11, DFF
The output signal DF11out of the circuit 12 and a signal Q1 synchronized with the DF12out are output from the OR circuit 41. The signal q13 and the signal q14 are input to the OR circuit 42, and the output signal DF of the normally operating DFF circuit 14 is output.
The signal Q2 synchronized with 14out is output from the OR circuit 42. The signal q15 and the signal q16 are connected to an OR circuit 43.
And the signal Q3 synchronized with the output signal DF16out of the normally operating DFF circuit 16 is input to the OR circuit 43.
Output from As described above, even if the "L" fixing defect occurs, the normal output Q in which the defect is corrected from the driving system X of each stage.
Can be obtained.

Next, a description will be given, with reference to FIG. 9, of a driving operation in which a defect is corrected, for example, when an "H" fixing defect occurs in the DFF circuit 13 of the driving block X1. FIG. 9 is a timing chart showing the operation timing of input / output signals in each circuit. As shown in FIG.
Since an "H" fixing failure has occurred in the F circuit 13, the DFF
The output DF13out of the circuit 13 is always at "H" level. Therefore, the output signal DF1 of the DFF circuit 15
5out is also always at "H" level. As described above, all the DFF circuits after the DFF circuit in which the “H” fixing failure has occurred have the “H” fixing failure. Also, the RSFF circuit 2
In No. 1, the output signal RS1out is always at the "L" level because no "L" level signal is input to the input terminal S.

As a result, the AND circuits 33 and 35 have:
Output signals DF13out, DF15out always "H"
, The "L" output signal RS1out is always input, and the AND circuits 33 and 35 always output "L" output signals q13 and q15. On the other hand, as described with reference to FIG. 7, signals from the normal DFF circuits 12, 14, and 16 are output at predetermined timings from the signals DF12out and DF14.
out, signals q12, q1 synchronized with DF16out
4, q16 is output.

The signal q11 and the signal q12 are input to the OR circuit 41, and the normally operating DFF circuit 11, DFF
The output signal DF11out of the circuit 12 and a signal Q1 synchronized with the DF12out are output from the OR circuit 41. The signal q13 and the signal q14 are input to the OR circuit 42, and the output signal DF of the normally operating DFF circuit 14 is output.
The signal Q2 synchronized with 14out is output from the OR circuit 42. The signal q15 and the signal q16 are connected to an OR circuit 43.
And the signal Q3 synchronized with the output signal DF16out of the normally operating DFF circuit 16 is input to the OR circuit 43.
Output from As described above, even if the "H" fixing failure occurs, the normal output Q in which the defect is corrected from the driving system X of each stage.
Can be obtained.

As described above, by using the drive block provided with the redundant circuit shown in FIG. 6, any defect of "L" fixing defect or "H" fixing defect can be automatically repaired. In addition, as is clear from this circuit configuration,
Even when a defect occurs in the RSFF circuits (defect storage circuits) 21 and 22, if the DFF circuits 11 to 16 operate normally, correct outputs Q1 to Q3 can be obtained.

In the present embodiment, the driving block Xn
Are three outputs Qn to Qn + 2 that supply gate pulses to three gate bus lines Gn to Gn + 2, respectively.
However, the present invention is not limited to this, and one RSFF circuit may be used for a drive block that drives m bus lines.

According to the redundant configuration of this embodiment, the circuit scale of the redundant configuration can be reduced as the number of DFF circuits in one drive block is increased. However, 1
DFF circuit and R in two drive blocks
When various types of defects occur in the SFF circuit, complete defect repair cannot be performed, causing a malfunction. To suppress this, the first embodiment in which a redundant circuit is provided for each bus line is most desirable. Therefore, it is desirable to configure the number of bus lines in one drive block according to the yield of the manufacturing process.

The present invention is not limited to the above embodiment, but can be variously modified. For example, in the above-described embodiment, an example in which the present invention is applied to the gate bus line driving circuit 88 has been described. However, the present invention is not limited to this, and can be applied to the data bus line driving circuit 90. In this case, the reset signal Reset input to the input terminal R of the RSFF circuit may be output not every one frame period but every one horizontal period.

[0078]

As described above, according to the present invention, a redundant circuit having a reduced circuit scale by reducing the number of elements can be obtained. Further, according to the present invention, it is possible to realize a liquid crystal driving circuit which can improve the manufacturing yield and suppress the size of the frame region, and a liquid crystal display device using the same. Further, according to the present invention, it is possible to make an optimal redundant configuration according to a desired manufacturing yield, and it is possible to realize a peripheral circuit integrated type display device with few failures.

[Brief description of the drawings]

FIG. 1 is a diagram showing a schematic configuration of a liquid crystal drive circuit and a liquid crystal display device using the same according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a schematic configuration of a redundancy circuit for relieving defects in a gate bus line driving circuit 88 as a liquid crystal driving circuit according to the first embodiment of the present invention.

FIG. 3 is a timing chart showing a driving operation when the driving system is normal in the liquid crystal driving circuit according to the first embodiment of the present invention.

FIG. 4 is a timing chart showing a driving operation when a driving system has an “L” fixing failure in the liquid crystal driving circuit according to the first embodiment of the present invention.

FIG. 5 is a timing chart showing a driving operation in a case where the driving system has an “H” fixing failure in the liquid crystal driving circuit according to the first embodiment of the present invention.

FIG. 6 is a diagram showing a schematic configuration of a defect relief redundancy circuit in a gate bus line drive circuit 88 as a liquid crystal drive circuit according to a second embodiment of the present invention.

FIG. 7 is a timing chart showing a driving operation when a driving system is normal in a liquid crystal driving circuit according to a second embodiment of the present invention.

FIG. 8 is a timing chart showing a driving operation in a case where a driving system has an “L” fixing failure in a liquid crystal driving circuit according to a second embodiment of the present invention.

FIG. 9 is a timing chart showing a driving operation when a driving system has an “H” fixing failure in the liquid crystal driving circuit according to the second embodiment of the present invention.

FIG. 10 is a diagram showing a schematic configuration of a redundant circuit used in a conventional gate bus line driving circuit.

[Explanation of symbols]

 11, 12, 13, 14, 15, 16 DFF circuit 20 Redundant circuit 21, 22, 23, 24 RSFF circuit 31, 32, 33, 34, 35, 36 AND circuit 41, 42, 43 OR circuit 81 Array substrate 82 Thin film transistor 84 pixel area 86 display area 88 gate bus line drive circuit 90 data bus line drive circuit 92 input terminal 94 opposing substrate 96 data bus line 98 gate bus line 100 redundancy circuit 124 judgment circuit 126 inverter 128, 130 MOSFET 102, 104, 106 shift Register 110 selection circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/78 614 F Term (Reference) 2H093 NC22 NC34 ND46 ND50 NE01 5C006 AA16 AC11 AC24 AF06 AF53 AF78 BB15 BC05 BC14 BC20 BF03 BF06 BF14 BF26 FA00 FA42 5C080 AA10 BB05 DD28 EE29 FF11 GG12 JJ02 JJ03 JJ04 5F110 AA27 AA30 BB02 GG02 GG13 NN72 NN73

Claims (5)

[Claims] A shift register provided for each bus line to change an output state level in synchronization with a predetermined signal; and an output state level of each of the plurality of shift registers is stored and stored in the output state level. A plurality of storage circuits that output corresponding control signals; a plurality of enable circuits that respectively change and output output state levels of the plurality of shift registers according to the control signals of the plurality of storage circuits; and a plurality of enable circuits. A liquid crystal drive circuit comprising: an output selection circuit that selects and outputs any one of the outputs described above. 2. The liquid crystal drive circuit according to claim 1, wherein an RS flip-flop circuit formed in each of said plurality of storage circuits, and an AN formed in each of said plurality of enable circuits.
A liquid crystal drive circuit comprising: a D circuit; and an OR circuit formed in the output selection circuit. 3. The liquid crystal drive circuit according to claim 1, wherein a plurality of the bus lines are combined to form one block, and the storage circuit is provided for each block. Liquid crystal drive circuit. 4. A liquid crystal display device comprising a liquid crystal drive circuit for sealing a liquid crystal between two substrates and controlling a plurality of bus lines formed on the substrates to drive the liquid crystal. The drive circuit according to claim 1, wherein
A liquid crystal display device using the liquid crystal drive circuit described in the above item. 5. The liquid crystal display device according to claim 4, wherein said liquid crystal drive circuit is formed on a substrate on which said plurality of bus lines are formed.