JP2002084074A - Multilayer printed wiring board and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer printed wiring board excellent in electric connectivity and reliability as well as in shape keeping characteristics and filmthickness keeping characteristics which comprises an inter-layer resin insulating layer where a via hole of wanted shape is formed. SOLUTION: The multilayer printed wiring board is provided where the inter-layer resin insulating layer and a conductor circuit are sequentially formed on a substrate in which an electronic part is incorporated or housed, with the electronic part and the conductor circuit as well as the upper and lower conductor circuits connected through the via hole. The inter-layer resin insulating layer comprises a photosensitized card type polymer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a build-up multilayer printed wiring board, and more particularly to a multilayer printed wiring board containing electronic components such as IC chips and a method of manufacturing the multilayer printed wiring board.

[0002]

2. Description of the Related Art Conventionally, an IC chip and a printed wiring board are connected by wire bonding, TAB (Tape Automated Bonn).
ding), flip-chip bonding, and other mounting methods. In wire bonding, an IC chip is die-bonded to a printed wiring board with an adhesive, and a pad of the printed wiring board and a pad of the IC chip are connected by a wire such as a gold wire.
In order to protect the IC chip and the wire, sealing with a resin such as a thermosetting resin or a thermoplastic resin has been performed.

[0003] In TAB, a tape on which a large number of conductive wires called leads are formed is used, and the bumps of the IC chip and the pads of the printed wiring board are collectively connected by soldering or the like, and then sealed with resin. I was In flip-chip bonding, an IC chip and a pad portion of a printed wiring board are connected via a bump, and a resin is filled in a gap between the bump and the bump. Further, the electronic components mounted by these methods are driven via a printed wiring board.

[0004]

As described above, in these mounting methods, the IC chip and the printed wiring board are electrically connected to each other through the connecting lead components (wires, leads, bumps). Was. Therefore, if each of these lead components is cut or corroded, IC
The connection between the chip and the printed wiring board is interrupted,
In some cases, this may cause malfunction of the IC chip.

In each of the mounting methods, sealing is performed with a resin such as an epoxy resin to protect the IC chip and lead components. When the resin is filled, bubbles may be contained. In some cases, the bubbles serve as a starting point, leading to destruction of lead components, corrosion of IC pads, and reduction in reliability. In addition, when sealing with a thermoplastic resin, etc., it is necessary to create a resin filling plunger, a mold, etc., according to each component. With sealing with a thermosetting resin, materials such as lead components and solder resist are used. In view of the above, it is necessary to select a resin, which causes an increase in cost.

[0006]

In order to solve such problems, a multilayer printed wiring board in which a semiconductor element such as an IC chip is incorporated or housed in a substrate has been disclosed in recent years. Japanese Patent Application Laid-Open No. 9-321408 discloses a multilayer printed wiring board in which a semiconductor element having a stud bump formed on a die pad is embedded in a substrate, and the stud bump and an upper conductive circuit are electrically connected through a via hole. It has been disclosed. However, in this multilayer printed wiring board, the shape of the stud bumps is onion-like, and the height of the stud bumps varies, so that the interlayer insulating layer formed on the substrate is not uniform in thickness. In some cases, the surface is not flat, and in this case, poor connection may occur in the electrical connection via the via hole. In addition, due to the structure of this multilayer printed wiring board, via-hole openings could not be formed at once, resulting in poor productivity.

Japanese Patent Application Laid-Open No. 10-256429 discloses a multilayer wiring board in which a semiconductor element is housed in a ceramic substrate, and the semiconductor element is electrically connected to a conductor circuit by a flip chip. The ceramic substrate made of alumina, aluminum nitride, or the like used in the multilayer wiring board is inferior in workability in outer shape, so that the semiconductor element is not easily accommodated. As a result, the heights of the pads of the semiconductor element become non-uniform, and as a result, poor connection may occur between the pads and the conductor circuit.

Japanese Patent Application Laid-Open No. H11-126978 discloses a multilayer printed wiring board in which a void is formed in a substrate and a semiconductor element is housed in the void. However, even in such a multilayer printed wiring board having a built-in semiconductor element, when the semiconductor element and the conductor circuit are connected via lead components such as solder, TAB, and wire bonding, the above-described problems occur. Could not be solved. Further, when a semiconductor element is accommodated in a gap portion of a substrate, if a gap exists between the semiconductor element and the substrate, a misalignment of the semiconductor element is likely to occur, leading to a decrease in connection reliability. was there.

Further, the present inventors have previously described an opening formed in a substrate as a multilayer printed wiring board capable of making direct electrical connection with an electronic component such as an IC chip without using a lead component. An IC chip or the like is built in or housed in a through hole or a counterbore portion (hereinafter, both are simply referred to as a built-in portion). Further, an interlayer resin insulating layer and a conductor circuit are laminated on the substrate. A multilayer printed wiring board is proposed in which circuits and circuits between upper and lower conductor circuits via an interlayer resin insulation layer are electrically connected via via holes.

As described above, in the multilayer printed wiring board incorporating the IC chip and the like, since the lead component and the sealing resin are not used for connecting the IC chip and the multilayer printed wiring board, the connection reliability is excellent. The cost can be reduced because an IC chip can be mounted when manufacturing a multilayer printed wiring board. In such a multilayer printed wiring board, since it is necessary to incorporate an IC chip or the like in the substrate,
As a material of the substrate, a resin substrate having excellent external formability is used. Therefore, when forming the interlayer resin insulation layer on the substrate, the formation temperature can not be higher than the temperature to soften the resin substrate, as a material of the interlayer resin insulation layer,
At a temperature lower than this, it is required that the formed interlayer resin insulation layer be excellent in formability and workability and be excellent in shape retention and insulation.

In a conventional printed wiring board, a photosensitive polyimide resin is disclosed as an interlayer resin insulating layer material having excellent heat resistance and insulation properties and excellent opening properties when forming via hole openings. Is disclosed in JP-A-59-151.
No. 498, JP-A-5-304362, JP-A-5-304367, JP-A-6-132409, JP-A-8-23166 and the like.
However, in these multilayer printed wiring boards, since the material of the substrate is a ceramic, alumina or glass substrate, even if the interlayer resin insulating layer is formed by curing at a high curing temperature of 350 ° C. or more, the substrate is softened. On the other hand, in the case of a multilayer printed wiring board using a resin substrate, as a material for an interlayer resin insulating layer, when a conventionally known photosensitive polyimide resin is used, if the curing temperature is too high, If the resin substrate is softened, dissolved or severely carbonized, the photosensitive polyimide resin may not cure sufficiently when the curing temperature is lowered, and the interlayer resin insulation layer formed Was inferior in shape retention and the like, and did not have sufficient connection reliability.

The present inventors have conducted further studies to solve these problems, and as a result, have found that a photosensitive cardo-type polymer is suitable as a material for an interlayer resin insulating layer. completed. The cured product of the photosensitive cardo-type polymer has a rigid chemical structure and a high cross-linking density, and thus has excellent shape retention. Even when cured at a curing temperature of about 200 ° C., the glass transition point is 250 to 350 ° C
Since the temperature is kept between these, the heat resistance is excellent and the curing temperature does not become 350 ° C. or more, so that the resin substrate is not adversely affected. In addition, cardo type polyimide resins to which photosensitivity is imparted by (meth) acrylate conversion have good resolution, excellent shape retention and film thickness retention when forming via hole openings, and via holes after exposure and development processing. Since no resin remains at the bottom of the hole opening, the electrical connection and the reliability via the via hole are excellent.

According to the present invention, there is provided a multilayer printed wiring formed by sequentially forming a conductor circuit and an interlayer resin insulation layer on a substrate on which electronic components are built or housed, and connecting these conductor circuits via via holes. A multilayer printed wiring board, wherein the interlayer resin insulating layer is made of a photosensitive cardo type polymer.

In the multilayer printed wiring board of the present invention, the photosensitive cardo type polymer is preferably a photosensitive cardo type polyimide resin. The photosensitive cardo type polymer has a glass transition temperature of 250 to 300.
C. is desirable.

In the multilayer printed wiring board, it is desirable that a transition layer is formed on pads of the electronic component.

Further, according to the method of manufacturing a multilayer printed wiring board of the present invention, an interlayer resin insulating layer and a conductor circuit are sequentially formed on a substrate in which an electronic component is built or housed, and the electronic component, the conductor circuit, A method of manufacturing a multilayer printed wiring board in which upper and lower conductor circuits are connected via via holes, characterized by including at least the following steps (1) to (4). (1) A step of applying a solution of a photosensitive cardo-type polymer to a substrate on which electronic components are built or housed, or a substrate on which at least one interlayer resin insulating layer and at least one conductive circuit are formed. (2) a step of forming a semi-cured layer of the photosensitive cardo type polymer; and (3) a photo-etching mask placed on the semi-cured layer of the photosensitive cardo type polymer. Forming an opening for a via hole by subjecting the semi-cured layer of the mold polymer to exposure and development; and (4) fully curing the semi-cured layer of the photosensitive cardo-type polymer in which the opening for the via hole is formed. Forming an interlayer resin insulation layer according to

In the production method of the present invention, the photosensitive cardo type polymer is preferably a photosensitive cardo type polyimide resin. Further, the fully cured photosensitive cardo type polymer layer has a glass transition temperature of 250-3.
Desirably, the temperature is 00 ° C.

In the production method of the present invention, before the solution of the photosensitive cardo type polymer is applied, the following (a) to (a)
By performing the step (e), it is desirable to form a transition layer on the pad portion of the electronic component. (A) On a substrate on which electronic components are built or housed,
Forming a metal film; (b) attaching a photosensitive dry film on the metal film; and (c) forming a plating resist by subjecting the photosensitive dry film to exposure and development. And (d) forming a plating layer in the plating resist non-formed portion; and (e) forming the transition layer by removing the plating resist and a metal film present under the plating resist. Process.

In the production method of the present invention, before applying the solution of the photosensitive cardo type polymer,
By performing the step (e), it is also desirable that a transition layer be formed on the pad portion of the electronic component. (A) On a substrate on which electronic components are built or housed,
Forming a metal film, (b) forming a plating layer on the metal film, (c) attaching a photosensitive dry film on the plating layer, and (d) forming the photosensitive film. A step of forming an etching resist by subjecting the dry film to exposure and development; and (e) forming the transition layer by removing the metal film and the plating layer under the portion where the etching resist is not formed by etching. Process.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The multilayer printed wiring board of the present invention
A multilayer printed wiring board comprising a conductor circuit and an interlayer resin insulation layer formed sequentially on a board in which electronic components are built, and these conductor circuits are connected via via holes. The layer is made of a photosensitive cardo type polymer.

According to the multilayer printed wiring board of the present invention, I
Since an electronic component such as a C chip is incorporated in the substrate, no lead component or sealing resin is used in connecting the electronic component to the multilayer printed wiring board. Therefore, the multilayer printed wiring board eliminates various problems that have occurred when an IC chip is mounted via a lead component,
It has excellent electrical connectivity and reliability.

In the multilayer printed wiring board of the present invention, since the interlayer resin insulating layer is made of a photosensitive cardo type polymer, the interlayer resin insulating layer can be formed at a relatively low curing temperature of 150 to 250 ° C. The formed interlayer resin insulation layer is excellent in shape retention and film thickness retention, and the via hole opening provided in the interlayer resin insulation layer has a desired shape. The board has excellent electrical connectivity and reliability.

The cardo-type polymer is a generic name of a polymer having a structure in which a cyclic group is directly bonded to a polymer main chain, and the cardo-type polymer has its structure, that is,
Due to the presence of bulky substituents in the main chain at right angles, the rotation of the polymer main chain is restricted, the conformation of the main chain and side chains is restricted, the intermolecular packing is inhibited, and the aromatic substituents on the side chains are introduced. A phenomenon such as an increase in aromaticity occurs,
Therefore, the glass transition temperature after curing becomes high.
In addition, the cardo-type polymer having such a structure suppresses the mobility of the main chain due to its bulky substituent, and the
Even if cured at below 0 ° C., the crosslink density is high,
Has excellent heat resistance. Furthermore, bulky substituents inhibit the proximity of molecular chains and therefore have excellent solvent solubility.

The cardo type polymer is obtained by copolymerizing a cyclic compound having a carbonyl group (ketone, ester, acid anhydride, imide, etc.) with an aromatic compound such as phenol or aniline or a derivative thereof by a condensation reaction. be able to.

The photosensitive cardo-type polymer has photosensitivity among cardo-type polymers having the above-mentioned structure, and specific examples thereof include a compound represented by the following chemical formula (1). ,

[0026]

Embedded image

A compound represented by the following general formula (2):

[0028]

Embedded image (In the formula, R ¹ represents oxygen, a carbonyl group, a tetrafluoroethylene group, or a single bond.)

A photosensitive cardo type polyester obtained by copolymerizing pyromellitic anhydride and at least one selected from terephthalic acid and its acid chloride is exemplified.

Further, a compound represented by the above general formula (1), a compound represented by the following general formula (3),

[0031]

Embedded image (Wherein, R ² , R ³ , R ⁴ , and R ⁵ are the same or different and each represents hydrogen or a hydrocarbon group having 1 to 5 carbon atoms, and R ⁶ is hydrogen, a carboxyl group, or 2 to 2 carbon atoms. 8
Represents an alkoxycarbonyl group. )

Photosensitive cardo type polyimide obtained by copolymerizing a compound represented by the above general formula (2), pyromellitic anhydride, and at least one selected from terephthalic acid and its acid chloride. And the like. Among these, photosensitive cardo type polyimide resin is desirable. This is because even a cured product obtained by curing at a relatively low temperature has a high glass transition temperature.

The glass transition temperature of the photosensitive cardo type polymer after curing is desirably 250 to 300 ° C.
Since the glass transition temperature in the above range can be achieved by curing the photosensitive cardo-type polymer at a curing temperature of about 200 ° C., it has an adverse effect on the resin substrate during the formation of the interlayer resin insulation layer (softening and melting of the resin substrate). And the like), and the formed interlayer resin insulating layer is excellent in shape retention and heat resistance.

In the above-mentioned multilayer printed wiring board,
It is desirable that a transition layer is formed on a pad portion of the electronic component. The transition layer is a conductor layer provided to enlarge the diameter of the pad provided on the IC chip. The purpose of the transition layer is to eliminate various inconveniences occurring in the pad of the IC chip described below. It is in.

That is, while the diameter of the via hole opening is usually 60 to 80 μm, the diameter of the pad part of the electronic component is about 40 μm, so that the pad is directly connected to the via hole. In such a case, the positional deviation of the via hole occurs due to the small pad diameter, and this may cause poor conduction or disconnection.However, by forming the transition layer, the transition layer is formed. The diameter in the horizontal direction (hereinafter, simply referred to as the diameter) is larger than the diameter of the pad, and the connection with the via hole can be reliably performed. In addition, when the above-mentioned multilayer printed wiring board is manufactured, an acid, an oxidizing agent, an etching solution, or the like may be used. However, by forming a transition layer, direct contact between the pad layer and the acid or the like can be prevented.

The diameter of the above-mentioned transition layer is not particularly limited, and may be appropriately selected in consideration of the diameter of the opening for the via hole and the like, and is desirably 60 to 80 μm, which is almost the same as the diameter of the opening for the via hole.

As a material of the above-mentioned transition layer,
Examples include copper, chromium, nickel, zinc, gold, silver, tin, iron, and the like. Among these, the same material as that of the conductor circuit (via hole) formed thereon is desirable, and copper is usually desirable since the material of the conductor circuit is copper. Further, the transition layer may be composed of one layer, or may be composed of two or more layers, but preferably composed of two or more layers. In particular, when the material of the pad of the IC chip is aluminum, it is desirable that the pad be composed of two layers: a lower layer made of zinc, chromium or nickel and an upper layer made of copper.

The transition layer has a thickness of 1 to 35
μm is desirable. The transition layer thickness is 35μ
If it exceeds m, the shape may be an undercut shape, which may lead to a decrease in the reliability of connection between the IC chip and the via hole. When the transition layer is composed of two or more layers, the thickness of the lower layer is desirably 0.01 to 0.5 μm. The method for forming the transition layer will be described later in detail when describing the manufacturing method of the present invention.

Hereinafter, the multilayer printed wiring board of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view schematically showing an example of the multilayer printed wiring board of the present invention. As shown in FIG. 1, the multilayer printed wiring board 10 includes a resin substrate 30 in which the IC chip 20 is built, an interlayer resin insulation layer 50, and an interlayer resin insulation layer 150. In the interlayer resin insulation layer 50,
Via holes 60 and conductive circuits 58 are formed, and via holes 160 and conductive circuits 158 are formed in interlayer resin insulating layer 150.

The IC chip 20 is covered with a passivation film 22, and an aluminum pad 24 constituting an input / output terminal is formed in an opening of the passivation film 22, and
A positioning mark (not shown) is provided. On the pad 24, a transition layer 38 including a metal film 36 and a plating layer 37 is formed.

On the interlayer resin insulating layer 150, a solder resist layer 70 is provided. In the conductor circuit 158 below the opening 71 of the solder resist layer 70, solder bumps 76 for connection to an external substrate such as a daughter board or a motherboard (not shown) are provided via a nickel plating layer 72 and a gold plating layer 74. .

In the multilayer printed wiring board 10, the IC chip 20 is built in the resin substrate in advance, and the transition layer 38 is provided on the pad 24 of the IC chip 20.
Therefore, without using lead components or sealing resin,
The C chip and the multilayer printed wiring board can be electrically connected.

The resin substrate is not particularly limited as long as it is generally used for a printed circuit board. For example, a reinforcing material such as a glass epoxy resin or a core material such as an epoxy resin, a BT resin, or a phenol resin is used. Examples of the substrate include a substrate made of a resin impregnated and a substrate laminated with a prepreg impregnated with an epoxy resin. Alternatively, a double-sided copper-clad laminate, a single-sided plate, a resin plate having no metal film, a resin film, or the like may be used. Note that the resin substrate and electronic components such as IC chips are joined by an adhesive or the like.

The interlayer resin insulations 50 and 150 are made of the above-mentioned photosensitive cardo type polymer. The interlayer resin insulating layer preferably has a thickness of 5 to 50 μm, and more preferably 15 to 35 μm. While ensuring sufficient insulation between the conductor circuits,
This is because a via hole opening having a desired shape can be formed, so that connection reliability via the via hole is improved.

The multilayer printed wiring board of the present invention can be manufactured, for example, by using the method for manufacturing a multilayer printed wiring board of the present invention described later.

Next, a method for manufacturing a multilayer printed wiring board according to the present invention will be described. In the method for manufacturing a multilayer printed wiring board according to the present invention, an interlayer resin insulating layer and a conductive circuit are sequentially formed on a substrate in which an electronic component is embedded or housed, and the electronic component and the conductive circuit, and upper and lower conductors are formed. A method for manufacturing a multilayer printed wiring board in which circuits are connected via via holes, comprising at least the following steps (1) to (4). (1) A step of applying a solution of a photosensitive cardo-type polymer to a substrate on which electronic components are built or housed, or a substrate on which at least one interlayer resin insulating layer and at least one conductive circuit are formed. (2) a step of forming a semi-cured layer of the photosensitive cardo type polymer; and (3) a photo-etching mask placed on the semi-cured layer of the photosensitive cardo type polymer. Forming an opening for a via hole by subjecting the semi-cured layer of the mold polymer to exposure and development; and (4) fully curing the semi-cured layer of the photosensitive cardo-type polymer in which the opening for the via hole is formed. Forming an interlayer resin insulation layer according to

According to the method for manufacturing a multilayer printed wiring board of the present invention, since the interlayer resin insulating layer is formed using the photosensitive cardo type polymer, the curing temperature is relatively low (150 to 25).
(0 ° C.), it is possible to form an interlayer resin insulating layer having a high crosslinking density and excellent shape retention and heat resistance, and the substrate is not softened or melted when the interlayer resin insulating layer is formed. Further, the photosensitive cardo type polymer used in the production method of the present invention is excellent in opening property by exposure and development processing, so that there is no resin residue in the via hole opening, and a via hole of a desired shape can be formed. .

Further, in the method of manufacturing a multilayer printed wiring board according to the present invention, a transition layer is formed on a pad of an IC chip built in a substrate, thereby providing a multilayer connection excellent in connection reliability between a pad and a conductive circuit. A printed wiring board can be manufactured.

First, the steps (1) to (4), that is, the step of forming an interlayer resin insulating layer will be described.
Details will be described later.

In the manufacturing method of the present invention, when forming the interlayer resin insulating layer, first, a substrate in which electronic components such as an IC chip are built, or at least a lower interlayer resin insulating layer and a conductor circuit are formed. A photosensitive cardo type polymer solution is applied to the substrate formed one by one. It is desirable to adjust the viscosity of the photosensitive cardo type polymer solution to 5 to 49 Pa · s. This is because it is easy to apply the composition on the substrate, and it is easy to form it uniformly. The viscosity can be adjusted by diluting with a solvent such as xylene.

The method for applying the solution of the photosensitive cardo type polymer is not particularly limited as long as the solution can be uniformly applied on a substrate. For example, a curtain coater method, a roll coater method, A coating method using a normal printing machine or the like can be used.

Next, a semi-cured layer of a photosensitive cardo type polymer is formed. The semi-cured layer is formed by drying the applied photosensitive cardo type polymer at a temperature of 80 to 200 ° C. for 10 to 60 minutes. Here, the semi-cured layer of the photosensitive cardo type polymer refers to a layer of the photosensitive cardo type polymer in a semi-cured state or a B-stage state which is hardened to some extent but can be dissolved by a solvent or the like.

Next, a photo-etching mask is placed on the semi-cured layer of the photosensitive cardo-type polymer, and then the semi-cured layer of the photosensitive cardo-type polymer is exposed to light and developed to form via holes. Forming openings. The exposure / development processing is, for example, 100 to 800 mj / cm.
Irradiation with ultraviolet light under the condition ² is followed by development using an organic or inorganic type developer.

Subsequently, the photosensitive cardo type polymer semi-cured layer in which the opening for the via hole is formed is fully cured to form an interlayer resin insulating layer. The temperature for performing the main curing is 150
~ 300 ° C is desirable. When the temperature is lower than 150 ° C.,
The semi-cured layer of the photosensitive cardo-type polymer cannot be cured sufficiently. On the other hand, when the temperature exceeds 300 ° C., the material resin of the substrate with a built-in IC may be softened or dissolved. The desirable glass transition temperature of the interlayer resin insulating layer (the layer of the fully cured cardo-type polymer) formed in the production method of the present invention is 250 to 300 ° C., and by performing the full curing at a temperature in the above range, This is because the cross-linking between the polymers proceeds, and an interlayer resin insulating layer having the above glass transition temperature can be formed.

Further, the above-mentioned main curing may be carried out by a step cure in which the temperature is raised after maintaining for a certain time in each temperature section. Thereby, the solvent and water remaining in the photosensitive cardo type polymer semi-cured layer can be completely removed. Through these steps,
An interlayer resin insulating layer made of a cardo-type polymer having excellent shape retention and heat resistance can be formed.

Next, all steps of manufacturing the multilayer printed wiring board of the present invention will be described in the order of steps with reference to FIGS. (1) First, glass epoxy resin or BT (bismaleimide triazine) with built-in electronic components such as IC chips
Substrate made of resin or the like (hereinafter, also referred to as IC built-in substrate) 3
0 is used as a starting material (see FIG. 5A). The upper portion of the IC chip 20 is covered with a passivation film 22, and a pad 24 made of aluminum or the like constituting an input / output terminal is provided in the opening of the passivation film 22.
Is formed.

The method for embedding the IC chip or the like in the substrate is not particularly limited. For example, a recess for embedding the IC chip is formed on one surface of the substrate by counterboring, and then the IC is inserted into the recess with an adhesive material. A method of fixing a chip, a method of forming a through hole for accommodating an IC chip in a substrate, accommodating the IC chip in the through hole, and laminating this substrate and a substrate having no through hole, etc. Is mentioned.

(2) Next, the IC chip is positioned with respect to the substrate by the following method. That is, the positioning marks provided at the four corners of the IC chip are photographed by a camera, and the positioning of the IC chip is performed by forming the positioning marks with laser at the four corners of the IC built-in substrate based on the positioning marks.

(3) Next, a transition layer is formed on the pads formed on the IC chip as required. The transition layer may be formed as necessary.However, when a transition layer is formed, a displacement occurs between the transition layer and the via hole because the diameter of the transition layer is larger than the diameter of the pad. This makes it possible to more reliably connect the pad and the via hole.

As a specific method for forming the above-mentioned transition layer, a method including the following steps (a) to (e) (hereinafter, referred to as a first transition layer forming method) can be used. (A) First, the metal film 36 is formed on the entire surface of the IC-embedded substrate 30 (see FIG. 5B). The metal film 36 is desirably formed by performing physical vapor deposition such as sputtering. The metal film 36 is formed using, for example, one or more metals such as chromium, copper, nickel, zinc, gold, tin, and iron. In some cases, two or more metal films 36 may be formed using different metals.

After performing sputtering or the like, electroless plating is performed to form a metal film 36 having two or more layers.
It may be. In this case, a layer made of chromium, nickel or zinc is formed by sputtering or the like, and thereafter,
It is desirable to form a layer made of copper by electroless plating. Considering that the material of the conductive circuit formed on the metal film 36 is usually copper, it is preferable that the material of the metal film 36 is also copper.
Is made of aluminum, it is not preferable to form the metal film 36 made of copper directly on the pad, as described above, because the pad 24 may be discolored. On the other hand, a layer made of chromium, nickel, or zinc is formed directly on the pad 24, and a layer made of copper is formed on the layer to prevent discoloration of the pad 24 and to improve the connection reliability with the via hole. It is possible to obtain a metal film 36 having excellent characteristics.

When the metal film 36 is formed by sputtering or the like and electroless plating, the thickness of the layer formed by sputtering or the like is preferably 0.01 to 0.5 μm. By physical vapor deposition such as sputtering, 0.5
This is because it is difficult to uniformly form a layer having a thickness exceeding μm. Further, the thickness of the layer formed by electroless plating is desirably 0.01 to 5.0 μm. 0.01 μm
If it is less than 5, a plating film cannot be formed on the entire surface, and if it exceeds 5.0 μm, it may be difficult to remove by etching, or the positioning mark may be buried, and the positioning mark may not be recognized. A more desirable range is 0.1 to 1.0 μm.

(B) Next, a photosensitive dry film is attached on the metal film. The photosensitive dry film is not particularly limited, and commercial products conventionally used for forming a plating resist can be used. (C) Next, a mask on which a pattern corresponding to the pad 24 of the IC chip 20 is formed is placed on the photosensitive dry film, and is subjected to exposure and development treatments, so that plating with an opening at the top of the pad 24 is performed. A resist 35 is formed.

(D) Thereafter, a plating layer 37 is formed by plating on the portion where the plating resist is not formed.
(A)). The plating treatment may be electroless plating, electrolytic plating, or both. As a material of the plating layer 37, for example, copper,
Examples thereof include those made of nickel, gold, silver, zinc, iron, and the like. Among these, copper is desirable because it is excellent in electrical characteristics and economy, and the material of the conductor circuit of the multilayer printed wiring board formed in a later step is desirably copper. The thickness of the plating layer 37 is 1 to 15 μm.
Is desirable.

(E) Next, after the plating resist 35 is removed, the metal film 36 existing under the plating resist 35 is removed.
Is removed to form a transition layer 38 (see FIG. 6B). The removal of the metal film 36 is performed using an etching solution such as a mixed solution of sulfuric acid and hydrogen peroxide, sodium persulfate, ammonium persulfate, ferric chloride, and cupric chloride.

As described above, when the transition layer is formed by the first transition layer forming method, it is possible to prevent the occurrence of resin residue on the pad when forming the interlayer resin insulating layer in a later step. In addition, since discoloration and dissolution of the pad can be prevented when the pad is immersed in an acid, an oxidizing agent, or an etching solution, or through various annealing processes, the connection between the pad and the via hole can be more reliably performed. Things.

(4) Next, if necessary, a roughened surface or a roughened layer (hereinafter, simply referred to as a roughened surface) 38α is formed on the surface of the transition layer 38 (FIG. 6).
(C)). By forming the roughened surface, the connection between the transition layer 38 and the interlayer resin insulating layer or the via hole becomes more reliable. The roughened surface 38
α can be formed by etching, blackening reduction, plating, or the like.

The above etching treatment can be performed, for example, using an etching solution containing an organic acid and a cupric complex. Examples of the organic acid include formic acid, acetic acid, propionic acid, butyric acid, valeric acid, caproic acid, acrylic acid, crotonic acid, oxalic acid, malonic acid, succinic acid, glutaric acid, maleic acid, benzoic acid, glycolic acid, Lactic acid, malic acid, sulfamic acid and the like. These may be used alone or in combination of two or more. In the mixed solution, the content of the organic acid is desirably 0.1 to 30% by weight. Maintain the solubility of oxidized copper, and
This is because catalyst stability can be ensured.

As the cupric complex, a cupric complex of an azole is desirable. This cupric complex of azoles is
It acts as an oxidizing agent for oxidizing metallic copper and the like. As the azoles, for example, diazole, triazole, tetrazole and the like can be mentioned. Among these, imidazole, 2-methylimidazole, 2-ethylimidazole, 2-ethyl-4-methylimidazole, 2-phenylimidazole, and 2-undecylimidazole are desirable. In the etching solution, the content of the cupric complex is desirably 1 to 15% by weight. This is because it is excellent in solubility and stability, and can also dissolve noble metals such as Pd constituting the catalyst core.

As a specific method of the blackening reduction treatment, NaOH (10 g / l), NaClO ₂ (40 g /
l), a blackening treatment using an aqueous solution containing Na ₃ PO ₄ (6 g / l) as a blackening bath, and NaOH (10 g / l),
A method of performing a reduction treatment using an aqueous solution containing NaBH ₄ (6 g / l) as a reduction bath is exemplified.

As a specific method of the plating process,
Copper sulfate (1-40 g / l), nickel sulfate (0.1-
6.0 g / l), citric acid (10-20 g / l), sodium hypophosphite (10-100 g / l), boric acid (1
0 to 40 g / l) and a surfactant (Surfynol 465, manufactured by Nissin Chemical Industry Co., Ltd.) (0.01 to 10 g / l)
And a method in which electroless plating is performed in an electroless plating bath having a pH of 9 and the like.

(5) Next, as described above, a solution of the photosensitive cardo type polymer is applied onto the substrate 30 with a built-in IC, and then dried under heating to form a semi-cured layer of the photosensitive cardo type polymer. After forming a via hole opening 48 in the semi-cured layer 50 ′ of the photosensitive cardo type polymer, a full curing is performed to form the interlayer resin insulating layer 50. (See FIG. 7B).

(6) Then, if necessary, a roughened surface 50α is formed on the surface of the interlayer resin insulating layer 50 (see FIG. 7C). The roughened surface 50α is formed, for example, by performing a plasma process. Further, the sputtering described later may be directly performed without forming the roughened surface 50α.

(7) Next, on the surface of the interlayer resin insulation layer 50,
If necessary, a thin film conductor layer 52 made of copper, nickel, tin, zinc, cobalt, thallium, lead, an alloy thereof, or the like is formed (see FIG. 8A). The thin film conductor layer 52 may be a single layer or may be composed of two or more layers. The thickness of the thin film conductor layer 52 is desirably 0.1 to 1.0 μm.

The method for forming the thin film conductor layer 52 is as follows.
For example, a method such as sputtering and electroless plating can be used. In the above sputtering, for example, when a Ni—Cu alloy is used as a target, the above SV-4540 is used, an argon gas is used as an inert gas, and a pressure of 0.
It can be performed under the conditions of 6 Pa, a temperature of 80 ° C., a power of 200 W, and a time of 5 minutes. When the thin film conductor layer 52 is formed by electroless plating, for example,
Palladium catalyst (made by Atotech) on the surface of
The catalyst nuclei are adhered to the surface of the interlayer resin insulating layer and the inner wall surface of the via hole opening by providing a substrate, and then the substrate is immersed in an aqueous electroless plating solution to form an electroless plating layer ( The thin film conductor layer) 52 can be formed.

(8) Next, a plating resist 54 is formed using a dry film on a part of the interlayer resin insulating layer 50 on which the thin film conductor layer 52 has been formed, and then the electrolytic plating is performed using the thin film conductor layer 52 as a plating lead. 8 to form an electrolytic plating layer 56 in the above-mentioned plating resist non-formed portion.
(B)). It is desirable to use copper plating as the electrolytic plating. At this time, the via hole opening may be filled with electrolytic plating to form a field via structure, and after filling the via hole opening with a conductive paste or the like, a lid plating layer may be formed thereon to form a field via structure. Good. By forming a field via structure, a via hole can be provided immediately above the via hole.

(9) Next, after the plating resist 54 is removed, the thin film conductor layer 52 existing under the plating resist 54 is dissolved and removed by etching, and the conductor composed of the thin film conductor layer 52 and the electrolytic plating layer 56 is removed. A circuit 58 and a via hole 60 are formed. When the thin film conductor layer 54 is formed by electroless plating after the catalyst is attached, acid,
Alternatively, the catalyst on the interlayer resin insulating layer 50 may be removed using an oxidizing agent. By removing palladium used as a catalyst, a decrease in electrical characteristics can be prevented.

Further, if necessary, roughened surfaces 58α and 60α are formed on the surfaces of the conductor circuit 58 and the via hole 60 (see FIG. 8C). The roughened surfaces 58α and 60α are
It can be formed by a method similar to the method used when forming the roughened surface on the surface of the transition layer 38.

(10) Next, if necessary, (6) to
By repeating the process of (10), the interlayer resin insulating layer 150 and the conductor circuit 158 (via hole 16
0 (including FIG. 9A) (see FIG. 9A).

(11) Next, a solder resist layer 70 is formed on the substrate surface including the outermost conductive circuit 158. Examples of the solder resist layer include those made of a polyphenylene ether resin, a polyolefin resin, a fluororesin, a thermoplastic elastomer, a solder resist resin composition, or the like. After the uncured resin (resin composition) is applied by a roll coater method or the uncured resin film is thermocompression-bonded, the solder resist layer is subjected to opening treatment such as laser treatment, exposure / development treatment, or the like. Then, it is formed by performing a curing treatment or the like (see FIG. 9B).

Examples of the solder resist resin composition include (meth) acrylate of novolak type epoxy resin, imidazole curing agent, difunctional (meth) acrylate monomer, and (meth) acrylic acid having a molecular weight of about 500 to 5,000. Ester polymers, thermosetting resins such as bisphenol-type epoxy resins, photosensitive monomers such as polyvalent acrylic monomers, paste-like fluids containing glycol ether solvents and the like, and the viscosity thereof is 25 ° C. Is preferably adjusted to 1 to 10 Pa · s.

(Meth) of the above novolak type epoxy resin
Examples of the acrylate include an epoxy resin obtained by reacting glycidyl ether of phenol novolak or cresol novolac with acrylic acid, methacrylic acid, or the like. The bifunctional (meth) acrylic acid ester monomer is not particularly limited, and examples thereof include various diols and esters of acrylic acid and methacrylic acid.

(12) Thereafter, the solder resist layer 70
A solder pad is provided by forming a nickel plating layer 72, a gold plating layer 74, and the like on the conductor circuit 158 in the opening 71, and a solder paste is printed on the solder pad and reflowed at 200 ° C. Thus, the solder bumps 76 are formed. Thus, a multilayer printed wiring board having the IC chip 20 built in the substrate and having the solder bumps can be obtained (see FIG. 1). Also, after printing a solder paste in the opening of the solder resist layer, a conductive pin is placed in the opening, and reflowed at 200 ° C., thereby connecting a PGA (Pin Grid Ar) for connecting to an external terminal.
ray) may be provided as a multilayer printed wiring board.

In the manufacturing method of the present invention, instead of the first transition layer forming method (step (3)),
The transition layer 38 may be formed using a method including the following steps (a) to (e) (hereinafter, referred to as a second transition layer forming method). Note that when the second transition layer forming method is used, the transition layer 3
Except for the step of forming 8, the above manufacturing method may be used. Regarding the second transition layer forming method,
This will be described with reference to FIG.

(A) First, a metal film 36 'is formed on the entire surface of the IC-embedded substrate in the same manner as in the above-described step (a) of the first transition layer forming method (see FIG. 12A). (B) Next, a plating layer 37 'is formed on the entire surface of the metal film by electroless plating and / or electrolytic plating.
As the plating layer 37 ', an electrolytic copper plating layer is desirable (see FIG. 12B). The thickness of the plating layer 37 'is 1 to
15 μm is desirable. When the thickness exceeds 15 μm,
This is because an undercut occurs at the time of etching to be described later, and a gap is generated at an interface between the formed traffic layer and the pad 24, which may cause separation between the two.

(C) Next, a photosensitive dry film is attached on the plating layer. The photosensitive dry film is not particularly limited, and a commercially available product conventionally used for forming an etching resist may be used. (D) Next, a mask having a pattern corresponding to the transition layer to be formed is placed on the photosensitive dry film, and subjected to exposure and development treatments, so that a portion corresponding to the portion where the transition layer is not formed is formed. An etching resist 39 having openings is formed (see FIG. 12C).

(E) Further, the metal film 36 'and the plating layer 37' under the portion where the etching resist 39 is not formed are removed by etching to form the transition layer 38 (see FIG. 12D). The etching treatment may be performed using an etching solution such as a sulfuric acid / hydrogen peroxide aqueous solution, an aqueous solution of a persulfate such as ferric chloride, cupric chloride, or ammonium persulfate.

As described above, even when the transition layer is formed by the second transition layer forming method, it is possible to prevent the occurrence of resin residue on the pad when forming the interlayer resin insulating layer in a later step. In addition, since discoloration and dissolution of the pad can be prevented when the pad is immersed in an acid, an oxidizing agent or an etchant, or undergoes various annealing steps, the connection between the pad and the via hole is more reliably performed. It can be.

In addition, a plasma treatment with oxygen, carbon tetrachloride, or the like may be appropriately performed for a character printing step for forming product recognition characters or the like or for modifying a solder resist layer.
Although the above method is based on the semi-additive method, a full-additive method may be employed.

As described above, by using the manufacturing method of the present invention, an electronic component such as an IC chip is built in the substrate, and the IC chip and the multilayer printed wiring board are electrically connected directly without the lead component. Can be manufactured. Further, in the manufacturing method of the present invention, since a photosensitive cardo type polymer is used for forming the interlayer resin insulating layer, a relatively low curing temperature (150 to 250) is used.
C), an interlayer resin insulating layer having a high crosslinking density and excellent shape retention and heat resistance can be formed, and the substrate is not softened or melted when the interlayer resin insulating layer is formed. In addition, since the photosensitive cardo-type polymer has excellent opening properties due to exposure / development processing, in the manufacturing method of the present invention, there is no resin residue in the via hole opening, and a via hole having a desired shape can be formed. it can.

[0091]

The present invention will be described in more detail below.

(Example 1) (1) An IC chip 20 in which an upper part is covered with a passivation film 22 and an aluminum pad 24 is formed as an input / output terminal in an opening of the passivation film 22 has a thickness of 0. A BT (bismaleimide triazine) resin substrate (hereinafter, also referred to as an IC built-in BT substrate) 30 of 0.8 μm was used as a starting material. (See FIG. 2A). First, the positioning marks (not shown) provided at the four corners of the IC chip 20 are photographed by a camera, and the positioning marks are formed at the four corners of the IC built-in substrate 30 with a laser with reference to the positioning marks. Was positioned.

(2) Next, a solution of a photosensitive cardo type polymer whose viscosity has been adjusted to 30 Pa · s in advance by a curtain coater is applied to the surface of the substrate including the IC chip. After drying for half an hour, a semi-cured layer 50 'of a photosensitive cardo type polymer was formed.
(B)).

The photosensitive cardo type polymer used here was bis-phenolfluorene-hydroxyacrylate represented by the above chemical formula (1) and the above-mentioned general formula (3)
A random copolymer obtained by reacting bis-aniline-fluorene in which R ² , R ³ , R ⁴ , R ⁵ and R ⁶ are hydrogen with pyromellitic anhydride at a molar ratio of 1: 4: 5. It is a polymer.

Next, a photo-etching mask having a black circle drawn in a portion corresponding to a portion where an opening for a via hole is formed is placed on the semi-cured layer 50 'of the photosensitive cardo type polymer. Irradiation was carried out under the condition of / cm ² to perform exposure / development processing to form a via hole opening 48. Thereafter, main curing was performed at 250 ° C. for 120 minutes to form an interlayer resin insulating layer 50 (see FIG. 2C). The glass transition temperature of the interlayer resin insulating layer formed here was 260 ° C.

(3) Next, S manufactured by Japan Vacuum Engineering Co., Ltd.
V-4540, argon gas was used as an inert gas, electric power 200 W, gas pressure 0.6 Pa, temperature 70
Plasma treatment was performed for 2 minutes at a temperature of ° C. to form a roughened surface 50α on the surface of the interlayer resin insulating layer 50 (see FIG. 2D).

(4) Further, after replacing the argon gas inside using the same apparatus, sputtering using Zn as a target was performed at a pressure of 0.6 Pa, a temperature of 80 ° C., and a power of 20 ° C.
0 W for 5 minutes, and the thickness of Zn is 0.1 mm.
A 1 μm thin-film conductor layer 52 was formed on the surface of the interlayer resin insulation layer 50 (see FIG. 3A).

(5) Next, a plating resist 54 is formed using a dry film on a part of the interlayer resin insulation layer 50 on which the thin film conductor layer 52 has been formed. Perform electrolytic copper plating under the conditions,
An electrolytic copper plating layer 56 was formed on the portion where the plating resist was not formed (see FIG. 3B).

[0099]

(6) Next, after the plating resist is removed, the thin film conductor layer 5 existing under the plating resist is removed.
2 was dissolved and removed by etching to form a 16 μm-thick conductor circuit 58 and via hole 60 comprising the thin-film conductor layer 52 and the electrolytic plating layer 56. Thereafter, the conductor circuit 58
The etching liquid was sprayed on the substrate (including the via hole 60) formed thereon to form a roughened surface 58α on the surface of the conductive circuit 58 (see FIG. 3C). Here, as the etching solution, a mixture of 10 parts by weight of an imidazole copper (II) complex, 7 parts by weight of glycolic acid, 5 parts by weight of potassium chloride, and 78 parts by weight of ion-exchanged water was used.

(7) Next, by repeating the steps (2) to (6), an upper interlayer resin insulation layer 150 and a conductor circuit 158 (including the via hole 160) are further formed (FIG. 4A). )reference).

(8) Next, a cresol novolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) so as to have a concentration of 60% by weight, and a 50% epoxy group was acrylated. Oligomer for imparting properties (molecular weight: 4000) 46.67
15 parts by weight of a bisphenol A type epoxy resin (trade name: Epicoat 1001 manufactured by Yuka Shell Co., Ltd.) 80% by weight dissolved in methyl ethyl ketone, imidazole curing agent (trade name: 2E4MZ-CN manufactured by Shikoku Chemicals Co., Ltd.)
1.6 parts by weight, 3 parts by weight of a polyfunctional acrylic monomer (manufactured by Kyoei Chemical Co., Ltd., trade name: R604) as a photosensitive monomer,
Also polyvalent acrylic monomer (Kyoei Chemical Co., Ltd., trade name:
1.5 parts by weight of DPE6A) and 0.71 part by weight of a dispersion defoaming agent (manufactured by San Nopco Co., trade name: S-65) are placed in a container, stirred and mixed to prepare a mixed composition. Of benzophenone (manufactured by Kanto Kagaku) and 0.2 parts by weight of Michler's ketone (manufactured by Kanto Kagaku) as a photosensitizer were added to the mixture to give a viscosity of 25.
A solder resist composition adjusted to 2.0 Pa · s at ℃ was obtained. The viscosity was measured using a B-type viscometer (manufactured by Tokyo Keiki Co., DVL-B type) at 60 rpm with rotor N
o. In the case of 4, 6 rpm, the rotor No. According to 3.

(9) Next, the above-mentioned solder resist composition is applied on the substrate 30 to a thickness of 20 μm,
After drying for 30 minutes at 70 ° C for 30 minutes,
A 5 mm-thick photomask on which the pattern of the solder resist resist opening is drawn is applied to the solder resist layer 70.
And exposed to ultraviolet light of 1000 mJ / cm ² ,
Developed with a DMTG solution, and an opening 7 having a diameter of 200 μm
1 was formed (see FIG. 4B).

(10) Next, the substrate on which the solder resist layer 70 has been formed is replaced with nickel chloride (2.3 × 10 ^-1 mol).
/ L), sodium hypophosphite (2.8 × 10 ^-1 mol)
/ L), sodium citrate (1.6 × 10 ^-1 mol /
l) containing 2 to the electroless nickel plating solution of pH = 4.5
By immersing for 0 minute, a nickel plating layer 72 having a thickness of 5 μm was formed in the opening 71. Furthermore, the substrate, gold potassium cyanide ^{(7.6 × 10 -3 mol / l} ), ammonium chloride ^{(1.9 × 10 -1 mol / l} ), sodium citrate (1.2 × 10 ^-1 mol / L), and immersed in an electroless plating solution containing sodium hypophosphite (1.7 × 10 ^-1 mol / l) at 80 ° C. for 7.5 minutes to form a layer having a thickness of 0% on the nickel plating layer 72. By forming a gold plating layer 74 of 0.03 μm, a solder pad 75 was formed on the conductor circuit 158 (see FIG. 4C).

(11) Thereafter, the solder resist layer 70
Print the solder paste in the opening 71 of
The solder bumps 76 were formed by reflow. As a result, a multilayer printed wiring board 100 incorporating the IC chip 20 and having the solder bumps 76 was obtained (FIG. 10).
reference).

(Example 2) In step (4) of Example 1, instead of sputtering using Zn as a target,
Sputtering with a target of Cr at a pressure of 0.6
Performed under the conditions of Pa, a temperature of 80 ° C., a power of 200 W, and a time of 5 minutes. A multilayer printed wiring board was obtained.

(Example 3) In step (2) of Example 1, as photosensitive cardo type polymer, bis-phenolfluorene-hydroxyacrylate, bis-aniline-fluorene, pyromellitic anhydride and the above-mentioned general formula In (2), benzophenonetetracarboxylic dianhydride in which R ¹ is a carbonyl group is used in a molar ratio of 1: 4:
Using a random copolymer obtained by reacting at 3: 2,
Further, in step (4), instead of sputtering using Zn as a target, sputtering using Ni as a target is performed at a pressure of 0.6 Pa, a temperature of 80 ° C., and a power of 20 ° C.
0 W for 5 minutes, and the thickness of Ni is 0.1 mm.
A multilayer printed wiring board was obtained in the same manner as in Example 1, except that a thin film conductor layer 52 of 1 μm was formed on the surface of the interlayer resin insulating layer 50. The glass transition temperature of the interlayer resin insulation layer is
260 ° C.

(Embodiment 4) (1) BT with built-in IC having a thickness of 0.8 μm similar to that of Embodiment 1
The substrate 30 was used as a starting material (see FIG. 5A). First,
The positioning marks provided at the four corners of the IC chip 20 are photographed by a camera, and the IC is referred to based on the positioning marks.
The positioning of the IC chip was performed by forming positioning marks at the four corners of the built-in substrate 30 with a laser.

(2) Next, sputtering using Zn as a target was performed by SV-454 manufactured by Japan Vacuum Engineering Co., Ltd.
0, gas pressure 0.6 Pa, temperature 80 ° C., power 200
W, for 5 minutes, to form a 0.1 μm thick Zn film on the entire surface of the BT substrate 30 with built-in IC.
By forming an electroless copper plating film having a thickness of 0.7 μm on the film by electroless copper plating, a metal film 36 composed of zinc and copper was formed (see FIG. 5B).

(3) Next, after a photosensitive dry film is stuck on the metal film 36, a mask on which a pattern corresponding to the pad 24 is formed is placed on the photosensitive dry film. By performing the development processing, the pad 2
A plating resist 35 having an opening at the upper part of No. 4 was formed. Further, an electrolytic copper plating layer 37 was provided on the portion where the plating resist 35 was not formed under the following conditions (see FIG. 6A).

[0111]

(4) Further, after the plating resist 35 is removed, the metal film 36 under the plating resist 35 is removed by etching, so that the pads 24 of the IC chip are removed.
A transition layer 38 having a diameter of 60 μm was formed thereon (see FIG. 6B). Note that a mixed solution of sulfuric acid and hydrogen peroxide was used as an etching solution.

(5) Next, an etching solution is sprayed on the BT substrate 30 with built-in IC on which the transition layer 38 is formed, and the roughened surface 38α is formed on the surface of the transition layer 38.
Was formed (see FIG. 6C). Here, as the etching solution, a mixture of 10 parts by weight of an imidazole copper (II) complex, 7 parts by weight of glycolic acid, 5 parts by weight of potassium chloride, and 78 parts by weight of ion-exchanged water was used.

(6) Next, on the IC built-in BT substrate 30 on which the transition layer 38 has been formed,
After applying a solution of the photosensitive cardo type polymer adjusted to Pa · s with a curtain coater,
After drying for a minute, a semi-cured layer 50 ′ of a photosensitive cardo type polymer was formed (see FIG. 7A). The same photosensitive cardo type polymer as in Example 1 was used as the photosensitive cardo type polymer.

Next, a photo-etching mask having a black circle drawn in a portion corresponding to a portion where an opening for a via hole is formed is placed on the semi-cured layer of the photosensitive cardo type polymer 50 ′.
After irradiating with ultraviolet light under the condition of 400 mj / cm ² , and then developing, performing exposure and development processing to form a via hole opening 48, and then 270 ° C.
The main curing was performed by drying under the condition of 120 minutes to form the interlayer resin insulating layer 50 (see FIG. 7B).

(7) Next, S manufactured by Japan Vacuum Engineering Co., Ltd.
V-4540, argon gas was used as an inert gas, electric power 200 W, gas pressure 0.6 Pa, temperature 70
Plasma treatment was performed at 2 ° C. for 2 minutes to form a roughened surface 50α on the surface of the interlayer resin insulating layer 50 (see FIG. 7C).

(8) Further, by applying a palladium catalyst (manufactured by Atotech) to the surface of the substrate having the roughened surface, the surface of the interlayer resin insulating layer 50 and the inner wall surface of the via hole opening 48 are formed. Catalyst nuclei were deposited.

(9) Next, the substrate is immersed in an electroless copper plating aqueous solution having the following composition to form a thin-film conductor layer 52 having a thickness of 0.6 to 0.9 μm on the entire surface of the roughened surface 50α. (See FIG. 8A).

[Electroless plating aqueous solution] NiSO ₄ 0.003 mol / l tartaric acid 0.200 mol / l copper sulfate 0.030 mol / l HCHO 0.050 mol / l NaOH 0.100 mol / l α, α ' -Bipyridyl 40 mg / l Polyethylene glycol (PEG) 0.10 g / l [Electroless plating conditions] 40 minutes at a liquid temperature of 35 ° C

(10) Next, a plating resist is formed using a dry film on a part of the interlayer resin insulation layer 50 on which the thin film conductor layer 52 has been formed, and then the thin film conductor layer 52 is used as a plating lead to form the plating resist (3). 8) Electrolytic copper plating was performed under the same conditions as in (1), and an electrolytic copper plating layer 56 was formed in the plating resist non-formed portion (see FIG. 8B).

(11) Next, after the plating resist is removed, the thin film conductor layer 5 existing under the plating resist is removed.
2 was dissolved and removed by etching to form a conductor circuit 58 and a via hole 60 each having a thickness of 16 μm comprising the thin film conductor layer 52 and the electrolytic plating film 56. Thereafter, the conductor circuit 58
An etching solution was sprayed onto the substrate on which the via holes 60 (including the via holes 60) were formed to form roughened surfaces 58α and 60α on the surfaces of the conductor circuits 58 and the via holes 60 (see FIG. 8C). As the etching solution, the same etching solution as that used in forming the roughened surface on the surface of the transition layer in the step (5) was used.

(12) Next, by repeating the steps (6) to (11), the upper interlayer resin insulation layer 15
0 and conductor circuit 158 (including via hole 160)
Was formed (see FIG. 9A).

(13) Next, a solder resist composition was obtained in the same manner as in Example 1. Further, the solder resist composition is applied to a thickness of 20 μm on the IC built-in substrate 30 having the conductor circuit 158 formed on the outermost layer.
After performing a drying process at 0 ° C. for 30 minutes at 70 ° C., a 5 mm-thick photomask on which a pattern of the opening of the solder resist resist is drawn is brought into close contact with the solder resist layer 70, and an ultraviolet ray of 1000 mJ / cm ² is applied. And developed with a DMTG solution to form an opening 71 having a diameter of 200 μm (see FIG. 9B).

(14) Next, the substrate on which the solder resist layer 70 is formed is coated with nickel chloride (2.3 × 10 ^-1 mol).
/ L), sodium hypophosphite (2.8 × 10 ^-1 mol)
/ L), sodium citrate (1.6 × 10 ^-1 mol /
l) containing 2 to the electroless nickel plating solution of pH = 4.5
By immersing for 0 minute, a nickel plating layer 72 having a thickness of 5 μm was formed in the opening 71. Furthermore, the substrate, gold potassium cyanide ^{(7.6 × 10 -3 mol / l} ), ammonium chloride ^{(1.9 × 10 -1 mol / l} ), sodium citrate (1.2 × 10 ^-1 mol / L), and immersed in an electroless plating solution containing sodium hypophosphite (1.7 × 10 ^-1 mol / l) at 80 ° C. for 7.5 minutes to form a layer having a thickness of 0% on the nickel plating layer 72. By forming a gold plating layer 74 of 0.03 μm, a solder pad 75 was formed on the conductor circuit 158 (see FIG. 9C).

(15) Thereafter, the solder resist layer 70
Print the solder paste in the opening 71 of
To form the solder bumps 76. Thus, a multilayer printed wiring board 10 having the IC chip 20 built therein and having the solder bumps 76 was obtained (see FIG. 1).

(Example 5) In step (2) of Example 4, the same random copolymerization as in Example 3 was used as the photosensitive cardo type polymer. In step (2), Zn was used as a target. Instead of sputtering
Sputtering with a target of Cr at a pressure of 0.6
The test was carried out under the conditions of Pa, a temperature of 80 ° C., a power of 200 W, and a time of 5 minutes.
A multi-layer printed wiring board was obtained in the same manner as in Example 4 except that it was formed on the entire surface of the built-in BT substrate 30.

(Embodiment 6) (1) BT with built-in IC having a thickness of 0.8 μm similar to that of Embodiment 1
The substrate 30 was used as a starting material (see FIG. 5A). First,
The positioning marks provided at the four corners of the IC chip 20 are photographed by a camera, and the IC
The positioning of the IC chip was performed by forming positioning marks at the four corners of the built-in substrate 30 with a laser.

(2) Next, sputtering using Ni as a target was performed by SV-454 manufactured by Nippon Vacuum Engineering Co., Ltd.
0, gas pressure 0.6 Pa, temperature 80 ° C., power 200
W, for 5 minutes, forming a 0.1 μm thick Ni film on the entire surface of the BT substrate 30 with built-in IC.
An electroless copper plating film having a thickness of 0.7 μm was further formed on the film by electroless copper plating, thereby forming a metal film 36 ′ made of nickel and copper (see FIG. 12A).

(3) Next, the fourth embodiment is formed on the metal film 36 '.
Plating electrolytic copper under the same conditions as in step (3) of
An electrolytic copper plating layer 37 'was provided on the entire surface of the metal film 36' (see FIG. 12B).

(4) Further, the electrolytic copper plating layer 37 '
A photosensitive dry film is adhered on top, and a mask on which a pattern corresponding to the transition layer is formed is placed on the photosensitive dry film, and exposed and developed to perform a process corresponding to a transition layer non-formed portion. An etching resist 39 having an opening at the part to be formed was formed (FIG. 12
(C)).

(5) Further, by removing the metal film 36 'and the electrolytic copper plating layer 37' under the portion where the etching resist 39 is not formed by etching, a transition layer 38 having a diameter of 60 μm is formed on the IC chip (FIG. 12 (D)). In this etching process, an etching solution composed of sulfuric acid and an aqueous solution of hydrogen peroxide was used.

(6) In the same manner as in the steps (5) to (12) of Example 4, a substrate having a conductor circuit 158 formed on the outermost layer was produced (see FIG. 9A).

(7) Next, a solder resist composition was obtained in the same manner as in Example 1. Furthermore, a conductor circuit 1 is provided on the outermost layer.
The above-mentioned solder resist composition is applied to a thickness of 20 μm on the IC-embedded substrate 30 on which the substrate 58 is formed.
After drying for 30 minutes at 70 ° C for 30 minutes,
A 5 mm-thick photomask on which the pattern of the solder resist resist opening is drawn is applied to the solder resist layer 70.
And exposed to ultraviolet light of 1000 mJ / cm ² ,
Developed with a DMTG solution, and an opening 7 having a diameter of 200 μm
1 was formed (see FIG. 9B).

(8) Next, the solder resist layer 70 is formed
The substrate thus formed is coated with nickel chloride (2.3 × 10^-1mol /
l), sodium hypophosphite (2.8 × 10^-1mol /
l), sodium citrate (1.6 × 10^-1mol /
l) containing 2 to the electroless nickel plating solution of pH = 4.5
Immerse for 0 minutes, and put nickel 5mm thick in opening 71
A plating layer 72 was formed. In addition, the substrate is
Potassium gold (7.6 × 10 ^-3mol / l), ammonium chloride
Num (1.9 × 10^-1mol / l), sodium citrate
Um (1.2 × 10^-1mol / l), sodium hypophosphite
Um (1.7 × 10 ^-1mol / l)
Immersed in the solution at 80 ° C for 7.5 minutes,
A gold plating layer 74 having a thickness of 0.03 μm is formed on the metal layer 72.
As a result, a solder pad 75 is formed on the conductor circuit 158.
(See FIG. 9C).

(9) After that, after solder paste is printed on the opening 71 of the solder resist layer 70, the conductive pins 176 are placed on the solder pads via the solder paste and reflow at 200 ° C. Thus, a multilayer printed wiring board 110 incorporating the IC chip 20 and having a PGA (Pin Grid Array) was obtained (see FIG. 11).

With respect to the multilayer printed wiring board manufactured as described above, the pad surface of the IC chip was observed, and
Whether or not peeling has occurred between the conductor circuit and the interlayer resin insulation layer before and after the reliability test, whether or not peeling has occurred between the pad of the IC chip and the via hole, and short-circuit and disconnection during the continuity test The presence or absence of occurrence was evaluated using the following evaluation method.

(1) Observation of Pad Surface The multilayer printed wiring board was cut with a blade, and the cut section was observed with a microscope. Here, the multilayer printed wiring board was cut so as to pass through the pad portion of the IC chip.

(2) Reliability Test A cycle of maintaining the obtained multilayer printed wiring board in an atmosphere of -65 ° C for 3 minutes and then in an atmosphere of 130 ° C for 3 minutes was repeated 1,000 times.

(3) Existence of Peeling Between Conductor Circuit and Interlayer Resin Insulating Layer The multilayer printed wiring board was cut with a cutter in the same manner as in the above (1), and the cut cross section was observed with a microscope. (4) Presence or absence of peeling between the pad of the IC chip and the via hole The multilayer printed wiring board was cut with a cutter in the same manner as in (1) above, and the cut cross section was observed with a microscope.

(4) Presence or Absence of Short-Circuit or Disconnection A continuity test was performed on the obtained multilayer printed wiring board with a built-in IC chip, and the continuity was evaluated from the result displayed on the monitor.

As a result of the above evaluation, the multilayer printed wiring boards of Examples 1 to 3 did not have a transition layer, so that there was a position shift between the via hole and the pad of the IC chip, Although the resin residue was generated on the surface but was found in a part, the via hole and the pad were connected, and were not so large as to affect the performance of the product. No peeling occurred between the conductor circuit and the interlayer resin insulating layer, or between the pad and the via hole, and no short circuit or disconnection occurred in the conduction test.

Further, in the multilayer printed wiring boards of Examples 4 to 6, since the transition layer was formed on the pad, displacement between the via hole and the pad of the IC chip and resin residue on the pad surface occurred. I didn't. In addition, no peeling occurred between the conductor circuit and the interlayer resin insulating layer or between the pad and the via hole, and no short circuit or disconnection occurred in the conduction test.

[0143]

As described above, since the multilayer printed wiring board of the present invention has the above-described structure, it is necessary to use a lead component or a sealing resin when connecting the electronic component to the printed wiring board. In addition, since the interlayer resin insulating layer is made of a photosensitive cardo type polymer, it is excellent in shape retention and has a via hole opening of a desired shape, and is excellent in electrical connectivity and reliability.

In the method of manufacturing a multilayer printed wiring board according to the present invention, since the interlayer resin insulating layer is formed using a photosensitive cardo type polymer, the crosslinking density is high at a relatively low curing temperature, and the shape retention and the like are improved. An interlayer resin insulating layer having excellent heat resistance can be formed, and the substrate does not soften or melt when the interlayer resin insulating layer is formed. Also,
The photosensitive cardo type polymer used in the production method of the present invention is
Since the opening property by the exposure / development processing is excellent, there is no resin residue in the via hole opening, and a via hole having a desired shape can be formed.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view schematically showing one example of a multilayer printed wiring board of the present invention.

FIGS. 2A to 2D are cross-sectional views schematically showing a manufacturing process of the multilayer printed wiring board according to the present invention.

FIGS. 3A to 3C are cross-sectional views schematically showing a manufacturing process of the multilayer printed wiring board of the present invention.

FIGS. 4A to 4C are cross-sectional views schematically showing a manufacturing process of the multilayer printed wiring board according to the present invention.

FIGS. 5A and 5B are cross-sectional views schematically showing a manufacturing process of the multilayer printed wiring board of the present invention.

FIGS. 6A to 6C are cross-sectional views schematically showing a process for manufacturing a multilayer printed wiring board according to the present invention.

FIGS. 7A to 7C are cross-sectional views schematically showing a manufacturing process of the multilayer printed wiring board of the present invention.

FIGS. 8A to 8C are cross-sectional views schematically showing a manufacturing process of the multilayer printed wiring board of the present invention.

FIGS. 9A to 9C are cross-sectional views schematically showing a manufacturing process of the multilayer printed wiring board of the present invention.

FIG. 10 is a cross-sectional view schematically showing another example of the multilayer printed wiring board of the present invention.

FIG. 11 is a cross-sectional view schematically showing still another example of the multilayer printed wiring board of the present invention.

FIGS. 12A to 12D are cross-sectional views schematically showing a manufacturing process of the multilayer printed wiring board of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 20 IC chip 24 pad 30 IC built-in board 38 Transition layer 50, 150 Interlayer resin insulation layer 58, 158 Conductor circuit 60, 160 Via hole 70 Solder resist layer 76 Solder bump

Claims (9)

[Claims] 1. An interlayer resin insulating layer and a conductive circuit are sequentially formed on a substrate on which an electronic component is built or housed.
The electronic component and the conductor circuit, and a multilayer printed wiring board in which upper and lower conductor circuits are connected via via holes, wherein the interlayer resin insulating layer is made of a photosensitive cardo type polymer. Multilayer printed wiring board. 2. The multilayer printed wiring board according to claim 1, wherein the photosensitive cardo type polymer is a photosensitive cardo type polyimide resin. 3. The multilayer printed wiring board according to claim 1, wherein the photosensitive cardo type polymer has a glass transition temperature of 250 to 300 ° C. 4. The electronic component according to claim 1, wherein a transition layer is formed on a pad portion of the electronic component, and the electronic component and the conductive circuit are connected via the transition layer and via holes. 2. The multilayer printed wiring board according to item 1. 5. An interlayer resin insulating layer and a conductive circuit are sequentially formed on a substrate on which an electronic component is built or housed,
A method for manufacturing a multilayer printed wiring board in which the electronic component and the conductor circuit and the upper and lower conductor circuits are connected via via holes, including at least the following steps (1) to (4). Of manufacturing a multilayer printed wiring board. (1) a board on which the electronic component is built or housed;
Or a step of applying a solution of a photosensitive cardo type polymer to a substrate on which at least one of the interlayer resin insulating layer and the conductor circuit is formed on the substrate; and (2) semi-curing of the photosensitive cardo type polymer Forming a layer; (3)
After placing a photo-etching mask on the semi-cured layer of the photosensitive cardo type polymer, forming a via hole opening by subjecting the semi-cured layer of the photosensitive cardo type polymer to exposure and development. (4) a step of forming the interlayer resin insulation layer by fully curing the semi-cured layer of the photosensitive cardo type polymer in which the via hole opening is formed. 6. The method according to claim 5, wherein the photosensitive cardo type polymer is a photosensitive cardo type polyimide resin. 7. The method for producing a multilayer printed wiring board according to claim 5, wherein the fully cured photosensitive cardo type polymer layer has a glass transition temperature of 250 to 300 ° C. 8. The following steps (a) to (e) are performed before applying the solution of the photosensitive cardo type polymer,
The method for manufacturing a multilayer printed wiring board according to any one of claims 5 to 7, wherein a transition layer is formed on a pad portion of the electronic component. (A) On a substrate on which electronic components are built or housed,
Forming a metal film, (b) attaching a photosensitive dry film on the metal film, and (c) forming a plating resist by subjecting the photosensitive dry film to exposure and development. And (d) forming a plating layer in the plating resist non-formed portion; and (e) forming the transition layer by removing the plating resist and a metal film present under the plating resist. Process. 9. Before applying the solution of the photosensitive cardo type polymer, the following steps (a) to (e) are carried out,
The method for manufacturing a multilayer printed wiring board according to any one of claims 5 to 7, wherein a transition layer is formed on a pad portion of the electronic component. (A) On a substrate on which electronic components are built or housed,
Forming a metal film; (b) forming a plating layer on the metal film; (c) attaching a photosensitive dry film on the plating layer; A step of forming an etching resist by subjecting the dry film to exposure and development; and (e) forming the transition layer by removing the metal film and the plating layer under the portion where the etching resist is not formed by etching. Process.