JP2002083894A - Semiconductor chip and semiconductor device using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor chip of integral rewiring layer which is hard to cause malfunction due to noise and deterioration of transmission characteristic, and also to provide a semiconductor device with good transmission characteristic. SOLUTION: A rewiring layer 3 is formed on a circuit forming plane 1a via an insulating layer 2, and an antenna coil 4 is formed by rewiring layer 3. Antenna coil 4 is formed near an analog circuit 21, not in or to circuit 21 itself, which is formed on circuit forming plane 1a. Analog circuit 21 can be an integration of all analog circuits to be formed on a semiconductor chip 1A, or one of a power circuit, an operational amplifier, a comparative amplifier, an RF receiver, an RF sender and an RF synthesizer, and an analog circuit that is easy to be affected by noise as a voltage rising circuit or an amplifying circuit constituting a part of a memory part, or it can be a coil constituting a part of the analog circuits to be formed in semiconductor chip 1A.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip having a rewiring layer integrally formed on a circuit forming surface via an insulating layer, and a semiconductor device having the semiconductor chip mounted thereon.
In particular, it relates to the arrangement of the redistribution layers.

[0002]

2. Description of the Related Art A semiconductor device, such as a card type, a tag type or a coin type, on which a semiconductor chip is mounted has an abundant amount of information and a high security performance. Spread is spreading. Among them,
A non-contact communication type semiconductor device developed in recent years is provided with no external terminal on a base and wirelessly transmits and receives power from a reader / writer and transmits / receives signals to / from the reader / writer. It is characterized by the fact that it does not essentially damage the external terminals as described above, is easy to handle such as storage, withstands long-term use, and is more resistant to data tampering and has even better security performance. It is expected to spread to a wider field in the future.

Conventionally, as a semiconductor chip mounted on this kind of non-contact type semiconductor device, a non-contact communication for receiving power from an external device and transmitting and receiving signals to and from the external device in a non-contact manner. In recent years, as shown in FIG. 16 and FIG. 17, a rewiring layer 3 is formed on a circuit formation surface via an insulating layer 2, and the rewiring layer 3 is formed. A coil-on-chip type semiconductor chip 1 in which an antenna coil 4 is formed integrally with the semiconductor chip 1 has been proposed.

[0004] Coil-on-chip type semiconductor chip 1
With the use of an antenna, there is no need to separately prepare an antenna coil, and the connection between the antenna coil and the semiconductor chip and the protection of the connection are not required. Cost can be reduced.

In recent years, as shown in FIGS. 18 and 19, a plurality of input / output terminals (non-contact type or contact type) are mounted along the outer periphery of a semiconductor chip mounted on a semiconductor device, as shown in FIGS. A rewiring layer 3 is formed on the circuit forming surface of the semiconductor chip on which the pad (pad) 5 is formed via an insulating layer 2, and one end of the rewiring layer 3 is provided with the input / output terminal 5.
, A bump 7 is formed on the other end, and a chip scale package (hereinafter abbreviated as “CSP”) type semiconductor chip 8 on which bump setting wiring 6 laid out on the entire surface of the semiconductor chip is formed. Proposed.

When the CSP type semiconductor chip 8 is used, the bumps 7 can be freely laid out on the entire surface of the semiconductor chip 8, so that the bumps 7 are formed on the input / output terminals 5 formed along the outer periphery. Compared with the case, the arrangement pitch and the bump size of the bumps 7 can be increased, so that the number of input / output terminals 5 can be increased and the flip chip mounting of the semiconductor chip can be facilitated.

[0007]

On the circuit formation surface of a semiconductor chip applied to a semiconductor device, as shown in FIGS. 16 and 18, a power supply circuit 11 and an operational amplifier (op-amp) 12 are compared. Amplifier (comparator) 1
3, the RF receiving unit 14, the RF transmitting unit 15, the RF synthesizer unit 16, the logic unit 17, the memory unit 18 and the like are formed in blocks, and when higher security performance is required, May have a built-in microprocessor. The power supply circuit 11, the operational amplifier 1
2, comparison amplifier 13, RF receiver 14, RF transmitter 15
Most of the RF synthesizer section 16 is composed of an analog circuit, and the memory section 18 is also an EEP as a memory element.
When a ROM or the like is used, a part of the circuit includes an analog circuit such as a voltage booster circuit or an amplifier circuit. On the other hand, the logic unit 17 is mostly constituted by a digital circuit. It should be noted that some conventionally known semiconductor chips for mounting a semiconductor device include a coil part in a part of the analog circuit.

In the coil-on-chip type semiconductor chip 1 and the CSP type semiconductor chip 8 in which the rewiring layer 3 is integrally formed, the semiconductor chips 1 and 8 are interposed via the insulating layer 2 having a relatively high dielectric constant. Since the circuit formation surface and the redistribution layer 3 are arranged close to each other, a parasitic capacitance C is formed between the circuit formed on the circuit formation surface and the redistribution layer 3 as schematically shown in FIG. Is done.

However, in the conventional coil-on-chip type semiconductor chip 1 and the CSP type semiconductor chip 8, there is no consideration given to the adverse effect when the parasitic capacitance C is generated in the analog circuit forming portion. Without
As shown in FIGS. 16 to 19, the antenna coil 4 or the bump setting wiring 5 is also formed at a position facing the analog circuit forming portion.

Therefore, the conventional coil-on-chip type semiconductor chip 1 and the CSP type semiconductor chip 8
Indicates the analog circuit formed on the circuit forming surface and the redistribution layer 3
A parasitic capacitance C is formed between them, and the electromotive force (AC) generated in the redistribution layer 3 and the parasitic capacitance C combine to generate electrostatic induction noise. As a result, crosstalk noise, ringing (LC resonance shift), power supply noise, and the like are generated, and thus there is a problem that malfunctions and deterioration of communication characteristics are likely to occur.

In the conventional coil-on-chip type semiconductor chip 1 and the CSP type semiconductor chip 8, the circuit formation surface and the redistribution layer 3 are arranged to face each other with the insulating layer 2 interposed therebetween. Electromagnetic induction noise is also likely to be generated in each circuit formed on the surface, and erroneous operation and deterioration of communication characteristics due to this are likely to occur.

Noise such as crosstalk noise, ringing, and power supply noise caused by the electrostatic induction noise or the electromagnetic induction noise is reduced by the power supply circuit 11, the operational amplifier 12,
Analog circuits such as the comparison amplifier 13, the RF reception unit 14, the RF transmission unit 15, and the RF synthesizer unit 16 are provided, particularly, the operational amplifier 12 and the comparison amplifier 13 that handle minute voltage waveforms, and the memory unit 18 that handles minute signals. This greatly affects the voltage boosting circuit and the amplifying circuit, the coil, and the like. In addition, since these noises have a greater adverse effect on a circuit having a higher voltage waveform or signal frequency, it is necessary to suppress the occurrence of the noise particularly in a high-frequency-compatible semiconductor chip applied to, for example, a mobile phone. is there.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to provide a semiconductor chip integrated with a redistribution layer which is unlikely to cause malfunction or deterioration of communication characteristics due to noise. And a semiconductor device having good communication characteristics.

[0014]

According to the present invention, in order to solve the above-mentioned problems, the present invention relates to a semiconductor chip in which a rewiring layer is integrally formed on a circuit forming surface via an insulating layer. , The whole or a part of the analog circuit formed on the circuit forming surface and the rewiring layer are arranged so as not to overlap with each other via the insulating layer.

As described above, when the analog circuit and the rewiring layer formed on the circuit formation surface of the semiconductor chip are arranged so as not to overlap with each other via the insulating layer, the parasitic capacitance is formed between the analog circuit and the rewiring layer. Is not formed, it is possible to prevent the occurrence of capacitance noise acting on the analog circuit. Further, since the analog circuit and the redistribution layer are not arranged to face each other, it is possible to prevent the generation of electromagnetic induction noise acting on the analog circuit. Therefore, the occurrence of crosstalk noise, ringing, power supply noise, and the like due to the electrostatic induction noise or the electromagnetic induction noise is prevented, and malfunction and communication caused by the noise are prevented even in the high-frequency compatible rewiring layer integrated semiconductor chip. Deterioration of characteristics can be eliminated. In addition, even if the rewiring layers are not arranged so as not to overlap for all the analog circuits formed on the circuit forming surface, if the rewiring layers are arranged so as not to overlap for analog circuits which are particularly susceptible to noise, ,
Practically, there is no problem of malfunction or deterioration of communication characteristics due to noise. Also, since digital circuits are less susceptible to noise than analog circuits, even if a redistribution layer is superimposed on a digital circuit formed on the circuit formation surface via an insulating layer, a semiconductor with an integrated redistribution layer There is no malfunction of the chip or deterioration of the communication characteristics.

The present invention relates to a semiconductor chip,
A power supply circuit, an operational amplifier, a comparison amplifier, an RF receiving unit, an RF transmitting unit, and a power supply circuit formed on the circuit forming surface in a semiconductor chip obtained by integrally forming a redistribution layer on a circuit forming surface via an insulating layer. At least one of the RF synthesizer units and the rewiring layer are arranged so as not to overlap with each other via the insulating layer.

As described above, the power supply circuit, operational amplifier, comparison amplifier, RF receiver, RF
Most of the transmitting unit and the RF synthesizer unit include analog circuits that are easily affected by noise. Therefore, if these circuit blocks and the rewiring layer are arranged so as not to overlap with each other via the insulating layer, crosstalk noise, ringing, and power supply caused by electrostatic induction noise or electromagnetic induction noise can be obtained for each circuit block. Generation of noise and the like can be prevented, and malfunctions and deterioration of communication characteristics due to the noise can be eliminated.

The present invention relates to a semiconductor chip,
In a semiconductor chip in which a rewiring layer is integrally formed on a circuit forming surface via an insulating layer, a coil formed on the circuit forming surface does not overlap with the rewiring layer via the insulating layer. It was configured to be arranged like this.

As described above, in a semiconductor chip having a coil formed on a circuit forming surface, if the coil and the rewiring layer are arranged so as not to overlap with each other via an insulating layer, the coil may have an electrostatic induction noise or an electromagnetic induction noise. Since noise is less likely to act and ringing or the like can be prevented, malfunctions and deterioration of communication characteristics due to noise can be eliminated.

The present invention relates to a semiconductor chip,
In addition, with the rewiring layer described in the first to third problem solving means, a non-contact communication antenna coil having both ends connected to input / output terminals formed on the circuit formation surface is formed. did.

As described above, when the antenna coil for non-contact communication is formed with the rewiring layer, a coil-on-chip having excellent noise resistance can be obtained. A semiconductor device can be manufactured.

The present invention relates to a semiconductor chip,
A bump setting wiring having one end connected to an input / output terminal formed on the circuit forming surface and the other end formed with a bump, using the rewiring layer described in the first to third problem solving means. It was configured to be formed.

As described above, when the bump setting wiring is formed with the rewiring layer, a CSP type semiconductor chip having excellent noise resistance can be obtained. Therefore, a semiconductor device having multiple terminals and having excellent noise resistance can be obtained. Obtainable.

The present invention relates to a semiconductor chip,
The circuit formed on the circuit forming surface according to any one of the first to fifth problem solving means is a wireless communication circuit formed by CMOS technology.

The applicant of the present application has experimentally confirmed that a wireless chip manufactured by CMOS technology has a large variation in individual transistor characteristics as compared with a transistor manufactured by Si bipolar technology, and has a dynamic range due to the influence of stray capacitance and the like. Since the characteristics easily deteriorate, the fact that the formation of a redistribution layer on an analog circuit has a great influence is known. According to the simulation, the effect of rewiring on the analog circuit on wireless communication characteristics is
It was confirmed that the value was 2 to 8 times that of the case where the Si bipolar technology was used. Therefore, by arranging the redistribution layers so that the redistribution layers are not formed on the analog circuit, the semiconductor chip having the wireless communication circuit formed on the circuit formation surface by the CMOS technology is particularly susceptible to the influence of the redistribution layer. It is possible to prevent communication characteristics of such a semiconductor chip from deteriorating.

The present invention relates to a semiconductor chip,
The circuit formed on the circuit forming surface according to any one of the first to sixth means for solving the above problems may have an 800 MHz frequency between the circuit and an external device.
The wireless communication circuit transmits, receives, or transmits / receives signals of the above frequencies.

The applicant of the present application has shown by experiments that the effect of rewiring on an analog circuit on wireless communication characteristics depends on the frequency for wireless communication, and that when the frequency exceeds 800 MHz, the communication characteristics rapidly deteriorate. I know the fact.
This is because the current flowing in the rewiring flows near the center of the rewiring when transmitting and receiving a low frequency of about several MHz, whereas the skin effect that flows through the surface of the rewiring at a high frequency of 800 MHz or more. Probably because of. The influence of the skin effect on the circuit causes an increase in an error rate due to noise, a sharp decrease in a communication distance, and a communication failure. Therefore, for a semiconductor chip on which a wireless communication circuit for transmitting, receiving, or transmitting and receiving a signal having a frequency of 800 MHz or more is formed, by arranging the rewiring layer so that the rewiring layer is not formed on the analog circuit,
It is possible to prevent the communication characteristics of this type of semiconductor chip, which is particularly susceptible to the influence of the rewiring layer, from deteriorating.

On the other hand, in order to solve the above-mentioned problems, the present invention relates to a semiconductor device in which a semiconductor chip is mounted on a base having a predetermined size and a predetermined shape. A rewiring layer is integrally formed on the circuit forming surface via an insulating layer, and all or a part of the analog circuit formed on the circuit forming surface overlaps with the rewiring layer via the insulating layer. In this configuration, semiconductor chips arranged so as not to be mounted are mounted.

As described above, when a semiconductor chip in which an analog circuit formed on a circuit forming surface and a rewiring layer are arranged so as not to overlap with each other via an insulating layer is mounted, electrostatic induction is applied to the analog circuit of the semiconductor chip. Since malfunction or deterioration of communication characteristics due to noise or electromagnetic induction noise does not occur, a semiconductor device with good communication characteristics can be obtained.

The present invention relates to a semiconductor device.
In a semiconductor device in which a semiconductor chip is mounted on a base having a predetermined size and a predetermined shape, a redistribution layer is integrally formed on a circuit forming surface via an insulating layer as the semiconductor chip,
And a power supply circuit formed on the circuit forming surface, an operational amplifier, a comparison amplifier, an RF receiving unit, an RF transmitting unit, and an RF synthesizer unit, and the rewiring layer via the insulating layer. The semiconductor chips are arranged so as not to overlap each other.

As described above, at least one of the power supply circuit, the operational amplifier, the comparison amplifier, the RF receiver, the RF transmitter, and the RF synthesizer formed on the circuit formation surface.
When semiconductor chips are arranged so that they do not overlap with each other via the insulating layer, malfunctions caused by electrostatic induction noise and electromagnetic induction noise can occur in those circuits that are most susceptible to the adverse effects of noise. Therefore, a semiconductor device having good communication characteristics can be obtained.

The present invention relates to a semiconductor device.
In a semiconductor device in which a semiconductor chip is mounted on a base having a predetermined size and a predetermined shape, a redistribution layer is integrally formed on a circuit forming surface via an insulating layer as the semiconductor chip,
In addition, a configuration is adopted in which a semiconductor chip arranged such that the coil formed on the circuit formation surface and the rewiring layer do not overlap via the insulating layer is mounted.

As described above, when a semiconductor chip in which the coil formed on the circuit forming surface and the rewiring layer are arranged so as not to overlap with each other via the insulating layer is mounted, the coil is easily affected by the adverse influence of noise. Since the electric induction noise and the electromagnetic induction noise do not act, a semiconductor device having good communication characteristics can be obtained.

[0034]

DESCRIPTION OF THE PREFERRED EMBODIMENTS <First Example of Semiconductor Chip> A first example of a semiconductor chip according to the present invention will be described with reference to FIGS. FIG. 1 is a plan view of a semiconductor chip 1A according to the first embodiment, and FIG. 2 is a sectional view taken along line AA of FIG.

The semiconductor chip 1A of this embodiment is a coil-on-chip type semiconductor chip. As shown in FIGS. 1 and 2, a rewiring layer 3 is formed on a circuit forming surface 1a via an insulating layer 2. The antenna coil 4 is formed integrally with the rewiring layer 3. In the semiconductor chip 1A of this example, a rectangular spiral antenna coil 4 is formed in a peripheral portion thereof avoiding the analog circuit 21 formed in a central portion of the circuit forming surface 1a.

The analog circuit 21 includes the semiconductor chip 1
All analog circuits to be formed in A may be integrated. For example, the power supply circuit 11, the operational amplifier 12, the comparison amplifier 13, the RF receiving unit 14, the RF transmitting unit 15, and the RF synthesizer unit 16 And one of analog circuits that are particularly susceptible to noise, such as a voltage booster circuit and an amplifier circuit that constitute a part of the memory unit 18.
May be one. Furthermore, a coil provided in a part of an analog circuit formed on the semiconductor chip 1A may be used.

The semiconductor chip 1A of this embodiment is formed on the circuit formation surface 1a of the base semiconductor chip (more practically, a completed wafer before being cut into individual semiconductor chips) via the insulating layer 2. It is manufactured by forming the wiring layer 3. Any known semiconductor chip can be used as a semiconductor chip on which the semiconductor chip 1A of this example is based. However, in order to reduce the thickness of a non-contact type semiconductor device as a final product, no circuit is formed. It is particularly preferable to use a bare chip whose surface 1b is thinned by chemical polishing or mechanical polishing or a combination of these means. The thickness is preferably not more than 300 μm, and particularly preferably about 50 μm to 150 μm for those applied to thin cards. In addition, a wireless communication circuit formed on a circuit formation surface by CMOS technology, or a wireless communication circuit for transmitting, receiving, or transmitting and receiving a signal having a frequency of 800 MHz or more with an external device is formed on the circuit formation surface. Can also be used.

In the example shown in FIG. 1, the antenna coil 4 is wound a plurality of turns. However, the number of turns of the antenna coil 4 is not limited to this.
Any number of turns equal to or greater than the number of turns can be used. Further, the planar shape of the antenna coil 4 is not limited to the examples shown in FIGS. 1 and 2. For example, a corner may be chamfered to have a shape in which the communication characteristics are hardly deteriorated due to the shape effect. . In addition, the insulating layer 2 and the redistribution layer 3 may be stacked in multiple stages to increase the number of turns of the antenna coil 4.

The semiconductor chip 1A of this embodiment has a circuit forming surface 1
The antenna coil 4 is formed so as to avoid the analog circuit 21 formed in the center portion of a, and the analog circuit 21 and the antenna coil 4 are arranged so as not to overlap each other. No parasitic capacitance is formed on the analog circuit 21, and the occurrence of capacitance noise acting on the analog circuit 21 can be prevented. Further, since the analog circuit 21 and the antenna coil 4 are not arranged to face each other, it is possible to prevent the generation of electromagnetic induction noise acting on the analog circuit 21. Therefore, the occurrence of crosstalk noise, ringing, power supply noise, and the like due to the electrostatic induction noise or the electromagnetic induction noise is prevented. Can be eliminated.

In particular, when a semiconductor chip having a wireless communication circuit formed on a circuit forming surface by CMOS technology is used as a semiconductor chip on which the semiconductor chip 1A is based, the rewiring layer 3
It is possible to prevent the communication characteristics of this type of semiconductor chip from being deteriorated particularly easily affected by the (antenna coil 4). When a semiconductor chip on which a wireless communication circuit for transmitting, receiving, or transmitting or receiving a signal having a frequency of 800 MHz or more to or from an external device is formed on a circuit forming surface is used as a semiconductor chip on which the semiconductor chip 1A is based. In addition, it is possible to prevent deterioration of communication characteristics of a semiconductor chip of this kind which is particularly susceptible to the influence of the rewiring layer 3 (antenna coil 4).

<Second Example of Semiconductor Chip> A second example of the semiconductor chip according to the present invention will be described with reference to FIG. FIG.
FIG. 9 is a plan view of a semiconductor chip 1B according to a second embodiment.

The semiconductor chip 1B of this embodiment is also a coil-on-chip type semiconductor chip. As shown in FIG. 3, a rewiring layer 3 is formed on a circuit forming surface 1a via an insulating layer 2, and The antenna coil 4 is integrally formed with the rewiring layer 3. Then, the semiconductor chip 1 of the present example
In B, an irregular spiral antenna coil 4 is formed in a peripheral portion thereof avoiding the analog circuit 21 formed in one corner of the circuit forming surface 1a. Other features are the same as those of the semiconductor chip 1A according to the first embodiment, and a description thereof will be omitted.

The semiconductor chip 1B of the present embodiment also has the circuit forming surface 1
Since the antenna coil 4 is formed avoiding the analog circuit 21 formed at one corner of a, and the analog circuit 21 and the antenna coil 4 are arranged so as not to overlap with each other.
The effect of the noise acting on the analog circuit 21 can be eliminated, and the semiconductor chip 1A according to the first embodiment can be eliminated.
The same effect as described above can be obtained.

<Third Example of Semiconductor Chip> A third example of a semiconductor chip according to the present invention will be described with reference to FIGS. FIG. 4 is a plan view of a semiconductor chip 1C according to the third embodiment, and FIG. 5 is a sectional view taken along line BB of FIG.

The semiconductor chip 1C of this embodiment is a CSP type semiconductor chip, as shown in FIGS.
A rewiring layer 3 is formed on the circuit forming surface 1a via the insulating layer 2, and one end of the bump is connected to the input / output terminal 5 and the other end is laid out on the entire surface of the semiconductor chip 1C with the rewiring layer 3 A setting wire 6 is formed, and a bump 7 is formed at the other end of the bump setting wire 6. Then, in the semiconductor chip 1C of this example, the circuit forming surface 1
The bump setting wiring 6 is routed around the analog circuit 21 formed on a part of the analog circuit 21a, and the bumps 7 are formed only on the side of the analog circuit 21 formation part.
Are arranged. Other features are the same as those of the semiconductor chip 1A according to the first embodiment, and a description thereof will be omitted.

The semiconductor chip 1C of this embodiment also has the circuit forming surface 1
a, the bump setting wiring 6 and the bump 7 are formed so as to avoid the analog circuit 21 formed in a part of the analog circuit 21.
And the bump setting wiring 6 and the bump 7 are arranged so as not to overlap with each other, so that the influence of noise acting on the analog circuit 21 can be eliminated.
The same effects as those of the semiconductor chip 1A according to the embodiment can be obtained.

<Fourth Example of Semiconductor Chip> A fourth example of a semiconductor chip according to the present invention will be described with reference to FIG. FIG.
Is a plan view of a semiconductor chip 1D according to a fourth embodiment.

The semiconductor chip 1D of this embodiment is also a CSP type semiconductor chip, and as shown in FIG.
, A rewiring layer 3 is formed on the circuit forming surface 1a, and one end of the rewiring layer 3 is connected to the input / output terminal 5 and the other end is laid out on the entire surface of the semiconductor chip 1D with the rewiring layer 3. 6 are formed, and a bump 7 is formed at the other end of the bump setting wiring 6. In the semiconductor chip 1D of this example, the bump setting wiring 6 is routed around the analog circuit 21 formed on a part of the circuit forming surface 1a and around the analog circuit 21. The bumps 7 are arranged above and on the side. Other features are the same as those of the semiconductor chip 1C according to the third embodiment, and the description is omitted.

The semiconductor chip 1C of the present embodiment also has the circuit forming surface 1
a, the bump setting wiring 6 and the bump 7 are formed so as to avoid the analog circuit 21 formed in a part of the analog circuit 21.
And the bump setting wiring 6 and the bump 7 are arranged so as not to overlap with each other, so that the same effect as that of the semiconductor chip 1C according to the third embodiment can be obtained.

<Fifth Example of Semiconductor Chip> A fifth example of a semiconductor chip according to the present invention will be described with reference to FIG. FIG.
FIG. 14 is a plan view of a semiconductor chip 1E according to a fifth embodiment.

The semiconductor chip 1E of this example is also a CSP type semiconductor chip, and as shown in FIG.
, A rewiring layer 3 is formed on the circuit forming surface 1a, and with the rewiring layer 3, one end is connected to the input / output terminal 5 and the other end is laid out over the entire surface of the semiconductor chip 1E. 6 are formed, and a bump 7 is formed at the other end of the bump setting wiring 6. In the semiconductor chip 1E of the present example, the bump setting wiring 6 is routed around the analog circuit 21 formed at two places on the circuit forming surface 1a, around the analog circuit 21, and before and after the formation part of the analog circuit 21. The bumps 7 are arranged on the left and right. Other features are the same as those of the semiconductor chip 1C according to the third embodiment, and the description is omitted.

The semiconductor chip 1E of this embodiment also has the circuit forming surface 1
a, the bump setting wiring 6 and the bump 7 are formed so as to avoid the analog circuit 21 formed in a part of the analog circuit 21.
And the bump setting wiring 6 and the bump 7 are arranged so as not to overlap with each other, so that the same effect as that of the semiconductor chip 1C according to the third embodiment can be obtained.

<First Example of Method of Forming Rewiring Layer> Hereinafter, a first example of a method of forming the rewiring layer 3 constituting the antenna coil 4 or the bump setting wiring 6 will be described with reference to FIGS. Will be explained. FIG. 8 is a plan view of a so-called completed wafer completed through a predetermined process, and FIG.
FIG. 10 is a process chart showing a first example of a method of forming a redistribution layer 3.
FIG. 4 is a plan view of a completed wafer on which is formed.

As shown in FIG. 8, the completed wafer 31 has
A large number of circuits 32 for semiconductor chips are formed at equal intervals on the inner peripheral portion except the outermost peripheral portion, and a required surface protective film 33 (see FIG. 9) is formed on the circuit forming surface side. I have.

In the first example of the method of forming the redistribution layer shown in FIG. 9, first, as shown in FIG. 9A, aluminum or aluminum is formed on the surface protection film 33 formed on the circuit formation surface of the completed wafer 31. Using an aluminum alloy, copper, or a copper alloy, a metal sputtered layer or a metal deposited layer 34 is uniformly formed. Next, as shown in FIG. 9B, a photoresist layer 35 is uniformly formed on the metal sputtered layer or the metal deposited layer 34, and the antenna layer 4 or the bump setting wiring 6 is formed on the formed photoresist layer 35. Is covered, and the photoresist layer 35 is exposed by irradiating light 37 of a predetermined wavelength from outside the mask 36. Photoresist layer 35 which has been subsequently exposed
9C, the exposed portion of the photoresist layer 35 is removed to expose a portion of the metal sputtered layer or the metal deposited layer 34 corresponding to the exposed pattern, as shown in FIG. 9C. As shown in FIG. 10, the exposed pattern of the metal sputtering layer or the metal deposition layer 34 includes a ring-shaped electrode portion 37 and the antenna coil 4 or the bump setting wiring 6 formed in a portion other than the analog circuit 21. And a lead portion 38 for connecting the electrode portion 37 to each antenna coil 4 or each bump setting wire 6. Next, using the electrode portion 37 as one electrode, the exposed portion of the metal sputtering layer or the metal deposition layer 34 is subjected to electroplating or precision electroforming, and as shown in FIG. The metal plating layer 39 is laminated on the exposed portion of the. Next, the photoresist layer 35 attached to the surface of the completed wafer 31 is removed by ashing or the like,
As shown in FIG. 9E, a metal plating layer 39 having an electrode portion 37, an antenna coil 4 or a bump setting wire 6, and a lead portion 38 was formed on a uniform metal sputtering layer or metal deposition layer. A completed wafer 31 is obtained. Next, the metal sputter layer or the metal vapor deposition layer 34 exposed from the metal plating layer 39 is selectively etched, and as shown in FIG. Remove. As a result, a completed wafer 31 on which the metal sputtering layer or the metal deposition layer 34 and the metal plating layer 39 are formed is obtained. Finally, the completed wafer 31 is scribed to obtain the required semiconductor chip IC elements 1A to 1E shown in FIGS.

In this embodiment, the metal plating layer 39 is used.
Although the electroplating method or the precision electroforming method is used as the forming means, the metal plating layer 39 may be formed by using an electroless plating method instead of such a configuration. In this case, since no electrode is required for forming the metal plating layer 39, the electrode portion 37
And the formation of the lead portion 38 become unnecessary.

Electroless plating is also called chemical plating,
The base metal is immersed in a metal salt solution of the plating metal to deposit metal ions on the surface of the base metal, and the feature is that a relatively simple facility can be used to obtain a plating layer having a strong adhesion and a uniform and sufficient thickness. . The metal salt serves as a supply source of metal ions to be plated. When plating copper, a solution such as copper sulfate, cupric chloride, or copper nitrate is used as a plating solution. Metal ions such as copper are deposited only on the base metal sputtered layer or metal deposited layer 34,
It does not deposit on the insulating surface protection layer 33. The base material is
It is necessary to have a small ionization tendency with respect to plating metal ions and to have a catalytic action on the deposition of plating metal ions. For this reason, when copper is plated on the metal sputtered layer or the metal deposited layer 6 made of aluminum, nickel is formed to a thickness of several μm or less on the surface of the aluminum layer, and is immersed in a zinc nitrate solution for several seconds. It is preferable to carry out a pretreatment for substituting.

On the other hand, in the electroplating method and the precision electroforming method, a completed wafer 31 on which a metal sputtered layer or a metal deposited layer 34 is formed and an electrode made of a plated metal are immersed in a plating bath containing ions of the plated metal. A voltage is applied using the metal sputtered layer or the metallized layer 34 formed on the completed wafer 31 as a cathode and the electrode immersed in the plating bath as an anode to apply metal ions in the plating bath to the metal sputtered layer or the metallized layer 3.
This is a method of precipitating on the surface of No. 4. Also in the electroplating method and the precision electroforming method, when plating copper, a solution of copper sulfate, cupric chloride, copper nitrate or the like is used as a plating solution.

In the method of forming the rewiring layer 3 of the present embodiment, a required conductive pattern including the required antenna coil 4 or the bump setting wiring 6 is formed on the completed wafer 31 and then the completed wafer 31 is scribed. Semiconductor chip 1
A to 1E are obtained, so that a coil-on-chip or CSP type semiconductor chip can be manufactured with higher efficiency as compared with a case where the antenna coil 4 or the bump setting wiring 6 is formed on each semiconductor chip. Cost can be reduced. Further, since the antenna coil 4 or the bump setting wiring 6 having a uniform thickness can be formed with high precision for all the semiconductor chips formed on the wafer 31, the variation in the communication characteristics can be reduced. Furthermore, when the antenna coil 4 or the bump setting wiring 6 is formed on each of the semiconductor chips 1A to 1E by using a sputtering method, a vacuum evaporation method, and a plating method, unnecessary conductors adhere to the outer peripheral portions of the semiconductor chips 1A to 1E. However, when a required conductive pattern including the antenna coil 4 or the bump setting wiring 6 is formed on the completed wafer 31, it is not necessary to form an outer peripheral portion of the completed wafer 31 at the time of sputtering or the like. Even if the conductor is attached, the portion is originally a portion to be disposed of as an unnecessary portion, and therefore does not adversely affect the insulating properties of the individual semiconductor chips 1A to 1E. In addition, in the method of forming the redistribution layer 3 of this example, the metal plating layer 39 is formed in the presence of the photoresist layer 35, and then the metal plating layer 39 of the metal sputtering layer or the metal deposition layer 34 is laminated. 8 is removed by etching.
As shown in (e), since the metal plating layer 39 is laminated only on the upper surface of the metal sputtering layer or the metal evaporation layer 34 and does not spread in the width direction, it is necessary to form the precise antenna coil 4 or the bump setting wiring 6. The antenna coil 4 having a large number of turns or a large number of wirings 6 for setting bumps can be formed in a small area.

<Second Example of Method for Forming Redistribution Layer>
A second example of the method for forming the rewiring layer 3 will be described with reference to FIG. FIG. 11 is a process chart showing a second example of the method for forming the redistribution layer 3.

According to the method of forming the redistribution layer 3 of this embodiment, FIG.
As shown in (a), a photoresist layer 35 is uniformly formed on a surface protection film 33 formed on a completed wafer 31,
The formed photoresist layer 35 is covered with a mask 35 on which a required pattern including the antenna coil 4 or the bump setting wiring 6 is formed, and the photoresist layer 35 is irradiated with light 37 having a predetermined wavelength from outside the mask 36. Expose. Thereafter, the exposed photoresist layer 35 is subjected to a development process, and as shown in FIG. 11B, the exposed portion of the photoresist layer 35 is removed, and a portion of the surface protection film 33 corresponding to the exposure pattern is removed. To expose. As shown in FIG. 10, the exposure pattern of the photoresist layer 35 is such that the antenna coil 4 or the bump setting wiring 6 and the lead portion 38 formed in portions other than the electrode portion 37 and the analog circuit 21 are formed.
And a shape including: Next, the completed wafer 31 after the development processing is mounted on a sputtering apparatus or a vacuum evaporation apparatus, and as shown in FIG.
A metal sputtered layer or a metal deposited layer 34 is formed on the exposed portion of the above. Next, as shown in FIG. 11D, after the photoresist layer 35 adhered to the completed wafer 31 is removed by an ashing process or the like, the electrode portion 37 is used as one of the electrodes to apply electric power to the metal sputtering layer or the metal deposition layer 34. Plating is performed, and a metal plating layer 39 is laminated on an exposed portion of the metal sputtering layer or the metal deposition layer 34 as shown in FIG. Finally, the completed wafer 31 is scribed, and the required semiconductor chip IC element 1 shown in FIGS.
A to 1E are obtained.

In the method of forming the redistribution layer 3 of the present embodiment, the electroplating method was used as the means for forming the metal plating layer 39. Instead of this configuration, the metal plating layer was formed by electroless plating. Layer 39 can also be formed. In this case, an electrode is not required for forming the metal plating layer 39, so that the exposure of the photoresist layer 35 does not require the formation of the electrode portion 37 and the formation of the lead portion 38.

The method of forming the redistribution layer 3 of this embodiment is based on the first method.
In addition to having the same effect as the method of forming the redistribution layer 3 according to the example, the number of steps for forming a conductive pattern on the completed wafer 31 can be reduced.
Type semiconductor chips can be manufactured with higher efficiency.

<First Example of Semiconductor Device> Next, a first example of a semiconductor device according to the present invention will be described with reference to FIG.
FIG. 12 is a cross-sectional view of the semiconductor device 40 according to the first embodiment.

The semiconductor device 40 according to the first embodiment is
As shown in FIG. 12, the coil-on-chip type semiconductor chip 1A or 1B is casing in a base body including an adhesive layer 41 and two cover sheets 42. As an adhesive constituting the adhesive layer 41,
Any known adhesive can be used as long as it has the required adhesive strength. However, it is particularly preferable to use a hot melt adhesive because of its excellent mass productivity. As the cover sheet 42, any sheet material belonging to the public domain can be used as long as it has the required strength and printability. For example, even if incinerated, such as polyethylene terephthalate, generation of harmful substances is small. It is particularly preferable to use a polymer sheet or paper. The semiconductor device 40 of this example has a first structure in which an adhesive layer 41 is formed on one side.
Semiconductor chip 1 on the adhesive layer 41 of the cover sheet 42 of FIG.
A or 1B is fixed, and then formed by bonding the adhesive layer 41 of the second cover sheet 42 having the adhesive layer 41 formed on one surface to the semiconductor chip bonding surface of the first cover sheet 42. it can.

The semiconductor device 40 of the present embodiment has the analog circuit 2
Since the semiconductor chip 1A or 1B in which the antenna chip 1 and the antenna coil 4 are arranged so as not to overlap with each other via the insulating layer 2 is mounted, no parasitic capacitance is formed between the analog circuit 21 and the antenna coil 4, and The occurrence of capacitance noise acting on the circuit 21 can be prevented. Also,
Since the analog circuit 21 and the antenna coil 4 are not arranged to face each other, it is possible to prevent the generation of electromagnetic induction noise acting on the analog circuit 21. Therefore, generation of crosstalk noise, ringing, power supply noise, and the like due to the electrostatic induction noise or the electromagnetic induction noise is prevented, and the coil-on-chip type semiconductor chip 1A or 1
The communication characteristics of the non-contact semiconductor device equipped with B can be improved. In addition, since the required semiconductor chip 1A or 1B can be manufactured simply by casing it with the two cover sheets 42, it is possible to manufacture the semiconductor chip at a low cost and in a very small size.

<Second Example of Semiconductor Device> Next, a second example of the semiconductor device according to the present invention will be described with reference to FIGS. FIG. 13 is a cross-sectional view of the semiconductor device according to the second embodiment, and FIG. 14 is a plan view of a booster coil provided in the semiconductor device according to the second embodiment.

The semiconductor device 50 according to the second embodiment is
As shown in FIG. 13, the coil-on-chip type semiconductor chip 1A or 1B and these semiconductor chips 1A
Alternatively, an insulating substrate 52 on which a booster coil 51 for enhancing electromagnetic coupling between an antenna coil 4 integrally formed on 1B and an antenna coil provided on a reader / writer (not shown) is formed by bonding an adhesive layer 41 and a cover sheet. 42. The casing is housed in a base body consisting of

As shown in FIG. 14, the booster coil 51 has a first coil 51a having a small winding diameter and a second coil 51a having a large winding diameter.
And a coil 51b, and are electrically connected to each other. The first coil 51a is a coil that is mainly electromagnetically coupled to the antenna coil 4 formed integrally with the semiconductor chip 1A or 1B, and has a planar shape and dimensions of an antenna coil 4 formed integrally with the semiconductor chip 1A or 1B. It is formed in the same or similar shape. On the other hand, the second coil 51b
This is a coil mainly electromagnetically coupled to an antenna coil provided in the reader / writer, and its planar shape and dimensions are formed as large as possible within a range that can be accommodated in the base formed by the adhesive layer 41 and the cover sheet 42. FIG.
In the example of No. 4, the first coil 51a and the second coil 51b are both formed in a rectangular spiral shape having a plurality of turns, but the number of turns and the planar shape of each of the coils 51a and 51b are not limited thereto. Instead, it can be formed arbitrarily. The booster coil 51 is connected to the insulating substrate 5
(2) An etching method for forming a required coil pattern by etching a conductive metal layer having a uniform thickness formed on one surface of the insulating substrate 52, or printing and forming a required coil pattern on one surface of the insulating substrate 52 using conductive ink. It can be formed by a suitable printing method.

The type of the adhesive forming the adhesive layer 41 and the type of the sheet material forming the cover sheet 42 are the same as those of the semiconductor device 40 according to the first embodiment. The description is omitted.

The semiconductor device 50 of the present embodiment has the same effects as the semiconductor device 40 according to the first embodiment, and further includes a booster coil, so that the semiconductor device 50 and the antenna coil 4 formed integrally with the semiconductor chip 1A or 1B can be used. There is an effect that electromagnetic coupling with an antenna coil provided in a reader / writer (not shown) can be strengthened.

<Third Example of Semiconductor Device> Next, a second example of the semiconductor device according to the present invention will be described with reference to FIG.
FIG. 15 is a sectional view of a main part of a semiconductor device according to the third embodiment.

The semiconductor device 60 according to the third embodiment is
As shown in FIG. 15, the first wiring layer 61, the first insulating layer 6
2, the second wiring layer 63, the first wiring layer 61 and the second wiring layer 63
63a, the second insulating layer 64, the semiconductor chip 1C, another mounting component 66, the conductor 67 connecting the second wiring layer 63 and the semiconductor chip 1C, the second wiring layer 63 and the other mounting component A semiconductor chip 1 for connecting the conductor 68 to the semiconductor chip 1
C, a mold resin 69 for integrally sealing the other mounting components 66 and the conductors 67, 68, a nickel layer (metal film) 70 locally formed on the outer surface of the first wiring layer 61, and a first wiring layer 61
And an external terminal 72 formed on the nickel layer 70.

The first wiring layer 61, the second wiring layer 63, and the connecting portion 63a are formed by electroplating (electroforming) copper or a copper alloy. As a copper alloy, copper-nickel alloy or copper-
Nickel-silver alloys are particularly suitable. The connecting portion 63a is connected to the first
The first wiring layer 61 is formed in the first opening 62 a formed in the insulating layer 62 and electrically connects the first wiring layer 61 and the second wiring layer 63.

The first insulating layer 62, the second insulating layer 64, and the protective resin layer 71 are formed of an insulating resin. In addition,
As the insulating resin, a photosensitive resin may be used to facilitate the formation of the first insulating layer 62, the second insulating layer 64, and the protective resin layer 71. In the first insulating layer 62,
First openings 62a for forming the connection portions 63a are formed in a required arrangement, and the second insulating layer 64 has conductors 67 and 6 formed therein.
8 are formed in a required arrangement.

As the other mounting components 66, chip components such as transistors, diodes, resistors, inductors, capacitors, crystal oscillators, filters, baluns, antennas, functional modules, and external connectors can be mounted. The functional modules include a VCO,
A PLL or a power supply regulator is included.

As the conductor 68 for connecting the other mounting component 66 to the second wiring layer 63, a conductive paste or an anisotropic conductive adhesive can be used, but a low-cost and highly reliable connection is possible. Therefore, solder is particularly suitable.

The molding resin 69 is provided in the semiconductor chip 1.
C, other mounted components 66, and each of these mounted components 1C, 6
6 and the connection portion of the second wiring layer 63 are integrally resin-sealed, and can be formed using various resin materials conventionally applied to resin sealing of semiconductor chips.

The nickel layer 70 facilitates the formation of the external terminals 72, and is formed on the terminal portion of the first wiring layer 61 where the external terminals 72 are to be formed.

The external terminal 72 is used to connect the semiconductor device 60 according to the present embodiment to an external device, for example, a printed wiring board. The external terminal 72 can be easily connected at low cost and with high reliability. For this reason, it is particularly preferable to use a solder.

The semiconductor device 60 of this embodiment has the same effects as the semiconductor device 40 according to the first embodiment, and furthermore, the wiring means for the mounted components 1C and 66 are formed by wiring layers 61 and 63 and protective resin layers 62 and 64. Therefore, the portion corresponding to the core material of the conventional multilayer substrate can be omitted, and a thin and inexpensive semiconductor device can be obtained. In addition, the wiring layer 6
Since 1,63 is used, the wiring pattern has a higher density, higher precision, smaller size, and homogenization as compared with the case of using a substrate having a lead frame or a wiring layer formed by metal foil etching or conductive paste printing. Therefore, a small-sized semiconductor module having high frequency compatibility can be obtained. Further, since the first wiring layer 61 and the second wiring layer 63 electrically connected thereto are formed in two layers,
The formation area of the wiring layers 61 and 63 can be reduced, and the size of the semiconductor device can be reduced.

In the above embodiment, the wiring layer is formed in two layers, but it is of course possible to form three or more wiring layers. In the above embodiment, the CSP type semiconductor chip 1C is used as the semiconductor chip.
P-type semiconductor chips 1D and 1E can also be used.

[0083]

According to the first aspect of the present invention, the analog circuit formed on the circuit formation surface of the semiconductor chip and the rewiring layer are arranged so as not to overlap with each other via the insulating layer. No parasitic capacitance is formed with the wiring layer,
It is possible to prevent generation of capacitance noise acting on the analog circuit. Further, since the analog circuit and the redistribution layer are not arranged to face each other, it is possible to prevent the generation of electromagnetic induction noise acting on the analog circuit. Therefore, the occurrence of crosstalk noise, ringing, power supply noise, and the like due to the electrostatic induction noise or the electromagnetic induction noise is prevented, and malfunction and communication caused by the noise are prevented even in the high-frequency compatible rewiring layer integrated semiconductor chip. Deterioration of characteristics can be eliminated.

According to a second aspect of the present invention, a power supply circuit, an operational amplifier, a comparison amplifier, an RF receiver, an RF transmitter, and an RF synthesizer which are particularly susceptible to noise among analog circuits formed on a circuit forming surface. Since at least one of the sections and the rewiring layer are arranged so as not to overlap with each other via the insulating layer, for each circuit block, crosstalk noise, ringing, and ringing noise caused by electrostatic induction noise or electromagnetic induction noise are obtained. It is possible to prevent power supply noise and the like, and it is possible to eliminate malfunctions and deterioration of communication characteristics caused by the noise.

According to the third aspect of the present invention, among the analog circuits formed on the circuit forming surface, the coil and the rewiring layer which are particularly susceptible to noise are arranged so as not to overlap with each other via the insulating layer. Therefore, electrostatic induction noise and electromagnetic induction noise hardly act on the coil, and malfunctions and deterioration of communication characteristics due to the noise can be eliminated.

According to the fourth aspect of the present invention, since the antenna coil for non-contact communication is formed with the rewiring layer, a coil-on-chip type semiconductor chip having excellent noise resistance can be obtained, and the cost can be reduced. Therefore, a non-contact type semiconductor device having excellent noise resistance can be manufactured.

According to the fifth aspect of the present invention, since the bump setting wiring is formed with the rewiring layer, a CSP type semiconductor chip having excellent noise resistance can be obtained. An excellent semiconductor device can be obtained.

According to a sixth aspect of the present invention, a redistribution layer is arranged so that a redistribution layer is not formed on an analog circuit in a semiconductor chip having a wireless communication circuit formed on a circuit formation surface by CMOS technology. It is possible to prevent the communication characteristics of this type of semiconductor chip, which is particularly susceptible to the influence of the rewiring layer, from deteriorating.

According to a seventh aspect of the present invention, a semiconductor chip on which a wireless communication circuit for transmitting, receiving or transmitting / receiving a signal having a frequency of 800 MHz or higher is formed so that a redistribution layer is not formed on an analog circuit. Since the layers are arranged, it is possible to prevent the communication characteristics of this type of semiconductor chip, which is particularly susceptible to the rewiring layer, from deteriorating.

According to the eighth aspect of the present invention, a semiconductor chip in which an analog circuit formed on a circuit forming surface and a rewiring layer are arranged so as not to overlap with each other via an insulating layer is mounted on a semiconductor device. A malfunction due to electrostatic induction noise or electromagnetic induction noise or deterioration of communication characteristics hardly occurs in an analog circuit of a semiconductor chip, and a semiconductor device with good communication characteristics can be obtained.

According to the ninth aspect of the present invention, a power supply circuit, an operational amplifier, a comparison amplifier, an RF receiver, an RF transmitter, and an RF synthesizer, which are particularly susceptible to noise, among analog circuits formed on a circuit forming surface. Since a semiconductor chip in which at least one of the parts and the redistribution layer are arranged so as not to overlap with each other via the insulating layer is mounted on the semiconductor device, it is possible to minimize the influence of noise on those circuits which are most likely to be adversely affected by noise. A malfunction due to electrical induction noise or electromagnetic induction noise or deterioration of communication characteristics is less likely to occur, and a semiconductor device with good communication characteristics can be obtained.

According to the tenth aspect of the present invention, among the analog circuits formed on the circuit forming surface, the coil and the rewiring layer which are particularly susceptible to noise are arranged so as not to overlap with each other via the insulating layer. Mounted semiconductor chip,
A semiconductor device having good communication characteristics can be obtained without electrostatic induction noise or electromagnetic induction noise acting on a coil which is easily affected by the adverse influence of noise.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor chip 1A according to a first embodiment.

FIG. 2 is a sectional view taken along line AA of FIG.

FIG. 3 is a plan view of a semiconductor chip 1B according to a second embodiment.

FIG. 4 is a plan view of a semiconductor chip 1C according to a third embodiment.

FIG. 5 is a sectional view taken along line BB of FIG. 4;

FIG. 6 is a plan view of a semiconductor chip 1D according to a fourth embodiment.

FIG. 7 is a plan view of a semiconductor chip 1E according to a fifth embodiment.

FIG. 8 is a plan view of a so-called completed wafer completed through a predetermined process.

FIG. 9 is a process chart showing a first example of a method for forming a redistribution layer.

FIG. 10 is a plan view of a completed wafer on which a rewiring layer 3 has been formed.

FIG. 11 is a process chart showing a second example of a method for forming a redistribution layer.

FIG. 12 is a cross-sectional view of the semiconductor device according to the first embodiment.

FIG. 13 is a sectional view of a semiconductor device according to a second embodiment.

FIG. 14 is a plan view of a booster coil provided in the semiconductor device according to the second embodiment.

FIG. 15 is a sectional view of a main part of a semiconductor device according to a third embodiment;

FIG. 16 is a plan view of a conventional coil-on-chip type semiconductor chip.

FIG. 17 is a sectional view of a conventional coil-on-chip type semiconductor chip.

FIG. 18 is a plan view of a conventional CSP type semiconductor chip.

FIG. 19 is a sectional view of a conventional CSP type semiconductor chip.

FIG. 20 is an explanatory diagram of a parasitic capacitance formed between a circuit portion of a semiconductor chip and an antenna coil.

[Explanation of symbols]

 1A to 1E Semiconductor chip 2 Insulating layer 3 Rewiring layer 4 Antenna coil 6 Bump forming wiring 11 Power supply circuit 12 Operational amplifier 13 Comparative amplifier 14 RF receiving unit 15 RF transmitting unit 16 RF synthesizer unit 21 Analog circuit 40, 50, 60 Semiconductor apparatus

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) G06K 19/077 G06K 19/00 H (72) Inventor Kazunari Nakagawa 1-188 Ushitora, Ibaraki-shi, Osaka (72) Inventor Yoshiharu Hino 1-88 Ushitora, Ibaraki-shi, Osaka F-term (reference) in Hitachi Maxell, Ltd. 5B035 BA03 BB09 CA01 CA23 CA31

Claims (10)

[Claims] In a semiconductor chip having a rewiring layer integrally formed on a circuit formation surface via an insulating layer, all or a part of an analog circuit formed on the circuit formation surface and the rewiring layer are formed. A semiconductor chip, wherein the semiconductor chips are arranged so as not to overlap with each other via the insulating layer. 2. A semiconductor chip in which a rewiring layer is integrally formed on a circuit forming surface via an insulating layer, wherein a power supply circuit, an operational amplifier, a comparison amplifier,
A semiconductor chip, wherein at least one of an RF receiving unit, an RF transmitting unit, and an RF synthesizer unit and the rewiring layer are arranged so as not to overlap with each other via the insulating layer. 3. A semiconductor chip in which a rewiring layer is integrally formed on a circuit forming surface via an insulating layer, wherein a coil formed on the circuit forming surface and the rewiring layer are connected via the insulating layer. A semiconductor chip characterized by being arranged so as not to overlap. 4. The non-contact communication chip according to claim 1, wherein both ends of the semiconductor chip are connected to input / output terminals formed on the circuit forming surface with the rewiring layer. A semiconductor chip having an antenna coil formed thereon. 5. The semiconductor chip according to claim 1, wherein one end of the semiconductor chip is connected to an input / output terminal formed on the circuit forming surface with the rewiring layer.
A semiconductor chip comprising a bump setting wiring having a bump formed on the other end. 6. The semiconductor chip according to claim 1, wherein the circuit formed on the circuit formation surface is a wireless communication circuit formed by a CMOS technology. Chips. 7. The semiconductor chip according to claim 1, wherein the circuit formed on the circuit formation surface transmits, receives, or receives a signal having a frequency of 800 MHz or more with an external device. A semiconductor chip, which is a wireless communication circuit for transmitting and receiving. 8. A semiconductor device in which a semiconductor chip is mounted on a base having a predetermined size and a predetermined shape, wherein a redistribution layer is integrally formed on a circuit forming surface via an insulating layer as the semiconductor chip; A semiconductor device comprising a semiconductor chip on which all or a part of an analog circuit formed on a circuit formation surface and the rewiring layer are arranged so as not to overlap with each other via the insulating layer. 9. A semiconductor device in which a semiconductor chip is mounted on a base having a predetermined size and a predetermined shape, wherein a redistribution layer is integrally formed as a semiconductor chip on a circuit forming surface via an insulating layer; At least one of a power supply circuit, an operational amplifier, a comparison amplifier, an RF receiving unit, an RF transmitting unit, and an RF synthesizer unit formed on a circuit forming surface does not overlap with the rewiring layer via the insulating layer. A semiconductor device having mounted thereon semiconductor chips arranged as described above. 10. A semiconductor device comprising a semiconductor chip mounted on a substrate having a predetermined size and a predetermined shape, wherein a redistribution layer is integrally formed on a circuit forming surface via an insulating layer as the semiconductor chip; A semiconductor device comprising a semiconductor chip on which a coil formed on a circuit forming surface and the rewiring layer are arranged so as not to overlap with each other via the insulating layer.