506045 A7 B7 662 8twf. doc/〇 〇6 五、發明說明（） 本發明是有關於一種晶片上具有電感元件結構，且 特別是有關於積體電路晶片外覆上一外部介電層，在此外 邰介電層之上，再鋪上各種形式之電感元件。 現今的高頻砍晶片（RF silicon cliip)以內建電感元件 之方式’將電感元件置於晶片之保護層下方，由於電感很 接近矽基底(<1〇μηι以下），在使用高頻元件的之頻率下， 矽基底會變成導體，並且消耗掉大量的能量，使得電感元 件之品質降低。再者，由於砷化鎵（GaAs)在高頻時會產生 半導體的隔離效果，因此坊間在製作高頻矽晶片時，通常 會使用昂貴的砷化鎵(GaAs)來替代矽作爲晶片，以改善電 感元件之能量消耗，提高高頻矽晶片之品質。 然而，砷化鎵(GaAs)晶片雖具有半導體之隔離效果， 但因其材料本身過於昂貴，使得製造成本遠高過金氧半導 體(CMOS) 〇 因此本發明的目的之一即在提供一種晶片上具有電感 元件結構，可以使電感元件遠離矽基底，以降低矽基底對 電感元件所造成的導磁干擾，以提高晶片效能，此結構尤 其針對高磁通量的被動元件或者設計高頻被截之電路設計 特別具有效率性。 本發明的目的之_^在於提出一'種晶片上具有電感兀 件結構，可以將電感元件配置於晶片之外，故可使用以矽 爲材質之晶片，而不須使用昂貴的砷化鎵（GaAs)晶片，如 此可以降低製造成本。 爲達成本發明之上述和其他目的，提出一種晶片上 4 本紙張尺度適用中國國家標準（CNS)A4規格（2】〇 X 297公釐i -- - -----I ---illlIII --I I I I I —Aw (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 506045 β 62 8 twf. doc/Ο 06 Α7 Β7 經濟部智慧財產局員工消費合作社印製 五、發明說明（2) 具有電感元件結構，分別包括：一晶片，此晶片具有一主 動表面，而晶片之主動表面暴露出多個接點。一寬導線結 構體’此覓導線結構體包括一^外部介電層、~~~~'立體化寬線 路結構，此寬導線結構體位於該晶片之主動表面之上，而 立體化寬線路結構交錯於外部介電層之內，且立體化寬線 路結構與晶片之接點電性連通。以及至少一電感元件，此 電感元件鋪設於寬導線結構體之上，並且電感元件與立體 化寬線路結構電性連接。 依照本發明的一較佳實施例，其中在晶片之主動表 面之表層還包括一保護層，而保護層暴露出晶片之接點。 力外’寬導線結構體還暴露出至少一防磁物質，而防磁物 質與晶片之主動表面接觸’且防磁物質的位置與電感元件 之位置相對應，防磁物質之材質包括金屬或其他磁性物 質。此外，電感元件之形式包括水平螺旋形式、立體螺旋 形式、環狀立體螺旋形式。再者，外部介電層之材質包括 聚亞醯胺或苯基環丁烯’其中外部介電層聚亞醯胺的形成 方式可以用旋塗固化的方式形成，旋塗後之聚亞醯胺需在 一真空環境中進行固化或在一氮氣環境下進行固化，溫度 保持在250度至400度之間，所需時間約〇.5至1.5個小時， 而厚度較厚之聚亞醯胺結構，可採用多層旋塗固化的方式 形成。另外，塡入立體化寬線路結構之方式可包括電鑛、 無電電鑛、濺鑛等方式，而立體化寬線路結構之導電材質 可包括銅、金、鎳、鋁、鎢等。 爲達成本發明之上述和其他目的，提出一種晶片上 5 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公爱） (請先閱讀背面之注音？事項再填寫本頁) f 訂----------線· 506045 五 A7 B7 662 8twf. doc/006 發明說明（+) 具有電感元件結構’分別包括：一晶片’此晶片具有一主 動表面，而晶片之主動表面暴露出多個接點。以及至少一 電感元件，此電感元件鋪設於晶片之主動表面之上’並且 電感元件與晶片之接點電性連接。 依照本發明的一較佳實施例，其中在晶片之主動表 面之表層還包括一保護層，而保護層暴露出晶片之接點。 此外，電感元件之形式包括水平螺旋形式、立體螺旋形式、 環狀立體螺旋形式。再者，外部介電層之材質包括聚亞醯 胺或苯基環丁烯，其中外部介電層聚亞醯胺的形成方式可 以用旋塗固化的方式形成，旋塗後之聚亞醯胺需在一真空 環境中進行固化或在一氮氣環境下進行固化，溫度保持在 250度至400度之間，所需時間約〇.5至1.5個小時，而厚 度較厚之聚亞醯胺結構，可採用多層旋塗固化的方式形 成。另外，塡入立體化寬線路結構之方式可包括電鑛、無 電電鍍、濺鍍等方式，而立體化寬線路結構之導電材質可 包括銅、金、鎳、鋁、鎢等。 爲讓本發明之上述和其他目的、特徵、和優點能更 明顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1圖、第2圖、第3圖繪示依照本發明第一較佳 實施例的一種晶片上具有電感元件結構之製程剖面示意 圖。 ----------------I---I---11--^ (請先閱讀背面t注音3事項再填寫本頁> 經濟部智慧財產局員工消費合作社印製 506045 A7 B7 6628twf.doc/006 五、發明說明（斗） 第4圖繪示對應於第3圖中水平螺旋形式電感之俯 視示意圖。 第5圖繪示依照本發明第二較佳實施例的一種晶片 上具有電感元件結構之剖面示意圖。 第6圖繪示依照本發明第三較佳實施例的一種晶片 上具有電感元件結構之立體剖面透視示意圖。 第7圖繪示對應於第6圖中電感元件結構之俯視示 意圖。 第8圖繪示對應於第7圖中剖面線I - I之剖面示意 圖。 第9圖繪示依照本發明第四較佳實施例的一種晶片 上具有電感元件結構之立體剖面透視示意圖 第10圖繪示對應於第9圖中電感元件結構之俯視 示意圖。 第11圖繪示依照本發明第五較佳實施例的一種晶 片上具有電感元件結構之剖面示意圖。 ---------------------訂-------！線#· (請先閱讀背面之注音3事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 圖式之標記說明： 100 : 晶片 101 : 表面 102 ： 基底 104 ： 元件層 106 : 積層 108 ： 金屬層 7 本紙張尺度適用中國國家標準（CNS)A4規格（2〗〇χ 297公釐） 經濟部智慧財產局員工消費合作社印製 506045 五、發明說明（& ) no :介電層 112 :保護層 130 :寬導線結構體 114 :外部介電層 116 :開孔 210、310 :電感結構體 212、312 :第一表面 222、322 :第一圖案化線路 214、314 ·•第二表面 224、324 :第二圖案化線路 230、330 :貫孔 226、326 :絕緣層 118、218、318、418 :電感元件 134 :連外接點 150 :種子層 152 :金屬層 136、410 :焊罩層 122 :立體化寬線路結構 124 :接點 126 :防磁物質 350a、350b、350c、350d :曲線 實施例 請參照第1圖、第2圖、第3圖，其繪示依照本發 本紙張尺度適用中國國家標準（CNS)A4規格（2.10 X 297公釐） -----------I i丨丨· —丨丨訂·丨—丨·丨丨丨線 (請先閲讀背面之注意事項再填寫本頁) 506045 A7 B7 6628twf.doc/006 五、發明說明（) 明第一較佳實施例的一種晶片上具有電感元件結構之製程 剖面示意圖。 請先參照第1圖，晶片100係由一基底102、一元 件層(DeviceLayer)104、一積層106、一保護層112所組成。 基底102,比如是互補金氧半導體（CMOS)常用之矽基底 (Silicon Substrate)，具有一表面101。元件層104，具有比 如是電晶體等元件，配置於基底102之表面101上，在元 件層104上再覆蓋積層106,而積層106由至少一金屬層1〇8 與至少一介電層Π0交互疊合而成，金屬層1〇8更包括數 個金屬內連線（未繪示），以連接元件層104。金屬內連線 之材質係選自於由鋁、鋁合金、銅、銅合金、以及黃金所 組成之族群中的一種材料。接著覆蓋保護層112(Passivation) 於積層106之上，而保護層112還具有多個接點124與金 屬內連線（未繪示)電性連通。保護層112之上再覆蓋外部 介電層114(Post Passivation)。保護層112係以氮化砂或氧 化砂沈積(Deposition)而成，而外部介電層114之材質包括 聚亞醯胺、苯基環丁烯等，而聚亞醯胺的形成方式可以用 旋塗固化的方式形成，旋塗後之聚亞醯胺需在一真空環境 中進行固化或在一氮氣環境下進行固化，溫度保持在250 度至400度之間，所需時間約〇·5至1.5個小時，若是厚 度較厚之聚亞醯胺結構，可採用多層旋塗固化的方式、多 層疊合（laminating)的方式、或網板印刷（screen printing)的 方式形成。 在外部介電層114內，利用微影蝕刻的方式形成數 9 本紙張尺度適用中國國家標準（CNS)A4規格（210x 297公釐） -------------------丨訂--------·線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 506045 A7 B7 6628twf.doc/006 五、發明說明（q) 個開孔116，再以一導電材質塡入開孔116中，而形成一 寬導線結構體130，並且定義此導電材質的沈積結構爲立 體化寬線路結構122，而立體化寬線路結構122與保護層 112之多個接點124電性連接，而立體化寬線路結構122 的導電材質可包括銅、金、鋁、鎳、鎢等，另外由於此製 作寬導線結構體的導線線寬（約數十微米）並不如半導體前 段製程（小於一微米）之精密，因此可使用低成本之製程， 如電鍍、無電電鍍之方式形成，亦可使用濺渡（sputtering) 的方式。並且寬導線結構體的導線厚度可達3微米以上， 如此可以大幅降低因導線所造成的訊號衰減或延遲。其中 寬導線結構體130的厚度可介於20微米與100微米之間。 請參照第2圖，在製作寬導線結構體之後，接下來 進行電感元件製作之製程，首先以濺鍍的方式鋪上一種子 層150於寬導線結構體130上，而種子層150的材質可以 包括鋅，然後再以電鍍的方式鋪上一金屬層152於種子層 150 上。 請參照第3圖、第4圖，其中第4圖繪示對應於第 3圖中水平螺旋形式電感之俯視示意圖。接下來，再透過 微影蝕刻的方式，定義出至少一電感元件118，以及至少 一連外接點134,最後鋪上一焊罩層136覆蓋電感元件118 ’ 並且暴露出連外接點134。其中連外接點134、電感元件118 均與立體化寬線路結構122電性連接，而電感元件118之 型態爲水平螺旋狀(如第4圖所示）。 上述之電感元件118的配置，可以使電感元件118 本紙張尺度適用中國國家標準（CNS)A4規格（210x 297公釐） -----------,f--------訂---------線參 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 506045 A7 B7 6628twf.doc/006 五、發明說明（X ) 遠離以矽爲材質之基底102,並降低基底102對電感元件 118所造成的導磁干擾，以提高晶片效能，此結構尤其針 對高磁通量的被動元件或者設計高頻被截之電路設計特別 具有效率性。再者，由於電感元件118配置於晶片之外， 故可使用以矽爲材質之晶片，而不須使用昂貴的砷化鎵 (GaAs)晶片，可以降低製造成本。 請參照第5圖，其所繪示依照本發明第二較佳實施 例的一種晶片上具有電感元件結構之剖面示意圖。與上述 第一較佳實施例不同的是，在本發明之第二較佳實施例中 寬導線結構體130還包括至少一防磁物質I%，並且寬導 線結構體130暴露出防磁物質126，與保護層112接觸， 並且防磁物質126的位置與電感元件us之位置相對應， 防磁物質126係用以阻隔電感元件U2對以砂爲材質的基 底102所產生的導磁效應，因此本發明可應用於更高磁通 量的被動兀件或者設計更高頻被截之電路設計。防磁物質 126之材質包括金屬或是磁性物質。 請參照第6圖、第7圖、第8圖，其中第6圖繪示 依照本發明第三較佳實施例的一種晶片上具有電感元件結 構之JL體剖面透視不意圖，而第7圖繪示對應於第6圖中 電感兀件結構之俯視不意圖，第8圖繪示對應於第7圖中 剖面線I - I之剖面不意圖。在前述之第一較佳實施例中， 電感兀件之形式係爲水平螺旋狀，然而電感元件之形式並 非侷限於上述的方式，電感元件218可以設計成立體螺旋 狀。一電感結構體21〇係由一絕緣層226以及一電感元件 - ----丨丨丨—丨S·丨丨！訂·------·線 (請先閱讀背面之注音？事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公爱） 506045 A7 B7 6628twf.doc/006 五、發明說明（q ) 218所組成，並且電感結構體210具有一第一表面212興 對應之一第二表面214，而電感結構體210以其第一表® 212與寬導線結構體130接觸，而寬導線結構體130位於 晶片100之保護層112之上，且寬導線結構體130的厚度 介於20微米與100微米之間。在電感結構體210之第一表 面212具有一第一圖案化線路222(如第7圖中虛線222所 示），而電感結構體210之第二表面214具有一第二圖案化 線路224(如第7圖中實線224所示），並且透過貫孔230內 的導電材質可以使第一圖案化線路222與第二圖案化線路 224電性蓮通，使其形成立體螺旋狀之電感元件218 ° 而立體螺旋狀之電感元件218的製造步驟，係先以 濺鍍的方式覆上一種子層於寬導線結構體130上，再以電 鍍的方式覆上一金屬層於種子層上，微影飩刻定義出第一 圖案化線路222。接下來覆上一絕緣層226於寬導線結構 體130上，並覆蓋住第一圖案化線路222，並透過微影鈾 刻的方式形成多個貫孔230，再以鍍穿孔(plate thr〇ugh h〇le) 的方式塡入一導電材質於貫孔230內。接下來以濺鍍的方 式覆上一種子層於絕緣層216上，再以電鍍的方式覆上一 金屬層於種子層上，然後以微影蝕刻的方式，定義出第二 圖案化線路224。此外，在電感結構體21〇之第一表面214 還可以塗佈一焊罩層（solder mask)，爲熟習該技術者應知 的結構，在此不再贅述。 g靑爹照第9圖、第10圖’第9圖繪示依照本發明 第四較佳實施例的一種晶片上具有電感元件結構之立體剖 12 本纸張尺度適用中國國家標準（CNS)A4規格（210x 297公釐） 广請先B3讀背面之涑意事頊再填寫本頁) -ϋ n n n n n n I l_i ϋ n n n -ϋ ϋ I - 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 506045 五、發明說明（丨0) 面透視示意圖，其中在第9圖中僅繪示出部份第一圖案化 線路與第二圖案化線路的連接關係，而第10圖繪示對應 於第9圖中電感元件結構之俯視示意圖。在本實施例中， 電感元件318亦可以設計成環狀立體螺旋狀。一電感結構 體310係由一絕緣層326以及一電感元件318所組成，絕 緣層326將電感元件318包覆其中，並且電感結構體310 具有一第一表面312與對應之一第二表面314，而電感結 構體310以其第一表面312與寬導線結構體130接觸，而 寬導線結構體130位於晶片100之保護層112之上，且寬 導線結構體130的厚度介於20微米與1〇〇微米之間。在電 感結構體310之第一表面312具有一第一圖案化線路322(如 第10圖中虛線322所示），而電感結構體310之第二表面 314具有一第二圖案化線路324(如第10圖中實線324所 示），並且透過貫孔330內的導電材質可以使第一圖案化線 路322與第二圖案化線路324電性連通，使其形成環狀立 體螺旋狀之電感元件318。另外，曲線350a、350b、350c、 350d描繪出電感元件318所環繞空間區域的大致形狀。 而環狀立體螺旋狀之電感元件318製程與第三實施 例中立體螺旋狀之電感元件製程雷同’只是環狀立體螺旋 狀之電感元件318排歹tl爲_狀’在此不再贅述° 在前述之電感元件乃在晶片之外部形成’相較於晶 片內部所製作的電感元件，本發明之電感元件的導線厚度 比較厚，且線寬較寬，因此具有較佳的品質。另外相較於 晶片內部所製作的立體狀電感元件，本發明之立體螺旋形 1本紙狀度剌規格⑵〇 X 297公爱) -----------丨 --------訂---------線 <請先閱讀背面之注意事項再填寫本頁) 506045 A7 B7 662Btwf.doc/006 五、發明說明（丨I ) 狀及環狀立體螺旋狀之電感元件的高度比較高且遠離基 底，故具有較佳的品質。 請參照第11圖，其繪示依照本發明第五較佳實施 例的一種晶片上具有電感元件結構之剖面示意圖。在前述 之第一較佳實施例中，係將電感元件鋪設於寬導線結構體 上，然而電感元件之配置並非侷限於上述的方式，亦可以 將電感元件418直接鋪設於保護層112上，然後再覆上一 焊罩層410以保護電感元件418。在本實施例中係以水平 螺旋狀之電感元件爲例，然而本實施例亦可以應用於立體 螺旋狀之電感元件或是環狀立體螺旋狀之電感元件，其中 立體螺旋狀或環狀立體螺旋狀之電感元件，其電感結構體 之厚度介於20微米與100微米之間。 綜上所述，本發明至少具有下列優點： 1. 本發明之晶片上具有電感元件結構，可以使電感 元件遠離矽基底，以降低矽基底對電感元件所造成的導磁 干擾，以提高晶片效能，此結構尤其針對高磁通量的被動 元件或者設計高頻被截之電路設計特別具有效率性。 2. 本發明之晶片上具有電感元件結構，可以安置一 防磁物質於寬導線結構體之內，以阻隔以矽爲材質的基底 對電感元件產生導磁的效應，如此可應用於更高磁通量的 被動元件或者設計更高頻被截之電路設計。 3·本發明之晶片上具有電感元件結構，可以將電感 元件配置於晶片之外，故可使用以矽爲材質之晶片，而不 須使用昂貴的砷化鎵(GaAs)晶片，如此可以降低製造成本。 -----------------訂----!-線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 …，用中國國家標準(€奶从4規格（2]0><297公爱 506045 A7 6 62 8 twf · ci〇 c/ 〇 〇 6 五、發明說明（（λ) 4·本發明之晶片上具有電感元件結構，由於電感元 件乃在晶片之外部形成，相較於晶片內部所製作的電感元 件’本發明之電感元件的導線厚度比較厚，且線寬較寬， 因此具有較佳的品質。 5·本發明之晶片上具有電感元件結構，由於電感元 件可形成於晶片外部的電感結構體中，因此可以有立體螺 旋形狀及環狀立體螺旋狀之電感元件之結構。相較於晶片 內部所製作的立體狀電感元件，本發明之立體螺旋形狀及 環狀立體螺旋狀之電感元件的高度比較高且遠離基底，故 具有較佳的品質。 雖然本發明已以較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公t )506045 A7 B7 662 8twf. Doc / 〇〇6 5. Description of the invention () The invention relates to a chip with an inductive element structure, and in particular to an integrated circuit chip coated with an external dielectric layer.之上 On top of the dielectric layer, various forms of inductive elements are laid. Today's RF silicon cliip uses built-in inductors to 'place inductors under the protective layer of the chip. Because the inductor is very close to the silicon substrate (<10 μηι), high-frequency components are used. At the frequency, the silicon substrate will become a conductor and consume a lot of energy, which will reduce the quality of the inductive element. In addition, because gallium arsenide (GaAs) produces semiconductor isolation at high frequencies, when manufacturing high-frequency silicon wafers, expensive gallium arsenide (GaAs) is often used instead of silicon as a wafer to improve The energy consumption of inductive components improves the quality of high-frequency silicon chips. However, although gallium arsenide (GaAs) wafers have the isolation effect of semiconductors, the material itself is too expensive, which makes the manufacturing cost far higher than metal oxide semiconductors (CMOS). Therefore, one of the objects of the present invention is to provide a wafer It has an inductive element structure, which can keep the inductive element away from the silicon substrate, so as to reduce the magnetic permeability interference caused by the silicon substrate to the inductive element and improve the chip performance. This structure is especially designed for passive components with high magnetic flux or high-frequency intercepted circuit design. Especially efficient. The object of the present invention is to propose a kind of chip with an inductor element structure, which can be arranged outside the chip, so a silicon-based wafer can be used instead of expensive gallium arsenide ( GaAs) wafers, which can reduce manufacturing costs. In order to achieve the above and other objectives of the invention, a paper size of 4 papers on a wafer is proposed to comply with the Chinese National Standard (CNS) A4 specification (2) 0X 297 mmi----I --- illlIII- -IIIII —Aw (Please read the notes on the back before filling out this page) Printed by the Employees ’Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 506045 β 62 8 twf. Doc / Ο 06 Α7 Β7 Printed by the Employees’ Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 2. Description of the invention (2) Inductive element structures, including: a chip, the chip has an active surface, and the active surface of the chip exposes multiple contacts. A wide wire structure External dielectric layer, ~~~~ 'three-dimensional wide line structure, this wide wire structure is located on the active surface of the chip, and the three-dimensional wide line structure is staggered within the outer dielectric layer, and the three-dimensional wide line is The structure is in electrical communication with the contacts of the chip. And at least one inductive element is laid on the wide wire structure, and the inductive element is electrically connected to the three-dimensional wide-line structure. In an embodiment, the surface layer on the active surface of the wafer further includes a protective layer, and the protective layer exposes the contacts of the wafer. The extra-wide wire structure also exposes at least one antimagnetic substance, and the antimagnetic substance and the active surface of the wafer The position of the anti-magnetic substance corresponds to the position of the inductive element. The material of the anti-magnetic substance includes metal or other magnetic substances. In addition, the form of the inductive element includes a horizontal spiral form, a three-dimensional spiral form, and a ring-shaped three-dimensional spiral form. Furthermore, The material of the outer dielectric layer includes polyimide or phenylcyclobutene. The polyimide of the outer dielectric layer can be formed by spin coating and curing. The polyimide after spin coating needs to be Curing in a vacuum environment or curing under a nitrogen atmosphere, the temperature is maintained between 250 degrees and 400 degrees, the time required is about 0.5 to 1.5 hours, and the thicker polyimide structure can be used Multi-layer spin-coating method is formed. In addition, the method of injecting the three-dimensional wide-line structure may include electric ore, non-electric power ore, and splattering, and the three-dimensional wide line The conductive material of the structure can include copper, gold, nickel, aluminum, tungsten, etc. In order to achieve the above-mentioned and other purposes of the invention, a paper on a wafer is proposed. The 5 paper sizes are applicable to the Chinese National Standard (CNS) A4 specification (210 x 297). ) (Please read the note on the back? Matters before filling out this page) f Order ---------- line · 506045 five A7 B7 662 8twf. Doc / 006 Description of the invention (+) Inductive element structure 'respectively Including: a chip 'the chip has an active surface, and the active surface of the chip exposes multiple contacts. And at least one inductive element, the inductive element is laid on the active surface of the chip' and the contact point between the inductive element and the chip Electrical connection. According to a preferred embodiment of the present invention, the surface layer on the active surface of the wafer further includes a protective layer, and the protective layer exposes the contacts of the wafer. In addition, the form of the inductance element includes a horizontal spiral form, a three-dimensional spiral form, and a circular three-dimensional spiral form. Furthermore, the material of the outer dielectric layer includes polyimide or phenylcyclobutene, wherein the polyimide of the outer dielectric layer can be formed by spin coating and curing, and the polyimide after spin coating is formed. Need to be cured in a vacuum environment or a nitrogen environment, the temperature is maintained between 250 degrees and 400 degrees, the time required is about 0.5 to 1.5 hours, and the thicker polyimide structure , Can be formed by multi-layer spin coating curing. In addition, the way to embed the three-dimensional wide line structure may include electric ore, electroless plating, sputtering, etc., and the conductive material of the three-dimensional wide line structure may include copper, gold, nickel, aluminum, tungsten, and the like. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following describes the preferred embodiments in detail with the accompanying drawings, as follows: Brief description of the drawings: Figure 1, FIG. 2 and FIG. 3 are schematic cross-sectional views of a manufacturing process with an inductor element structure on a wafer according to a first preferred embodiment of the present invention. ---------------- I --- I --- 11-^ (Please read the note 3 on the back before filling out this page > Staff Consumption of Intellectual Property Bureau, Ministry of Economic Affairs Printed by the cooperative 506045 A7 B7 6628twf.doc / 006 V. Description of the invention (bucket) Figure 4 shows a schematic top view corresponding to the horizontal spiral form inductor in Figure 3. Figure 5 shows a second preferred implementation according to the invention Example is a schematic cross-sectional view of a structure with an inductive element on a wafer. FIG. 6 shows a perspective view of a three-dimensional cross-section of a structure with an inductive element on a wafer according to a third preferred embodiment of the present invention. A schematic top view of the structure of the inductive element in the figure. Fig. 8 shows a schematic cross-section corresponding to the section line I-I in Fig. 7. Fig. 9 shows an inductive element on a chip according to a fourth preferred embodiment of the present invention. 3D perspective view of the structure. FIG. 10 is a schematic top view corresponding to the structure of the inductive element in FIG. 9. FIG. 11 is a schematic cross-sectional view of a structure having an inductive element on a wafer according to a fifth preferred embodiment of the present invention. --------------------- Order -------! # · (Please read the note 3 on the back before filling out this page) Marking instructions printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs: 100: Wafer 101: Surface 102: Substrate 104: Element Layer 106: Laminate 108: Metal layer 7 This paper size applies the Chinese National Standard (CNS) A4 specification (2〗 〇χ 297mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 506045 5. & Invention no: Dielectric layer 112: Protective layer 130: Wide wire structure 114: External dielectric layer 116: Opening 210, 310: Inductive structure 212, 312: First surface 222, 322: First patterned circuit 214, 314Second surface 224 , 324: second patterned lines 230, 330: through holes 226, 326: insulating layers 118, 218, 318, 418: inductive elements 134: connecting points 150: seed layers 152: metal layers 136, 410: solder mask layers 122: Three-dimensional wide-line structure 124: Contact 126: Antimagnetic substance 350a, 350b, 350c, 350d: For a curve example, please refer to Figure 1, Figure 2, and Figure 3, which are shown in accordance with the paper size of this paper China National Standard (CNS) A4 Specification (2. 10 X 297 mm) ----------- I i 丨 丨 · — 丨 丨 Subscribe · 丨 —— 丨 · 丨 丨 丨 Line (Please read the precautions on the back before filling this page) 506045 A7 B7 6628twf.doc / 006 V. Description of the Invention () A schematic cross-sectional view of a manufacturing process of an inductor element structure on a wafer according to the first preferred embodiment. Please refer to FIG. 1 first. The wafer 100 is composed of a substrate 102, a device layer 104, a build-up layer 106, and a protective layer 112. The substrate 102, such as a Silicon Substrate commonly used in complementary metal-oxide-semiconductor (CMOS), has a surface 101. The element layer 104, which includes elements such as transistors, is disposed on the surface 101 of the substrate 102. The element layer 104 is further covered with a build-up layer 106, and the build-up layer 106 is interacted by at least one metal layer 108 and at least one dielectric layer Π0. The metal layer 108 includes a plurality of metal interconnects (not shown) to connect the element layer 104. The material of the metal interconnect is a material selected from the group consisting of aluminum, aluminum alloy, copper, copper alloy, and gold. Then, a protective layer 112 (Passivation) is covered on the build-up layer 106, and the protective layer 112 also has a plurality of contacts 124 in electrical communication with the metal interconnects (not shown). The protective layer 112 is covered with an external dielectric layer 114 (Post Passivation). The protective layer 112 is formed of nitrided or oxidized sand, and the material of the outer dielectric layer 114 includes polyimide, phenylcyclobutene, and the like. The coating is formed by curing. The polyimide after spin coating needs to be cured in a vacuum environment or a nitrogen atmosphere. The temperature is maintained between 250 and 400 degrees, and the time required is about 0.5 to For 1.5 hours, if the polyimide structure is thicker, it can be formed by a multi-layer spin coating method, a multi-laminating method, or a screen printing method. In the outer dielectric layer 114, a number of 9 papers are formed by means of lithographic etching. The paper size applies to the Chinese National Standard (CNS) A4 specification (210x 297 mm) --------------- ---- 丨 Order -------- · Line (Please read the precautions on the back before filling out this page) Printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs 506045 A7 B7 6628twf.doc / 006 V. Invention Explain (q) the openings 116, and then insert a conductive material into the openings 116 to form a wide wire structure 130, and define the deposition structure of this conductive material as the three-dimensional wide line structure 122, and the three-dimensional wide The circuit structure 122 is electrically connected to the plurality of contacts 124 of the protective layer 112, and the conductive material of the three-dimensional wide circuit structure 122 may include copper, gold, aluminum, nickel, tungsten, and the like. In addition, because of this, the conductors of the wide conductor structure are made. The line width (about tens of micrometers) is not as precise as the previous semiconductor manufacturing process (less than one micrometer), so low-cost processes can be used, such as electroplating and electroless plating, and sputtering can also be used. In addition, the thickness of the conductor of the wide conductor structure can be more than 3 microns, which can greatly reduce the signal attenuation or delay caused by the conductor. The thickness of the wide wire structure 130 may be between 20 microns and 100 microns. Please refer to FIG. 2. After the wide wire structure is manufactured, the manufacturing process of the inductive element is carried out. First, a sub-layer 150 is spread on the wide wire structure 130 by sputtering. The material of the seed layer 150 may It includes zinc, and then a metal layer 152 is deposited on the seed layer 150 by electroplating. Please refer to Fig. 3 and Fig. 4, wherein Fig. 4 shows a schematic plan view corresponding to the horizontal spiral inductor in Fig. 3. Next, the lithographic etching method is used to define at least one inductive element 118 and at least one external point 134. Finally, a solder mask layer 136 is applied to cover the inductive element 118 'and the external point 134 is exposed. Among them, the external point 134 and the inductive element 118 are electrically connected to the three-dimensional wide line structure 122, and the type of the inductive element 118 is a horizontal spiral (as shown in FIG. 4). The above configuration of the inductive element 118 can make the paper size of the inductive element 118 applicable to the Chinese National Standard (CNS) A4 specification (210x 297 mm) -----------, f ------ --Order --------- Line Ginseng (Please read the precautions on the back before filling this page) Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 506045 A7 B7 6628twf.doc / 006 V. Description of the invention ( X) Keep away from the substrate 102 made of silicon, and reduce the magnetic interference caused by the substrate 102 to the inductive element 118 to improve the performance of the chip. This structure is especially designed for passive components with high magnetic flux or high-frequency intercepted circuit design. Be efficient. In addition, since the inductive element 118 is disposed outside the wafer, a silicon wafer can be used instead of an expensive gallium arsenide (GaAs) wafer, which can reduce manufacturing costs. Please refer to FIG. 5, which is a schematic cross-sectional view of a structure having an inductive element on a wafer according to a second preferred embodiment of the present invention. Different from the above first preferred embodiment, in the second preferred embodiment of the present invention, the wide wire structure 130 further includes at least one antimagnetic substance I%, and the wide wire structure 130 exposes the antimagnetic substance 126, and The protective layer 112 is in contact, and the position of the antimagnetic substance 126 corresponds to the position of the inductive element us. The antimagnetic substance 126 is used to block the magnetic permeability effect of the inductive element U2 on the substrate 102 made of sand. Therefore, the present invention can be applied. Designed for passive components with higher magnetic flux or circuit designs designed to be cut at higher frequencies. The material of the antimagnetic substance 126 includes a metal or a magnetic substance. Please refer to FIG. 6, FIG. 7, and FIG. 8. FIG. 6 illustrates a perspective view of a JL body having an inductance element structure on a wafer according to a third preferred embodiment of the present invention, and FIG. 7 illustrates The plan view corresponding to the structure of the inductor element in FIG. 6 is not intended, and FIG. 8 is the plan view corresponding to the section line I-I in FIG. 7. In the aforementioned first preferred embodiment, the form of the inductor element is a horizontal spiral, but the form of the inductor element is not limited to the above-mentioned manner, and the inductor element 218 may be designed into a body spiral shape. An inductive structure 21 is composed of an insulating layer 226 and an inductive element ----- 丨 丨 丨-丨 S · 丨 丨! Customized --------- line (please read the note on the back? Matters before filling out this page) Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is printed in accordance with Chinese National Standard (CNS) A4 (210 x 297) (Public love) 506045 A7 B7 6628twf.doc / 006 V. Invention description (q) 218, and the inductor structure 210 has a first surface 212 and a second surface 214, and the inductor structure 210 is A watch® 212 is in contact with the wide wire structure 130, and the wide wire structure 130 is located on the protective layer 112 of the chip 100, and the thickness of the wide wire structure 130 is between 20 microns and 100 microns. The first surface 212 of the inductor structure 210 has a first patterned circuit 222 (as shown by the dashed line 222 in FIG. 7), and the second surface 214 of the inductor structure 210 has a second patterned circuit 224 (such as The solid line 224 in FIG. 7), and the conductive material in the through hole 230 can electrically connect the first patterned circuit 222 and the second patterned circuit 224 to form a three-dimensional spiral inductor element 218. ° And the manufacturing steps of the three-dimensional spiral inductor element 218 are firstly covered with a sub-layer on the wide conductor structure 130 by sputtering, and then a metal layer on the seed layer by electroplating. The engraving defines a first patterned line 222. Next, an insulating layer 226 is covered on the wide wire structure 130, and the first patterned circuit 222 is covered, and a plurality of through holes 230 are formed by lithography, and plated through holes (plate thrugh) are used. h〇le) into a conductive material in the through hole 230. Next, a sub-layer is sputter-coated on the insulating layer 216, a metal layer is electro-plated on the seed layer, and then a second patterned circuit 224 is defined by lithographic etching. In addition, a solder mask layer may be coated on the first surface 214 of the inductor structure 21, which is a structure known to those skilled in the art and will not be described again here. According to Figure 9 and Figure 10, Figure 9 shows a three-dimensional section of a chip with an inductive element structure on a wafer according to a fourth preferred embodiment of the present invention. 12 This paper size applies to Chinese National Standard (CNS) A4. Specifications (210x 297 mm) Please read B3 on the back of the page, and then fill out this page) -nn nnnnnn I l_i ϋ nnn -ϋ ϋ I-Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives, printed Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the employee consumer cooperative 506045 V. Description of the invention (丨 0) plane perspective diagram, in which only a part of the connection relationship between the first patterned line and the second patterned line is shown in FIG. 9, and FIG. 10 shows A schematic plan view corresponding to the structure of the inductor element in FIG. 9 is shown. In this embodiment, the inductive element 318 may also be designed in a ring-shaped three-dimensional spiral shape. An inductance structure 310 is composed of an insulation layer 326 and an inductance element 318. The insulation layer 326 covers the inductance element 318, and the inductance structure 310 has a first surface 312 and a corresponding second surface 314. The inductor structure 310 is in contact with the wide wire structure 130 with its first surface 312, and the wide wire structure 130 is located on the protective layer 112 of the chip 100, and the thickness of the wide wire structure 130 is between 20 microns and 1.0. 〇m. The first surface 312 of the inductor structure 310 has a first patterned circuit 322 (as shown by the dashed line 322 in FIG. 10), and the second surface 314 of the inductor structure 310 has a second patterned circuit 324 (such as The solid line 324 in FIG. 10), and the conductive material in the through hole 330 can electrically connect the first patterned circuit 322 and the second patterned circuit 324 to form a loop-shaped three-dimensional spiral inductor element. 318. In addition, the curves 350a, 350b, 350c, and 350d depict the approximate shape of the space region surrounded by the inductance element 318. The manufacturing process of the ring-shaped three-dimensional spiral inductor element 318 is the same as the process of the three-dimensional spiral-shaped inductor element in the third embodiment, except that the ring-shaped three-dimensional spiral inductor element 318 is in the shape of “_”, which will not be repeated here. The aforementioned inductive element is formed on the outside of the chip. Compared with the inductive element produced inside the chip, the lead wire of the inductive element of the present invention has a thicker wire and a wider line width, so it has better quality. In addition, compared with the three-dimensional inductance element produced inside the chip, the three-dimensional spiral 1 paper-like degree of the present invention (specification ⑵〇X 297 public love) ----------- 丨 ----- --- Order --------- Lines < Please read the notes on the back before filling this page) 506045 A7 B7 662Btwf.doc / 006 V. Description of the invention (丨 I) Shaped and circular three-dimensional spiral The height of the shaped inductor element is relatively high and it is far from the substrate, so it has better quality. Please refer to FIG. 11, which is a schematic cross-sectional view showing a structure of an inductive element on a wafer according to a fifth preferred embodiment of the present invention. In the aforementioned first preferred embodiment, the inductance element is laid on a wide wire structure. However, the configuration of the inductance element is not limited to the above-mentioned manner, and the inductance element 418 may be directly laid on the protective layer 112, and then Then, a solder mask layer 410 is applied to protect the inductive element 418. In this embodiment, a horizontal spiral inductor element is used as an example. However, this embodiment can also be applied to a three-dimensional spiral inductor element or a ring-shaped three-dimensional spiral inductor element, in which the three-dimensional spiral or ring-shaped three-dimensional spiral element is used. The thickness of the inductor structure is between 20 microns and 100 microns. In summary, the present invention has at least the following advantages: 1. The chip of the present invention has an inductive element structure, which can keep the inductive element away from the silicon substrate, so as to reduce the magnetic permeability interference caused by the silicon substrate to the inductive element and improve the efficiency of the chip. This structure is especially efficient for passive components with high magnetic flux or circuit designs designed to be cut at high frequencies. 2. The chip of the present invention has an inductive element structure, and an antimagnetic substance can be placed in the wide wire structure to block the substrate made of silicon as a material that has a magnetic permeability effect on the inductive element. This can be applied to higher magnetic flux Passive components or circuit designs designed to be cut at higher frequencies. 3. The chip of the present invention has an inductive element structure, and the inductive element can be arranged outside the chip, so a silicon-based wafer can be used instead of an expensive gallium arsenide (GaAs) wafer, which can reduce manufacturing cost. ----------------- Order ----!-Line (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ..., According to the Chinese national standard (€ 4 milk from 4 specifications (2) 0 > < 297 public love 506045 A7 6 62 8 twf · cioc / 〇〇6) 5. Description of the invention ((λ) 4 · The wafer of the present invention has Inductive element structure, because the inductive element is formed on the outside of the chip, compared with the inductive element produced inside the chip, the inductive element of the present invention has a thicker wire and a wider line width, so it has better quality. · The wafer of the present invention has an inductive element structure. Since the inductive element can be formed in an inductive structure body outside the wafer, it can have a three-dimensional spiral shape and a ring-shaped three-dimensional spiral shape of the inductive element structure. The three-dimensional inductive element of the present invention is relatively high in the three-dimensional spiral shape and the annular three-dimensional spiral shape of the present invention and is far away from the base, so it has better quality. Although the present invention has been disclosed above in the preferred embodiment, its Not intended to limit the hair It is clear that anyone skilled in this art can make various modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application. (Please read the notes on the back before filling in this page) Printed on the paper by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the paper size is applicable to China National Standard (CNS) A4 (21〇X 297g t)