JP2002076860A - Variable delay circuit, its setting method and semiconductor test device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid the effect caused by the sink phenomenon in the case of measuring the delay time of a variable delay circuit. SOLUTION: A circuit adopting the setting method of this invention is provided with a memory that stores the correlation between the combination of delay sections causing a delay time among delay sections 1a-1n and the delay time and is further provided with an offset section 10 that is connected in series with the delay sections and produces a delay time to shift the period of self- running loop oscillation to a period other than that in the vicinity of a multiple period when the period of the self-running loop oscillation is close to the multiple period of the operating period of surrounding electric circuits in the case of measuring the delay time by the combination of the delay sections in the self-running loop oscillation state in order to set the correlation to this memory.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for avoiding the influence of a suction phenomenon when measuring the delay amount of a variable delay circuit by a free-running oscillation loop method.

[0002]

2. Description of the Related Art A semiconductor test apparatus for performing an operation test of a semiconductor integrated circuit includes a variable delay circuit for synchronizing and extracting signals output from external terminals (pins) of a semiconductor integrated circuit to be inspected. It has.

Here, the configuration of a conventional variable delay circuit will be briefly described with reference to FIG. FIG. 4 is a circuit diagram for explaining the configuration of a conventional variable delay circuit. As shown in FIG. 4, the conventional variable delay circuit has an input terminal 2
N stages (n is an integer of 2 or more) between 0 and the output terminal 21
Of delay units 1a, 1b and 1n are connected in series.

[0004] The delay units 1a to 1n at each stage include a pass path 2 for passing a signal, delay paths 3a, 3b and 3n for delaying a signal, and a pass path 2 or a delay path 3a to 3n.
3n, and a selector 4 for selectively transmitting a signal to 3n. A gate element 3 is provided on each of the delay paths 3a to 3n. Then, each of the delay units 1a to 1a
1n makes the number of gate elements 3 different from each other, thereby causing different delay times for each delay unit.

Further, as shown in FIG. 4, the conventional variable delay circuit corresponds to a set delay time and a combination of delay units for transmitting signals to delay paths 3a to 3n among delay units 1a to 1n. A linearization memory 5 for storing the data is also provided. Therefore, by inputting a desired set delay time to the linearize memory 5, a combination of the delay units 1a to 1n corresponding to the set delay time can be obtained in the linearize memory 5.

The conventional variable delay circuit includes a pulse width shaping circuit 6 immediately after the n-th stage delay unit 1n. This pulse width shaping circuit 6 is, for example, as shown in FIG.
The circuit configuration shown in FIG. Then, according to this circuit configuration, when the input signal in is input, as shown in the timing chart of FIG. 5B, an inverted signal A and a delayed signal B thereof are generated. Then, a signal C is generated as an AND of the inverted signal A and the delayed signal B. Further, a first delay signal D and a second delay signal E of the signal C are generated.
And the OR of the signal C, the first and second delayed signals D and E
To generate the output signal out. By doing so, even when the pulse width of the output signal of the delay unit 1n at the n-th stage changes, an output signal having a constant pulse width can be output.

By the way, the delay time generated by the gate element 3 on the delay paths 3a to 3n of each of the delay units 1a to 1n is:
There is variation depending on the gate element 3. Therefore, in order to set the combination of the delay circuit and the delay time in the linearize memory 5 in association with each other, it is necessary to actually measure the delay time in each combination.

It is necessary to measure the delay time before using the variable delay circuit for the first time. further,
The delay time due to the gate element 3 varies depending on the environmental temperature. Therefore, even when the installation condition of the variable delay circuit changes, it may be necessary to measure the delay time again.

The measurement of the delay time is performed under a free-running loop oscillation state. Therefore, in the conventional variable delay circuit, a loop circuit for inputting a signal output from the output terminal 21 to the first-stage delay unit 1a is formed. Here, the signal output from the output terminal 21 is branched and taken out immediately before the output terminal 21, and is input to the first-stage delay unit 1a via the OR circuit 8 and the flip-flop 9.

The delay time in the free-running loop oscillation state can be accurately measured by measuring the free-running loop oscillation cycle (ie, the reciprocal of the frequency) using a frequency counter 7 provided on the loop circuit. . And the delay time measured in this way is
The data is stored in the linearization memory in association with the combination of the delay units when the delay time is generated.

The set values are given to the combinations of the delay units in ascending order of the delay time. When a desired delay time is input to the linearization memory 5, a set value corresponding to the measured delay time, which is closest to the delay time, is obtained. Then, depending on the set value, each of the delay units 1a to 1
n selectors 4 are respectively controlled, and each of the delay units 1a to 1
n, the passing path 2 or the delay paths 3a-3
n is selected.

[0012]

By the way, in a semiconductor inspection apparatus and other apparatuses, various circuits are usually provided around a variable delay circuit. These various circuits often include a circuit operating at a specific operating frequency. For example, a logic circuit operating at a specific clock frequency may be installed near the variable delay circuit.

When the frequency of the free-running loop oscillation when measuring the delay time of the variable delay circuit is close to the clock frequency of the logic circuit or a multiple thereof, the frequency of the free-running loop oscillation becomes equal to this clock frequency or a multiple thereof. A so-called suction phenomenon, which results in a numerical value, occurs.

Here, the suction phenomenon will be described with reference to FIG. FIG. 6 is a graph for explaining the suction phenomenon. The horizontal axis of this graph represents a set value, and the vertical axis represents a period during self-running loop oscillation. The solid line I in the graph represents the cycle of the free-running loop oscillation when the suction phenomenon occurs. Also, the broken line in the graph
II represents the cycle of the free-running loop oscillation when the suction phenomenon has not occurred.

In the example shown in FIG. 6, there is shown a case where a circuit such as a logic circuit operating at the period T0 or a multiple thereof is located near the variable delay circuit. In this case, a suction phenomenon occurs near the period T0. In other words, the self-running loop oscillation cycle originally indicated by the broken line II is shifted from the cycle T1 to the cycle T2 in the range of ΔT before and after the cycle T0 to become the cycle T0 as shown by the solid line I.

For this reason, for example, the measurement result in the case of the set value B is not the original free-running loop oscillation period t2 but the period T0. Also, for example, the measurement result in the case of the set value C is not the original free-running loop oscillation period t1, but
The period becomes T0. As described above, when the free-running loop oscillation cycle is shifted to the cycle T0, there is a problem that it is difficult to accurately measure the delay time.

When the self-running loop oscillation cycle is apart from the cycle T0, the suction phenomenon does not occur. For example, in the case of the set value A and the set value D, the original free-running loop oscillation cycle can be measured.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a variable delay circuit capable of avoiding the influence of a suction phenomenon in measuring the delay time of the variable delay circuit, and a method of setting the variable delay circuit. Aim.

[0019]

According to a first aspect of the present invention, there is provided a variable delay circuit comprising: a plurality of input terminals each having a different delay time between an input terminal and an output terminal; A stage delay unit is provided in series, and a memory for storing a combination of a delay unit that generates a delay time among the delay units and a correspondence with the delay time is provided. A variable delay circuit having a loop circuit for inputting to a delay unit.When a delay time due to a combination of the delay units is measured in a free-running loop oscillation state in order to set a correspondence with a memory, the free-running loop oscillation When the period is near a multiple period of the operation period of the electric circuit provided near the variable delay circuit, a delay time for shifting the period of the self-running loop oscillation to a period other than the vicinity of the multiple period is set. Cause The offset portion is a structure in which connected in series to the delay unit.

As described above, according to the variable delay circuit of the present invention, the cycle of the free-running loop oscillation is shifted by adding the delay time by the offset unit. For this reason,
The self-running loop oscillation can be performed while avoiding the cycle of the self-running loop oscillation in which the suction phenomenon occurs. As a result, the delay time can be obtained by measuring the cycle of the free-running loop oscillation without being affected by the suction phenomenon. Then, the delay time obtained by subtracting the delay time due to the offset unit is:
This is the delay time of the variable delay circuit.

According to the second aspect of the present invention, the offset section includes a pass path for passing a signal, a delay path for delaying a signal, and a selector for selectively transmitting a signal to the pass path or the delay path. It is constituted by. With such a configuration, a signal can be propagated through the delay path only when a delay time corresponding to the offset is added in order to avoid a suction phenomenon, and otherwise, a signal can be propagated through the pass path. Then, when used as a variable delay circuit, the signal can be propagated through the passing path of the offset unit.

According to the third aspect of the present invention, a plurality of delay paths are provided in the offset section. As described above, if a plurality of delay circuits of the offset unit are provided, the cycle of the free-running loop when the delay time due to one delay path of the offset unit is added overlaps with the cycle affected by the other suction phenomenon. In addition, by selecting another delay path of the offset section, the influence of the suction phenomenon can be avoided.

Further, according to the variable delay circuit setting method of the present invention, in a variable delay circuit in which a plurality of delay units are provided in series, a combination of the delay units is set in association with the delay time. In order to measure the delay time in the free-running loop oscillation state, when the free-running loop oscillation cycle is close to a multiple cycle of the operation cycle of the electric circuit provided near the variable delay circuit, the delay By connecting a delay path with a known time in series to the delay unit, the cycle of this free-running loop oscillation is shifted to a cycle other than the multiple cycle.

As described above, according to the variable delay circuit setting method of the present invention, the cycle of the free-running loop oscillation is shifted by adding a delay path. For this reason, the free-running loop oscillation can be performed while avoiding the cycle of the free-running loop oscillation in which the suction phenomenon occurs. As a result, the delay time can be obtained by measuring the cycle of the free-running loop oscillation without being affected by the suction phenomenon. Then, the delay time obtained by subtracting the delay time by the offset unit becomes the delay time of the variable delay circuit. Then, the determined delay time can be set in association with the combination of the delay units serving as the delay time.

According to a fifth aspect of the present invention, there is provided a semiconductor integrated circuit having a variable delay circuit for synchronizing and extracting signals output from respective external terminals of a semiconductor integrated circuit to be inspected. A variable delay circuit having a path for passing a signal and a path for delaying a signal between an input terminal and an output terminal, and different delay times from each other. And a memory for storing a combination of a combination of delay units for generating a delay time among the delay units and a delay time, and a signal output from an output terminal. Is provided to the first-stage delay unit, and when the delay time due to the combination of the delay units is measured in the free-running loop oscillation state, the self-running loop oscillation When the period is near a multiple period of the operation period of the electric circuit provided near the variable delay circuit, a delay time for shifting the period of the self-running loop oscillation to a period other than the vicinity of the multiple period is set. The offset section to be generated is provided in series with the delay section.

As described above, according to the semiconductor test apparatus of the present invention, the cycle of the free-running loop oscillation is shifted by adding the delay time by the offset section of the variable delay circuit. For this reason, the free-running loop oscillation can be performed while avoiding the cycle of the free-running loop oscillation in which the suction phenomenon occurs.
As a result, the delay time can be obtained by measuring the cycle of the free-running loop oscillation without being affected by the suction phenomenon. Then, the delay time obtained by subtracting the delay time by the offset unit becomes the delay time of the variable delay circuit. Then, the determined delay time can be set in association with the combination of the delay units serving as the delay time.

[0027]

Embodiments of the present invention will be described below with reference to the drawings. First, referring to FIG.
The configuration of the variable delay circuit according to the present embodiment will be described. This variable delay circuit is provided in a semiconductor inspection device (IC tester) in order to synchronously extract signals output from external terminals of a semiconductor integrated circuit to be inspected.

FIG. 1 is a circuit diagram for explaining the configuration of the variable delay circuit according to the present embodiment. In the variable delay circuit shown in FIG. 1, similarly to the conventional example, n stages (n is an integer of 2 or more) of delay units 1 are provided between an input terminal 20 and an output terminal 21.
a, 1b and 1n are connected in series and provided.

Further, the set delay time and each of the delay units 1a to 1
and a pulse width shaping circuit 6 for storing a combination of delay units for transmitting signals to the delay paths 3a to 3n of the n. further,
The variable delay circuit of the present embodiment also forms a loop circuit for inputting a signal output from the output terminal 21 to the first-stage delay unit 1a, similarly to the conventional example. Further, a frequency counter 7 for measuring the frequency of the free-running loop oscillation is provided.

When the frequency of the free-running loop oscillation is close to the clock frequency of the logic circuit or a multiple thereof, a suction phenomenon occurs as described above. Therefore, in the present embodiment, in order to avoid this suction phenomenon, the offset unit 1 connected in series to the delay units 1a to 1n.
0 is provided.

The offset unit 10 includes a passing path 12 for passing a signal and a first delay path 13 for delaying a signal.
It comprises a first and a second delay path 132 and a selector 14 for selectively transmitting a signal to a pass path, a first delay path or a second delay path. In the present embodiment, the first delay path 131 generates a delay time of, for example, 3 ns, and the second delay circuit 132 generates a delay time of, for example, 6 ns.

When the cycle of the free-running loop oscillation is close to a multiple cycle of the operation cycle of the electric circuit provided near the variable delay circuit, the selector 14 controls the first or the second of the offset section 10 by the selector 14. Two delay paths 131 or 13
Select 2. As a result, by adding a delay time, the cycle of the self-running loop oscillation can be shifted to a cycle other than the vicinity of a multiple cycle. Note that the delay time of the delay path of the offset unit 10 may be a delay time that does not coincide with an operation cycle causing a suction phenomenon and a multiple cycle thereof.

Next, referring to FIG.
The shift of the free-running loop oscillation period due to the above will be described.
The horizontal axis of the graph in FIG. 2 represents a set value, and the vertical axis represents a cycle during self-running loop oscillation. And the solid line I in the graph
Shows the relationship between the set value and the loop cycle when the signal is propagated to the passing path 12 in the offset unit 10. A solid line II in the graph indicates a relationship between a set value and a loop cycle when a signal is propagated to the first delay path 131 in the offset unit 10. The solid line III in the graph indicates the relationship between the set value and the loop period when the signal is propagated to the second delay path 132 in the offset unit 10.

In FIG. 2, the period T01 and the period T
At 02, a suction phenomenon has occurred. As such a cycle, a clock cycle of 4 near the variable delay circuit is used.
In the case where there is a logic circuit operating at ns, for example, 20 ns of the multiple period corresponds to the period T01, and
ns corresponds to the period T02. Therefore,
When measuring the self-running loop cycle, avoiding the vicinity of the cycle T01 and the cycle T02 in which the suction phenomenon occurs, as shown by the thick line IV in the graph of FIG. 2, the solid lines I, II, and II
Change I and measure.

In the example shown in FIG. 2, at first, the passing section 12 is selected in the offset section 10, and the self-running loop oscillation period on the solid line I is measured. For example, for the set value A, the period is measured on the solid line I. Then, when the period becomes longer on the solid line I, the solid line I approaches the period T02. Therefore, in order to avoid the influence of the suction phenomenon, the cycle is shifted at the set value B. For the set value B, the solid line
Since II is near the period T01, it is shifted on the solid line III. In this case, in the offset unit 10, the selector 14 selects the second delay path 132 and propagates the signal to the second delay path 132. As a result, for example,
At the set value C, an accurate period can be measured on the solid line III.

Further, when the period becomes longer on the solid line III,
The solid line III approaches the period T01. Therefore, in order to avoid the influence of the suction phenomenon, the cycle is shifted again to the solid line II at the set value D. In this case, the selector 14 selects the first delay path 131 in the offset unit 10 and propagates the signal to the first delay path 131. As a result, for example, for the set value E, an accurate period can be measured on the solid line II. In this case, the cycle of the set value D may be shifted to the solid line I.

Further, when the period becomes longer on the solid line II, the solid line II approaches the period T02. Therefore, in order to avoid the influence of the suction phenomenon, the cycle is shifted to the solid line I again at the set value F. In this case, the selector 14 selects the passing path 12 in the offset unit 10 and propagates the signal to the passing path 12. As a result, for example, for the set value G, an accurate period can be measured on the solid line I.

The delay times measured in this way are stored in the linearization memory in ascending order of the delay time in association with the combination of the delay units that caused the delay time. At this time, the delay time obtained by subtracting the delay time by the offset unit becomes the delay time of the variable delay circuit.
Then, a set value is given to the combination of the delay units in ascending order of the delay time, and the set time and the combination of the delay units are set.

As a result, when a desired delay time is input to the linearization memory 5, a set value corresponding to the measured delay time, which is closest to the delay time, is obtained. And
Depending on the set value, the selector 4 of each of the delay units 1a to 1n
Are respectively controlled, and the passing path 2 or the delay paths 3a to 3n are selected in the respective delay units 1a to 1n.

The method of selecting a delay path by the offset unit for avoiding the suction phenomenon is not limited to the example shown by the thick line IV in FIG. For example, it can be shifted as shown in FIG. In the graph of FIG. 3, similarly to the graph of FIG. 2, the horizontal axis represents the set value, and the vertical axis represents the cycle at the time of self-running loop oscillation.

The solid line I in the graph indicates the relationship between the set value and the loop period when the signal is propagated through the passing path 12 in the offset unit 10. A solid line II in the graph indicates a relationship between a set value and a loop cycle when a signal is propagated to the first delay path 131 in the offset unit 10. The solid line III in the graph indicates the relationship between the set value and the loop period when the signal is propagated to the second delay path 132 in the offset unit 10.

However, in the example shown in FIG. 3, the delay time of the first delay path 131 is 1 ns, and the second delay path 13
2 is 2 ns. In other words, the delay maintenance interval added by the offset unit 10 is set to a period sufficiently shorter than the interval (for example, 4 ns) of a multiple period of the operation period.

In FIG. 3, as indicated by the thick line IV,
When the self-running loop period approaches the period T01 in which the suction phenomenon occurs, the frequency is sequentially shifted to the solid line I, the solid line II, and the solid line III to avoid the influence of the suction phenomenon.
That is, the frequency is shifted from the solid line I to the solid line II in the portion indicated by A in FIG. 3, and further, in the portion indicated by B in FIG.
The frequency is shifted from solid line II to solid line III. Such shifting can also avoid the influence of the suction phenomenon.

In the above-described embodiment, an example has been described in which the present invention is configured under specific conditions. However, the present invention can be variously modified. For example, in the above-described embodiment, an example in which the offset unit 10 is provided between the input terminal 20 and the output terminal 21 has been described. However, in the present invention, after branching before the output terminal 21, the OR circuit 8 An offset unit 10 may be provided on the loop circuit until input.

[0045]

As described above, according to the present invention, the period of the free-running loop oscillation is shifted by adding a delay path. For this reason, the free-running loop oscillation can be performed while avoiding the cycle of the free-running loop oscillation in which the suction phenomenon occurs. As a result, the delay time can be obtained by measuring the cycle of the free-running loop oscillation without being affected by the suction phenomenon. Then, the delay time obtained by subtracting the delay time by the offset unit becomes the delay time of the variable delay circuit. Then, the determined delay time can be set in association with the combination of the delay units serving as the delay time.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a configuration of a timing correction circuit according to an embodiment.

FIG. 2 is a graph for explaining an example of switching of an offset in the embodiment.

FIG. 3 is a graph for explaining another example of offset switching in the embodiment.

FIG. 4 is a circuit diagram illustrating a configuration of a conventional timing correction circuit.

FIG. 5A is a circuit diagram for explaining a pulse width shaping circuit constituting a conventional timing correction circuit;
(B) is a timing chart for explaining the operation of the pulse width shaping circuit.

FIG. 6 is a graph for explaining a suction phenomenon in a conventional timing correction circuit.

[Explanation of symbols]

 1a, 1b, 1n Delay section 2 Passing path 3 Gate 3a, 3b, 3n Delay path 4 Selector 5 Linearize memory 6 Pulse width shaping circuit 7 Frequency counter 8 OR gate 9 Flip-flop 10 Offset section 12 Passing path 14 Selector 20 Input terminal 21 output terminal 131 first delay path 132 second delay path

Claims (5)

[Claims] An input terminal and an output terminal each have a path for passing a signal and a path for delaying a signal,
A plurality of delay units for generating delay times different from each other are provided in series, and a memory for storing a correspondence between a combination of delay units for generating delay time among the delay units and a delay time is provided; A variable delay circuit comprising a loop circuit for inputting a signal output from the first stage to a first-stage delay unit, wherein the self-propelled loop includes a delay time by a combination of the delay units in order to set the association in the memory. When measuring in an oscillation state, if the cycle of the free-running loop oscillation is close to a multiple cycle of the operation cycle of an electric circuit provided near the variable delay circuit, the cycle of the free-running loop oscillation is A variable delay circuit, comprising: an offset unit for generating a delay time for shifting to a period other than the multiple period, in series with the delay unit. 2. The apparatus according to claim 1, wherein the offset unit includes a pass path for passing a signal, a delay path for delaying a signal, and a selector for selectively propagating a signal to the pass path or the delay path. The variable delay circuit according to claim 1. 3. The variable delay circuit according to claim 2, wherein a plurality of said delay paths in said offset section are provided. 4. In a variable delay circuit having a plurality of delay units connected in series, a delay time is measured in a free-running loop oscillation state in order to set a combination of delay units and a delay time in association with each other. When the cycle of the free-running loop oscillation is close to a multiple cycle of the operation cycle of the electric circuit provided near the variable delay circuit, a delay path with a known delay time is connected in series to the delay unit. , The cycle of this self-running loop oscillation
A method of setting a variable delay circuit, wherein the variable delay circuit is shifted to a period other than the vicinity of the multiple period. 5. A semiconductor test apparatus for performing an operation test of a semiconductor integrated circuit, comprising a variable delay circuit for synchronously extracting signals output from respective external terminals of a semiconductor integrated circuit to be inspected. The variable delay circuit has a path for passing a signal and a path for delaying a signal between an input terminal and an output terminal, and a plurality of delay units that generate different delay times are serially connected. A memory that stores a combination of a delay unit that generates a delay time among the delay units and a correspondence with the delay time, and inputs a signal output from the output terminal to the first-stage delay unit A loop circuit for setting the association in the memory, when measuring the delay time due to the combination of the delay units in a free running loop oscillation state, the cycle of the free running loop oscillation is variable. When the cycle of the free-running loop oscillation is near a multiple cycle of the operation cycle of the electric circuit provided near the extension circuit, an offset causing a delay time for shifting the cycle of the free-running loop oscillation to a cycle other than the multiple cycle. A semiconductor testing device, wherein a section is provided in series with the delay section.