JP3633605B2 - Semiconductor device and speed selection method used therefor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a speed selection method used therefor , and more particularly, to a speed selection method for an LSI (Large Scale Integrated circuit).
[0002]
[Prior art]
In recent years, the clock frequency of LSIs has increased with an acceleration, and is about to exceed 1 GHz. On the other hand, LSI testers that measure LSIs can no longer measure at the normal clock frequency of LSIs. In addition to the reason that it cannot be measured in terms of performance, there is a need to reduce the cost of LSI testing, and in many cases, an inexpensive and low-performance LSI tester is used.
[0003]
In general, the measurement by the LSI tester is a defect selection by an operation check at a low frequency, and an AC speed selection is not performed. Here, the speed is an operable frequency of the LSI. Further, testing the operable frequency and selecting the LSI is hereinafter referred to as speed selection. In LSI, the speed of gate elements and the like may vary greatly due to slight manufacturing errors in the manufacturing process. Therefore, speed selection is required for LSIs aiming at high-spec performance as described above.
[0004]
Speed selection is performed separately, and the first method is to test in the same environment as the situation where LSI is actually used. Measurement is performed by mounting on a printed circuit board or a computer device.
[0005]
In the second method, the LSI speed itself is not actually measured, but the overall LSI performance is estimated from the correlated circuit performance. This method can also be measured at the LSI tester level.
[0006]
In general, as shown in FIG. 4, frequency measurement of a ring oscillator in which odd-numbered NAND circuits 31 to 3n [n = 2m + 1] are connected on a ring is used for the estimation. By measuring the oscillation frequency of this ring oscillator, the speed of the gate element per stage can be measured. The operating frequency of the LSI is estimated from this value.
[0007]
[Problems to be solved by the invention]
In the conventional LSI speed selection method described above, in the case of the first method, the cost of assembling the LSI into a package for mounting is first generated, so that the assembly cost of the LSI that has become defective in the speed selection is wasted.
[0008]
In addition, there is a cost in preparing the evaluation environment for equipment and printed circuit boards, and there are also costs for using the measuring equipment and labor costs, which are ultimately reflected in the price of LSIs and equipment. Becomes higher.
[0009]
On the other hand, the problem with the second method is that the frequency of the ring oscillator and the LSI performance cannot be completely correlated. LSI performance is almost determined by a delay between specific circuits called a critical path. When the gate elements (inverters, NAND circuits, etc.) constituting the critical path are dispersed in the LSI, the gate elements are connected by a long wiring.
[0010]
In contrast, ring oscillators are often configured with almost no wiring due to size restrictions and the like. In a microfabrication manufacturing process commonly referred to as a 0.18 um / 0.15 um rule, the delay of wiring has become a value that cannot be ignored compared with the delay of a gate element.
[0011]
Therefore, the correlation between the gate element delay calculated from the ring oscillator frequency measurement and the critical path delay cannot be said to be highly accurate. It is also difficult to design a ring oscillator to increase accuracy.
[0012]
Accordingly, an object of the present invention is to provide a semiconductor device that can solve the above-described problems and can examine the performance of an LSI at the LSI tester level and a speed selection method used therefor.
[0013]
[Means for Solving the Problems]
A semiconductor device according to the present invention is a semiconductor device including first and second semiconductor integrated circuits connected to each other via a transmission line, and includes an input buffer that holds an output from the transmission line, A signal line for negatively feeding back an output to the transmission line; and a selector for selecting one of a signal on the signal line and an input signal to the transmission line and outputting the selected signal to the transmission line. In one of the semiconductor integrated circuits,
An input buffer that holds an output from the transmission line, and a selector that selects one of the output of the input buffer and an input signal to the transmission line and outputs the selected signal to the transmission line. In the other of the semiconductor integrated circuits,
The first and second flip-flops are arranged on the input side and the output side of the transmission line, respectively, and a common clock signal applied to each of them is set so as to pass through the input signal during the operable frequency test. ,
The output of one input buffer of the first and second semiconductor integrated circuits is negatively fed back to the other of the first and second semiconductor integrated circuits via the transmission path to form a ring oscillator. ing.
[0014]
That is, the semiconductor integrated circuit of the present invention is characterized in that a ring oscillator is configured using a critical path. Measuring the oscillation frequency of the critical path / ring oscillator from the outside is as easy as measuring a normal ring oscillator, and the speed of the circuit can be easily calculated from the measurement of the frequency.
[0015]
Moreover, the circuit is a critical path that determines the performance of the entire LSI, and the performance can be measured with high accuracy. This makes it possible to examine the performance of the LSI at the LSI tester level. When the distance between the first flip-flop and the second flip-flop is long, the minimum necessary number of relay buffers are inserted into the signal FB, but the performance delay caused by the insertion of this circuit into the critical path Must be very small and negligible.
[0016]
A high-performance / expensive LSI tester is not required for measurement, and only a frequency counter is required. Further, since it can be measured even at a wafer test at the LSI tester level, it is not necessary to assemble a package with a defective speed, and it is not necessary to select on the apparatus, so that it is possible to further reduce the cost. Therefore, it is possible to provide a means that enables LSI speed selection at the LSI tester level.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to an embodiment of the present invention. 1, a semiconductor integrated circuit according to an embodiment of the present invention includes a logic circuit (logic) 3 constituting a critical path in an LSI, and flip-flop circuits (hereinafter referred to as F / F) 2 before and after the logic circuit 3. , 4, a signal wiring FB for negative feedback from the output of F / F 4 to the input of F / F 2, and a selector (SEL) 1. The F / Fs 2 and 4 are constituted by flip-flops of a type having two layers of scan clocks SC1 and SC2, and a common clock CLK is applied to each of them.
[0018]
The operation of the semiconductor integrated circuit according to one embodiment of the present invention will be described with reference to FIG. Here, portions other than the dotted line portion in FIG. 1 are normal logic circuits, and represent signal paths called critical paths that determine the performance of the LSI. A dotted line portion is a circuit added in one embodiment of the present invention, and the circuit is configured to be inserted into a critical path.
[0019]
One embodiment of the present invention targets speed sorting. The operation during the test will be described below. First, an appropriate level is given to the signal EN so that the input of the selector 1 selects the signal FB.
[0020]
The two-phase scan clocks SC1 and SC2 of F / F2 and 4 are set so that F / F2 and 4 are through. As the F / Fs 2 and 4 operating with the two-phase scan clocks SC1 and SC2, for example, LSSD (level sensitive scan design) is known.
[0021]
Thus, by setting the F / F 2 and 4 to be through, the signal passes through from F / F 2 to F / F 4 in the above circuit. Furthermore, by negatively feeding back the output of F / F4 to F / F2 via signal FB, it becomes possible to form a ring oscillator configuration with a critical path (hereinafter referred to as a critical path / ring oscillator). .
[0022]
In this case, the logic in the ring needs to be inverted logic (indicated in FIG. 1 by marking the output part of F / F4 with a circle). This critical path / ring oscillator oscillates by itself.
[0023]
For tests other than speed selection and normal operation, an appropriate level is given to the signal EN, and the selector 1 is switched so as to select the input side, thereby providing a negative feedback path in which the output of the F / F4 is negatively fed back to the F / F2. Cut.
[0024]
Since it is possible to measure the oscillation frequency of the critical path ring oscillator from the outside as easily as the normal ring oscillator measurement, it is also possible to easily calculate the speed of the circuit from the frequency measurement. Moreover, the circuit is a critical path that determines the performance of the entire LSI, and the performance can be measured with high accuracy.
[0025]
This makes it possible to examine the performance of the LSI at the LSI tester level. When the distance between F / F2 and F / F4 is long, a relay buffer is inserted into the signal FB as much as necessary, but the performance delay caused by the insertion of this circuit to the critical path is extremely small. Need to be in a range that can be ignored.
[0026]
Therefore, a high-performance / expensive LSI tester is not required for measurement, and only a frequency counter is required. Further, since it can be measured even at a wafer test at the LSI tester level, it is not necessary to assemble a package with a defective speed, and it is not necessary to select on the apparatus, so that further cost reduction can be achieved.
[0027]
FIG. 2 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to another embodiment of the present invention. In FIG. 2, the semiconductor integrated circuit according to another embodiment of the present invention has substantially the same configuration as that of the semiconductor integrated circuit according to one embodiment of the present invention shown in FIG. 1, but the clocks CLK1 and F / F6 that tap F / F5 are used. Is different from the clock CLK2 in that it is a multi-layer clock. Even between different-phase clocks, the frequency can be measured with a circuit similar to the semiconductor integrated circuit according to the embodiment of the present invention.
[0028]
FIG. 3 is a circuit diagram showing a configuration of a semiconductor device according to another embodiment of the present invention. In FIG. 3, a semiconductor device according to another embodiment of the present invention is obtained by extending another embodiment of the present invention between LSIs.
[0029]
That is, an LSI 1 including the selector 11, F / Fs 12 and 15, the output buffer 13 and the input buffer 14, and an LSI 2 including the selector 23, F / Fs 22 and 24, the output buffer 25, and the input buffer 21 are connected between the LSIs. Another embodiment of the present invention is applied to the configuration connected at 101 and 102.
[0030]
In this case, the measurement target is not a critical path but an inter-LSI line (inter-LSI transmission paths 101 and 102). Since it is necessary to prepare an input / output buffer for the return path, as shown in FIG. 3, if the circuit configurations of the forward path and the return path are the same, the transmission delay on one side is simply calculated as 1/2 of the round trip. be able to.
[0031]
Of course, in the case of delay measurement of transmission between LSIs, it cannot be measured at the LSI tester level, and the measurement at the time of mounting on a printed board is different from the above. In other words, the delay between LSIs can also be measured.
[0032]
【The invention's effect】
As described above, according to the present invention, in a semiconductor integrated circuit including a critical path representing a signal path, a ring oscillator is configured using the critical path, thereby checking the LSI performance at the LSI tester level. There is an effect that can be.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to an embodiment of the present invention.
FIG. 2 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to another embodiment of the present invention.
FIG. 3 is a circuit diagram showing a configuration of a semiconductor device according to another embodiment of the present invention.
FIG. 4 is a circuit diagram showing a configuration of a ring oscillator according to a conventional example.
[Explanation of symbols]
1,11,23 selectors 2,4,12,15,
22, 24 Flip-flop 3 Logic circuit 13, 25 Output buffer 14, 21 Input buffer 101, 102 Transmission path between LSIs

Claims (6)

A semiconductor device including first and second semiconductor integrated circuits connected to each other via a transmission line, an input buffer for holding an output from the transmission line, and an output of the input buffer to the transmission line Of the first and second semiconductor integrated circuits, a signal line to be fed back and a selector for selecting one of the signal on the signal line and an input signal to the transmission path and outputting the selected signal to the transmission path On one side,
An input buffer that holds an output from the transmission line, and a selector that selects one of the output of the input buffer and an input signal to the transmission line and outputs the selected signal to the transmission line. The other of the semiconductor integrated circuits,
The first and second flip-flops are arranged on the input side and the output side of the transmission line, respectively, and a common clock signal applied to each of them is set so as to pass through the input signal during the operable frequency test. ,
The output of one input buffer of the first and second semiconductor integrated circuits is negatively fed back to the other of the first and second semiconductor integrated circuits via the transmission path to form a ring oscillator. A semiconductor device. A semiconductor device including first and second semiconductor integrated circuits connected to each other via a transmission line, an input buffer for holding an output from the transmission line, and an output of the input buffer to the transmission line Of the first and second semiconductor integrated circuits, a signal line to be fed back and a selector for selecting one of the signal on the signal line and an input signal to the transmission path and outputting the selected signal to the transmission path On one side,
An input buffer that holds an output from the transmission line, and a selector that selects one of the output of the input buffer and an input signal to the transmission line and outputs the selected signal to the transmission line. The other of the semiconductor integrated circuits,
The first and second flip-flops are arranged on the input side and the output side of the transmission line, respectively, and are set with independent clock signals applied to the input signals so that the input signals pass through during the operable frequency test. ,
The output of one input buffer of the first and second semiconductor integrated circuits is negatively fed back to the other of the first and second semiconductor integrated circuits via the transmission path to form a ring oscillator. A semiconductor device. 3. The semiconductor device according to claim 1 , wherein the signal line is configured to negatively feed back the output of the second flip-flop to the first flip-flop. A speed selection method for a semiconductor device comprising first and second semiconductor integrated circuits connected to each other via a transmission line,
In one of the first and second semiconductor integrated circuits, the output of the input buffer that holds the output from the transmission path is negatively fed back to the transmission path through a signal line, and the signal on the signal line and the transmission path Select one of the input signals to the selector and output to the transmission line,
In the other of the first and second semiconductor integrated circuits, one of the output of the input buffer holding the output from the transmission path and the input signal to the transmission path is selected by a selector and the transmission is performed. Output to the road,
The output of one input buffer of the first and second semiconductor integrated circuits is negatively fed back to the other of the first and second semiconductor integrated circuits via the transmission path to form a ring oscillator. ,
The semiconductor devices are arranged on the input side and the output side of the transmission line, respectively, and a common clock signal applied to each is set so as to pass through the input signal during an operable frequency test. Speed selection method characterized by comprising flip-flops . A speed selection method for a semiconductor device comprising first and second semiconductor integrated circuits connected to each other via a transmission line,
In one of the first and second semiconductor integrated circuits, the output of the input buffer that holds the output from the transmission path is negatively fed back to the transmission path through a signal line, and the signal on the signal line and the transmission path Select one of the input signals to the selector and output to the transmission line,
In the other of the first and second semiconductor integrated circuits, one of the output of the input buffer holding the output from the transmission path and the input signal to the transmission path is selected by a selector and the transmission is performed. Output to the road,
The output of one input buffer of the first and second semiconductor integrated circuits is negatively fed back to the other of the first and second semiconductor integrated circuits via the transmission path to form a ring oscillator. ,
The semiconductor devices are arranged on the input side and the output side of the transmission line, respectively, and a common clock signal applied to each is set so as to pass through the input signal during an operable frequency test. Speed selection method characterized by comprising flip-flops . 6. The speed selection method according to claim 4, wherein the signal line negatively feeds back the output of the second flip-flop to the first flip-flop.

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