JP2002076206A - Flip-chip coupled package - Google Patents

Flip-chip coupled package

Info

Publication number
JP2002076206A
JP2002076206A JP2001036918A JP2001036918A JP2002076206A JP 2002076206 A JP2002076206 A JP 2002076206A JP 2001036918 A JP2001036918 A JP 2001036918A JP 2001036918 A JP2001036918 A JP 2001036918A JP 2002076206 A JP2002076206 A JP 2002076206A
Authority
JP
Japan
Prior art keywords
chip
flip
heat
module
epoxy resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001036918A
Other languages
Japanese (ja)
Inventor
Wen-Lo Hsien
文樂 謝
Eisei So
永成 莊
▲寧▼ ▲黄▼
Ning Huang
Hui Pin Chen
▲慧▼萍 陳
華文 ▲蒋▼
Hua Wen Chiang
Chang Chuang Ming
衷銘 張
豐昌 ▲徐▼
Hosho Jo
富裕 ▲黄▼
Fu Yu Huang
Chang Hsuan Jui
軒睿 張
Hu Chia Chieh
嘉傑 胡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Orient Semiconductor Electronics Ltd
Original Assignee
Orient Semiconductor Electronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Orient Semiconductor Electronics Ltd filed Critical Orient Semiconductor Electronics Ltd
Publication of JP2002076206A publication Critical patent/JP2002076206A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a flip-chip coupled package that greatly saves manufacturing time, increases the heat transfer effect of a chip module, and is made of a single material. SOLUTION: A flip-chip coupled module 1 is coupled onto a substrate 11, where a tin ball 111 is provided by a flip-chip package system. In the structure, a filler 31 completely covers a projection 211. Then, the entire flip-chip coupled module 1 covered completely with an epoxy resin 41 where a high-heat- conduction and high-conductivity particle constituent such as copper, gold, aluminum, and silver is added. The epoxy resin 41 is brought directly into contact with a chip 21, thus shortening a heat conduction path, and increasing a heat exhaust function. The flip-chip coupled module 1 can be machined in a machining basis state, thus saving process and time for moving and changing a production line.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、フリップチップ結
合パッケージに関する。The present invention relates to a flip-chip bonded package.

【０００２】[0002]

【従来の技術】現在の新世代のパッケージング技術にお
いて、フリップチップ結合は主流であり、かつ多くはフ
リップチップ結合技術の組合せ応用から各種ハイレベル
のパッケージ法に浸透している。フリップチップ結合パ
ッケージの排熱構造は一般に図１Ａに示すように、その
フリップチップ結合モジュール１’の基板１１’下側に
は若干の錫ボール（ｓｏｌｄｅｒ ｂａｌｌ）１１１’
が設けられている。基板１１’の上側はフリップチップ
パッケージ（１３’充填剤、１２１’突起、１２’チッ
プ）であり、排熱構造はチップ１２’の上側と、底部に
排熱剤および接着剤１４’を塗布し、底縁の接触面に排
熱剤および接着剤１４’を塗布した上蓋排熱板１６’を
接着して形成されている。2. Description of the Related Art In the current new generation of packaging technology, flip-chip bonding is the mainstream, and in many cases, the combination of flip-chip bonding technology has penetrated various high-level packaging methods. Generally, as shown in FIG. 1A, the heat dissipation structure of the flip-chip bonding package includes a small tin ball 111 'on the underside of the substrate 11' of the flip-chip bonding module 1 '.
Is provided. The upper side of the substrate 11 'is a flip chip package (13' filler, 121 'projection, 12' chip), and the heat dissipation structure is formed by applying a heat dissipation agent and an adhesive 14 'to the upper side and the bottom of the chip 12'. The upper cover heat-dissipating plate 16 'coated with a heat-dissipating agent and an adhesive 14' is adhered to the contact surface of the bottom edge.

【０００３】もう一種の従来のフリップチップ結合モジ
ュール２’は図１Ｂに示すように、基板２１’の上側は
フリップチップパッケージ（２３’充填剤、２２１’突
起、２２’チップ）であり、排熱構造はチップ２２’の
周囲に高い排熱枠２７１’を設け、かつその排熱枠２７
１’の頂上面は平板形の排熱板２７’で覆い被され、熱
源の排熱効果を高めている。平板形排熱板２７’とチッ
プ２２’の接触面には排熱剤および接着剤２４’が塗布
され、平板形排熱板２７’と排熱枠２７１’の間には排
熱剤および接着剤２５’が塗布され、排熱枠２７１’と
基板の間には排熱剤および接着剤２６’が塗布されて平
板形排熱板２７’を固定している。As shown in FIG. 1B, another conventional flip-chip bonding module 2 'is a flip-chip package (23' filler, 221 'protrusion, 22' chip) on the upper side of a substrate 21 ', and heat is discharged. The structure is such that a high heat dissipation frame 271 'is provided around the chip 22' and the heat dissipation frame 27
The top surface of 1 'is covered with a flat heat-dissipating plate 27' to enhance the heat-dissipating effect of the heat source. A heat-dissipating agent and an adhesive 24 ′ are applied to the contact surface between the flat heat-dissipating plate 27 ′ and the chip 22 ′, and the heat-dissipating agent and the adhesive are applied between the flat heat-dissipating plate 27 ′ and the heat-dissipating frame 271 ′. An agent 25 'is applied, and a heat-dissipating agent and an adhesive 26' are applied between the heat-dissipating frame 271 'and the substrate to fix the flat heat-dissipating plate 27'.

【０００４】また、もう一種の従来のフリップチップ接
合モジュール３’に応用されている排熱構造は図１Ｃに
示すように、基板３１’の上側はフリップチップパッケ
ージ（３３’充填剤、３２１’突起、３２’チップ）で
あり、排熱構造はチップ３２’の頂上面に排熱板３５’
を覆い被せ、排熱板３５’の固定およびチップ３２’の
熱の排出のために、排熱板３５’とチップ３２’の接触
面に排熱剤３４’が塗布されている。Further, as shown in FIG. 1C, a heat-dissipating structure applied to another type of conventional flip-chip bonding module 3 'has a flip-chip package (33' filler, 321 'protrusion) on the upper side of a substrate 31'. , 32 ′ chip), and the heat-dissipating structure is a heat-dissipating plate 35 ′
A heat-dissipating agent 34 'is applied to the contact surface between the heat-dissipating plate 35' and the chip 32 'for fixing the heat-dissipating plate 35' and discharging the heat of the chips 32 '.

【０００５】[0005]

【発明が解決しようとする課題】しかしながら、上述各
種従来のフリップチップ結合モジュールの排熱構造によ
り排熱効果を得ることはできるが、この排熱構造の形式
は元の基礎をそのまま使用して加工することができず、
そのためにモジュール全体を別の生産ラインへ移して作
業するため、製造過程が複雑になってしまう。排熱板の
熱伝導は主としてチップと排熱板間の排熱剤によって行
われ、排熱板とチップが接触していないためチップの熱
は迅速に排熱板に伝達されず、排熱効果に影響が出る。
また、排熱板とチップの間は排熱接着剤により固定さ
れ、排熱板と排熱板の間にも排熱接着剤が使用されてい
る場合がある。排熱構造は数種類の熱膨脹係数の違う材
料から構成されるので、チップは高温において各材料の
伸びが異なり、結合上の問題が発生する。However, the above-described various types of conventional flip-chip bonded modules can provide a heat-dissipating effect by the heat-dissipating structure. Can not do
Therefore, since the entire module is moved to another production line for work, the manufacturing process becomes complicated. The heat conduction of the heat-dissipating plate is mainly performed by the heat-dissipating agent between the chip and the heat-dissipating plate. Since the heat-dissipating plate and the chip are not in contact, the heat of the chips is not quickly transferred to the heat-dissipating plate, and the heat-dissipating effect is obtained. Is affected.
In some cases, the heat-dissipating adhesive is fixed between the heat-dissipating plate and the chip, and the heat-dissipating adhesive is also used between the heat-dissipating plates. Since the heat-dissipating structure is composed of several kinds of materials having different thermal expansion coefficients, the chips have different elongations at high temperatures, which causes a bonding problem.

【０００６】したがって本発明の目的は、元の基礎状態
のままモルディング可能で、移動する必要が無く、製造
の時間を大幅に節約することができるフリップチップ結
合パッケージを提供することにある。本発明の次の目的
は、チップモジュールの伝熱効果を高めることが可能な
フリップチップ結合パッケージを提供することにある。
本発明の更にひとつの目的は、違う材料が高熱を受けた
ときの違う膨脹係数による伸縮から発生する結合および
応力上の問題を完全に避けることができる単一材料によ
るフリップチップ結合パッケージを提供することにあ
る。Accordingly, it is an object of the present invention to provide a flip-chip bonded package which can be molded in its original base state, does not need to be moved, and can save a lot of manufacturing time. It is another object of the present invention to provide a flip chip bonding package capable of enhancing the heat transfer effect of a chip module.
It is a further object of the present invention to provide a single material flip chip bonding package that can completely avoid bonding and stress problems arising from expansion and contraction due to different coefficients of expansion when different materials are subjected to high heat. It is in.

【０００７】[0007]

【課題を解決するための手段】上述の課題を解決するた
めに、本発明の請求項に記載のフリップチップ結合パッ
ケージは、主として高伝熱および高導電性粒子例えば銅
と銀、アルミニウムを添加した熱伝導特性に優れたエポ
キシーレジンを採用し、フリップチップ結合モジュール
の全体構造を覆い被せる。SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, a flip-chip bonded package according to the present invention is mainly provided with high heat transfer and high conductive particles such as copper, silver and aluminum. Employs an epoxy resin with excellent heat conduction characteristics to cover the entire structure of the flip chip bonding module.

【０００８】フリップチップ結合モジュールは、錫ボー
ルを有する基板上の所定位置にフリップチップ形式によ
り、突起でチップと基板を結合させている。その構造
は、充填接着剤により突起を完全に覆い被せ、つづいて
高熱伝導および高導電性粒子を含むエポキシーレジンに
よりフリップチップ結合モジュール全体を包覆する。エ
ポキシーレジンとチップとの直接接触によって伝熱経路
を短縮し排熱機能を高めることが可能となる。[0008] In the flip chip bonding module, the chip and the substrate are bonded to each other at predetermined positions on the substrate having tin balls by using a flip chip method by using projections. The structure completely covers the protrusions with a filling adhesive, and then covers the entire flip-chip bonding module with an epoxy-resin containing high thermal and highly conductive particles. The direct contact between the epoxy resin and the chip shortens the heat transfer path and enhances the heat removal function.

【０００９】[0009]

【発明の実施の形態】以下、本発明の実施例を図面に基
づいて説明する。図２に示すように本発明の一実施例に
よるフリップチップ結合パッケージは、主としてフリッ
プチップ結合されたモジュールにおいて、エポキシーレ
ジンでモジュール全体を覆い被せて、排熱構造を形成す
るものである。Embodiments of the present invention will be described below with reference to the drawings. As shown in FIG. 2, a flip-chip bonded package according to an embodiment of the present invention is a flip-chip bonded module, in which the entire module is covered with an epoxy resin to form a heat dissipation structure.

【００１０】フリップチップ結合モジュール１は錫ボー
ル１１１の設けられている基板１１上にフリップチップ
パッケージ方式により結合される。その構造中、充填剤
３１は突起２１１を完全に覆い被している。つづいて
銅、金、アルミニウムおよび銀など高熱伝導および高導
電性粒子成分を添加したエポキシーレジン４１でフリッ
プチップ結合モジュール１全体を包覆する。エポキシー
レジン４１とチップ２１の直接接触によって熱伝導の経
路を短縮し、排熱機能を高める。The flip-chip bonding module 1 is bonded on the substrate 11 on which the tin balls 111 are provided by a flip-chip package method. In the structure, the filler 31 completely covers the protrusion 211. Subsequently, the entire flip chip bonding module 1 is covered with an epoxy resin 41 to which high heat conductive and high conductive particle components such as copper, gold, aluminum and silver are added. The direct contact between the epoxy resin 41 and the chip 21 shortens the heat conduction path and enhances the heat discharging function.

【００１１】本発明の実施例による構造を使用すれば、
元のフリップチップ結合モジュール１を加工基礎状態で
そのまま加工することができ、生産ラインを移動交換す
る過程と時間を節約できる。本発明の実施例による構造
はチップを完全に包覆するので固定性および排熱性がと
もに向上可能となる。Using the structure according to the embodiment of the present invention,
The original flip chip bonding module 1 can be processed as it is in the processing basic state, and the process and time for moving and replacing the production line can be saved. The structure according to the embodiment of the present invention completely covers the chip, so that both the fixing property and the heat discharging property can be improved.

【００１２】更に本発明の実施例によるエポキシーレジ
ンは単一材料によるので、従来の違う材料が加熱された
後に発生する、異なる膨脹係数による結合上の問題を完
全に避けることができる。勿論、本実施例の構造におい
て単純にその基板１１を導線枠に変えて実施した場合、
それも本発明に規定された構造範囲に属するべきであ
る。Further, since the epoxy resin according to the embodiment of the present invention is made of a single material, it is possible to completely avoid the bonding problems caused by different expansion coefficients which occur after the conventional different materials are heated. Of course, in the structure of the present embodiment, when the substrate 11 is simply changed to a wire frame,
It should also belong to the structural range defined in the present invention.

【図面の簡単な説明】[Brief description of the drawings]

【図１】従来のフリップチップ結合パッケージを示す断
面図である。FIG. 1 is a cross-sectional view illustrating a conventional flip chip bonding package.

【図２】本発明の一実施例によるフリップチップ結合パ
ッケージを示す断面図である。FIG. 2 is a cross-sectional view illustrating a flip-chip bonded package according to an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１ フリップチップ結合モジュール ２ フリップチップ結合モジュール基板 １１ 基板 ２１ チップ ３１ 充填剤 ４１ エポキシーレジン １１１ 錫ボール ２１１ 突起 DESCRIPTION OF SYMBOLS 1 Flip chip bonding module 2 Flip chip bonding module board 11 Substrate 21 Chip 31 Filler 41 Epoxy resin 111 Tin ball 211 Projection

フロントページの続き (72)発明者 陳 ▲慧▼萍 台湾高雄県鳳山市海洋二路58号 (72)発明者 ▲蒋▼ 華文 台湾高雄市三民区昌富街57号３樓之２ (72)発明者 張 衷銘 台湾嘉義県布袋鎮見龍里109号 (72)発明者 ▲徐▼ 豐昌 台湾高雄県鳥松郷中正路367之９号 (72)発明者 ▲黄▼ 富裕 台湾高雄市新興区光耀里22隣渤海街29号 (72)発明者 張 軒睿 台湾高雄市前鎮区中山二路55巷35号 (72)発明者 胡 嘉傑 台湾高雄市楠梓区後昌路546巷11弄12号之 ５ Ｆターム(参考） 4M109 AA01 BA03 DB04 EA02 EB12 EC06 GA05 5F036 AA01 BB08 BB21 BD21 BE01Continuing on the front page (72) Inventor Chen ▲ Hui ▼ Ping No. 58, Ocean Road 2, Fengshan City, Kaohsiung, Taiwan ) Inventor Zhang Eikmei, No. 109, Yuri, Zimimi, Hotei, Chiayi, Taiwan No. 29, Bohai Street, Next to 22 Guangya-ri, Gu (29) No. 35, Zhang Xianlui, 55, Zhongshan 2nd Road, 55, Zhongshan District, Qianzhen District, Kaohsiung, Taiwan Toku No. 12 5F term (reference) 4M109 AA01 BA03 DB04 EA02 EB12 EC06 GA05 5F036 AA01 BB08 BB21 BD21 BE01

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 フリップチップ結合されたモジュールに
おいて高熱伝導および高導電性粒子を含むエポキシーレ
ジンにより前記モジュール全体を覆い被せることにより
排熱構造を形成し、 前記モジュールは錫ボールを有する基板上の所定位置に
フリップチップ形式により、突起でチップと基板とが結
合され、 充填接着剤により前記突起は完全に覆い被せられ、高熱
伝導および高導電性粒子を含む前記エポキシーレジンに
より前記モジュール全体が包覆され、前記エポキシーレ
ジンとチップとの直接接触によって伝熱経路が短縮され
排熱機能を高められていることを特徴とするフリップチ
ップ結合パッケージ。1. A heat-dissipating structure is formed by covering the entire module with an epoxy resin containing high thermal conductivity and high conductive particles in a flip-chip bonded module, wherein the module has a predetermined shape on a substrate having tin balls. In a flip-chip manner, the chip and the substrate are joined by protrusions, the protrusions are completely covered by the filling adhesive, and the entire module is covered by the epoxy resin containing high heat conductive and highly conductive particles. A flip chip bonding package, wherein a heat transfer path is shortened by a direct contact between the epoxy resin and the chip to enhance a heat discharging function. 【請求項２】 前記モジュール内の基板構造が導線枠に
より転用されていることを特徴とする請求項１記載のフ
リップチップ結合パッケージ。2. The flip-chip bonded package according to claim 1, wherein the substrate structure in the module is diverted by a wire frame.
JP2001036918A 2000-08-21 2001-02-14 Flip-chip coupled package Pending JP2002076206A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW89214600 2000-08-21
TW89214600 2000-08-21

Publications (1)

Publication Number Publication Date
JP2002076206A true JP2002076206A (en) 2002-03-15

Family

ID=21671897

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001036918A Pending JP2002076206A (en) 2000-08-21 2001-02-14 Flip-chip coupled package

Country Status (2)

Country Link
JP (1) JP2002076206A (en)
DE (1) DE10100142A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7956435B2 (en) 2008-03-12 2011-06-07 Renesas Electronics Corporation Semiconductor device
US8883331B2 (en) 2008-10-22 2014-11-11 Samsung Sdi Co., Ltd. Protective circuit module and rechargeable battery including the same
CN105789065A (en) * 2016-04-08 2016-07-20 广东欧珀移动通信有限公司 Chip package structure and preparation method thereof, and terminal device comprising the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7956435B2 (en) 2008-03-12 2011-06-07 Renesas Electronics Corporation Semiconductor device
US8883331B2 (en) 2008-10-22 2014-11-11 Samsung Sdi Co., Ltd. Protective circuit module and rechargeable battery including the same
CN105789065A (en) * 2016-04-08 2016-07-20 广东欧珀移动通信有限公司 Chip package structure and preparation method thereof, and terminal device comprising the same
US10679917B2 (en) 2016-04-08 2020-06-09 Guangdong Oppo Mobile Telecommunications Corp., Ltd. Chip package structure, terminal device, and method

Also Published As

Publication number Publication date
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