JP2002064138A - Semiconductor integrated circuit device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique which can improve electromigration resistance and achieve a favorable contact between an interconnect line and a plug. SOLUTION: A plug P2 formed between a first layer interconnect line M1 and a second layer interconnect line M2 is formed by etching an interlayer dielectric TH2 on the first layer interconnect line to expose a surface of the first layer interconnect line M1, and further etching (overetching) the exposed surface of the first layer interconnect line M1 to form a contact hole C2 whose bottom portion reaches a position deeper than the surface of the first layer interconnect line M1 and burying a tungsten film in this contact hole C2. As a result, the contact area of the first layer interconnect line M1 and the plug P2 can be increased and the average current density in the contact portion can be reduced. Accordingly, the electromigration resistance can be improved and a favorable contact between the interconnect line and the plug can be achieved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly to a technique effective when applied to a connection between wirings of a semiconductor integrated circuit device having a multilayer wiring.

[0002]

2. Description of the Related Art In recent years, with the increasing integration of LSIs, a multilayer wiring structure in which wirings and insulating films are repeatedly formed has been adopted. The plurality of wirings are connected via a plug formed in the interlayer insulating film.

[0003]

However, as the aspect ratio of the contact hole in which the plug is buried increases with the miniaturization of the semiconductor integrated circuit device, the area of the contact portion between the plug and the underlying wiring is reduced. In other words, physical and thermal stress at the contact portion may cause a contact failure.

Further, in the formation of a wiring by a so-called damascene technique which can realize a multi-layered wiring and a flattening, the electromigration resistance at the contact portion between the plug and the lower wiring is extremely low with respect to the reliability of the wiring. It is an important factor. That is, if the adhesion between the plug and the underlying wiring is weak, voids are generated due to electromigration when a current is applied, and the contact area may be reduced, and a connection failure may occur.

An object of the present invention is to improve the electromigration resistance between a wiring and a plug and to achieve good contact.

It is another object of the present invention to improve the reliability of a semiconductor integrated circuit device by achieving good contact between a wiring and a plug.

Another object of the present invention is to secure contact between a wiring and a plug even when a gap occurs between the wiring and a plug formed on the wiring. An object of the present invention is to improve the yield of semiconductor integrated circuit devices.

[0008] The purpose of the present invention and other objects and novel features will be apparent from the description of the present specification and the accompanying drawings.

[0009]

The following is a brief description of an outline of typical inventions disclosed in the present application.

(1) A method of manufacturing a semiconductor integrated circuit device according to the present invention includes: (a) forming a first wiring on a semiconductor substrate; and (b) forming an interlayer insulating film on the first wiring. (C) exposing the surface of the first wiring by etching the interlayer insulating film; and (d)
Forming a contact hole by further etching the exposed surface of the first wiring; and (e).
Forming a plug by burying a conductive film in the contact hole; and (f) forming a second plug on the plug.
Forming the wiring of the above.

(2) A method of manufacturing a semiconductor integrated circuit device according to the present invention includes: (a) forming a first copper wiring on a semiconductor substrate; and (b) an interlayer insulating film on the first copper wiring. (C) exposing the surface of the first wiring by anisotropically etching the interlayer insulating film; and (d) further etching the exposed surface of the first copper wiring. Forming a contact hole by anisotropically etching; and (e) forming a plug by embedding a conductive film in the contact hole;
(F) forming a second copper wiring on the plug;
Having.

(3) A method for manufacturing a semiconductor integrated circuit device according to the present invention includes: (a) forming a first insulating film for forming a wiring groove on a semiconductor substrate on which a semiconductor element is formed; and (b)
Forming a wiring groove by etching a wiring formation scheduled region of the first insulating film; and (c) forming a conductive film on the first insulating film including the inside of the wiring groove; Forming a first wiring in the wiring groove by polishing the first conductive film until the surface of the insulating film is exposed; and (e) forming the first wiring and the first insulating film. Forming an interlayer insulating film thereon; (f) exposing the surface of the first wiring by anisotropically etching the interlayer insulating film on the first wiring; and (g) exposing Forming a contact hole by further anisotropically etching the surface of the first wiring,
(H) forming a plug by burying a second conductive film in the contact hole; and (i) forming a second wiring on the plug.

(4) A method of manufacturing a semiconductor integrated circuit device according to the present invention includes: (a) forming a first insulating film for forming a wiring groove on a semiconductor substrate on which a semiconductor element is formed; and (b)
Forming a wiring groove by etching a wiring formation scheduled region of the first insulating film; and (c) forming a copper film on the first insulating film including the inside of the wiring groove, Forming a first wiring in the wiring groove by polishing the copper film until an insulating film surface is exposed;
(E) forming an interlayer insulating film on the first wiring and the first insulating film; and (f) anisotropically etching the interlayer insulating film on the first wiring to form the first insulating film. Exposing the surface of the wiring, and (g) exposing the exposed first surface.
Forming a contact hole by further anisotropically etching the surface of the wiring, (h) forming a plug by embedding a conductive film in the contact hole, and (i) forming a plug on the plug. Forming a second wiring.

(5) The semiconductor integrated circuit device of the present invention
(A) a first wiring serving as a contacted region formed on a semiconductor substrate; and (b) an insulating film formed on a region other than the contacted region on the first wiring. (C) a plug formed on the contacted region, the plug including a first connection part existing on the first wiring, and a second connection part existing in the first wiring; A plug, and (d) a second wiring formed on the plug.

[0015]

Next, a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention will be described. FIG.
11 to 11 are cross-sectional views of a main part of a substrate showing a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

First, as shown in FIG.
By the ET forming process, the n-channel type MISFET Q
An n and p channel type MISFET Qp is formed.

A typical MISFET forming process includes, for example, the following.

First, an element isolation groove 2 is formed by etching a semiconductor substrate 1 made of p-type single crystal silicon, and a thin silicon oxide film is formed on the inner wall of the groove by thermally oxidizing the substrate 1. Next, a silicon oxide film 7 is deposited on the substrate 1 including the inside of the groove by a CVD (Chemical Vapor deposition) method, and is subjected to chemical mechanical polishing (CMP; Ch).
The silicon oxide film 7 above the trench is polished by an emical mechanical polishing method to flatten the surface.

Next, a p-type impurity and an n-type impurity are ion-implanted into the substrate 1 and then the impurities are diffused by heat treatment to thereby form the p-type well 3 and the n-type well 4.
Is formed, a clean gate oxide film 8 having a thickness of about 6 nm is formed on each surface of the p-type well 3 and the n-type well 4 by thermal oxidation.

Next, a low-resistance polycrystalline silicon film 9a doped with phosphorus is deposited on the gate oxide film 8 by a CVD method, and then a thin WN film (not shown) and a W film are formed thereon by a sputtering method. 9c, and a silicon nitride film 10 is further deposited thereon by CVD.

Next, the silicon nitride film 10 is dry-etched to leave the silicon nitride film 10 in a region where a gate electrode is to be formed. Using the silicon nitride film 10 as a mask, a W film 9c and a WN film (not shown) By dry-etching the polycrystalline silicon film 9a, a gate electrode 9 composed of the polycrystalline silicon film 9a, the WN film and the W film 9c is formed.

Next, the p-type wells 3 on both sides of the gate electrode 9 are formed.
An n ⁻ -type semiconductor region 11 is formed by ion-implanting an n-type impurity into the p ^- type semiconductor region 12 by ion-implanting a p-type impurity into the n-type well 4.
To form

Next, after depositing a silicon nitride film on the substrate 1 by the CVD method, the silicon nitride film is anisotropically etched so that the side wall spacer 13 is formed on the side wall of the gate electrode 9.
To form

Next, an n ⁺ -type semiconductor region 14 (source, drain) is formed by ion-implanting an n-type impurity into the p-type well 3, and a p-type impurity is ion-implanted into the n-type well 4. ⁺ Type semiconductor region 15
(Source, drain) are formed.

Up to this point, LDD (Lightly Doped
N-channel type MISFET Qn and p-channel type MISFET Qp
Is formed.

Thereafter, an interlayer insulating film such as a silicon oxide film and a conductive film such as a copper film are alternately deposited on the MISFETs Qn and Qp to form a plurality of wirings. The formation will be described in detail with reference to FIGS.

First, as shown in FIG.
And a silicon oxide film having a thickness of about 700 nm to 800 nm is deposited on the Qp by the CVD method.
The interlayer insulating film TH1 is formed by polishing by the P method and flattening the surface.

Next, a photoresist film is formed on the interlayer insulating film TH1 (not shown), and the interlayer insulating film TH1 is etched using the photoresist film as a mask, thereby forming an n ⁺ type semiconductor on the main surface of the semiconductor substrate 1. A contact hole C1 is formed on the region 14 and the p ⁺ type semiconductor region 15.

Next, as shown in FIG. 3, a tungsten film is deposited on the interlayer insulating film TH1 including the inside of the contact hole C1 by the CVD method, and the tungsten film is polished by the CMP method until the interlayer insulating film TH1 is exposed. Thus, the plug P1 is formed in the contact hole C1. Note that the plug P1 may have a stacked structure of a barrier film made of a TiN film or the like and a tungsten film.

Next, the interlayer insulating film TH1 and the plug P
1, a silicon nitride film H1a and a silicon oxide film H
1b is sequentially deposited by the CVD method, and an insulating film H1 for a wiring groove made of these films is formed. The wiring groove HM1 is formed by etching the wiring groove insulating film H1 in the region where the first layer wiring is to be formed. The silicon nitride film H1a
Is used as an etching stopper at the time of the etching.

Next, as shown in FIG. 4, a barrier layer M1a made of titanium nitride is deposited on the wiring groove insulating film H1 including the inside of the wiring groove HM1 by sputtering or CVD.
Next, a copper film M1b is formed on the barrier layer M1a by a sputtering method. Note that the copper film may be formed by an electrolytic plating method.

Next, as shown in FIG. 5, the copper film M1b and the barrier layer M1a outside the wiring groove HM1 are removed by CMP to form a first layer wiring M1 composed of the copper film M1a and the barrier layer M1b.

Next, as shown in FIG. 6, an insulating film D1 for preventing copper diffusion is formed on the first layer wiring M1 by depositing a silicon nitride film by the CVD method.
Form H2. The interlayer insulating film TH2 is formed in the same manner as the interlayer insulating film TH1.

Then, using a resist film (not shown) in which the contact region of the first layer wiring M1 is opened on the interlayer insulating film TH2 as a mask, the interlayer insulating film is exposed until the surface of the first layer wiring M1 is exposed. TH2 and the insulating film D1 for preventing copper diffusion are anisotropically etched. Further, by etching (over-etching) the surface of the first layer wiring M1 exposed by this etching, the contact hole C whose bottom reaches a position deeper than the surface of the first layer wiring M1 is formed.
Form 2

Next, a plug P2 is formed in the contact hole C2 as follows. FIG. 7 is an enlarged view of the vicinity of the contact hole C2 in FIG. First, a barrier layer P2 is formed by depositing a nitride of a high melting point metal such as TiN, TaN or WN to a thickness of 30 to 70 nm on the interlayer insulating film TH2 including the inside of the contact hole C2 shown in FIG.
a is formed (FIG. 8). The barrier layer P2a is lower wiring by (in this case, the first layer wiring M1) WF ₆ used in the formation of the tungsten film to be described later serve to prevent erosion. Next, CVD is performed on the barrier layer P2a.
About 200 to 500 nm tungsten film P2b
Is deposited (FIG. 9). Note that the tungsten film P2b is
The contact hole C2 is formed so as to be completely buried.

Subsequently, the plug P2 composed of the tungsten film P2b and the barrier layer P2a is formed by removing the tungsten film P2b and the barrier layer P2a outside the contact hole C2 by CMP (FIG. 10).

Next, the second layer wiring M2 is placed on the plug P2.
Is formed in the same manner as the first layer wiring M1. That is, the silicon nitride film H2a is formed on the interlayer insulating film TH2 and the plug P1.
And a silicon oxide film H2b are sequentially deposited, and the wiring groove insulating film H2 formed of these films is etched to form a wiring groove HM2. Next, a barrier layer M1a made of titanium nitride is deposited on the wiring groove insulating film H2 including the inside of the wiring groove HM2, and then a copper film M is formed on the barrier layer M2a.
2b is formed by sputtering or electrolytic plating. Next, the copper film M2b and the barrier layer M2a outside the wiring groove HM2 are removed by CMP to form the copper film M2a.
And a second layer wiring M2 composed of a barrier layer M2b.

As described above, in the present embodiment, the first
When the contact hole C2 was formed on the layer wiring M1, after the surface of the first layer wiring M1 was exposed, over-etching was performed to form the plug P2 in the contact hole C2. However, since they extend not only in the interlayer insulating film (first connection part) but also in the first layer wiring M1 (second connection part), the contact area with the first layer wiring M1 increases. Therefore, even if a physical or thermal stress is applied to the contact portion between the plug P2 and the first layer wiring M1, a contact failure hardly occurs.

FIG. 12 shows that the plug P is inserted into the contact hole C92 which has been etched when the surface of the first layer wiring M1 is exposed without performing the over-etching.
In this case, electrons flow in the direction of the arrow in the figure (current flows in the direction opposite to the direction of the arrow).
In this case, since the contact area between the plug P92 and the first-layer wiring M1 is smaller than that in FIG. 11, the average current density in the contact portion is large, voids are generated by electromigration, and the contact area is reduced and the connection failure is caused. (Electromigration resistance is reduced).

Conversely, in the case shown in FIG. 11, the contact area between the plug P2 and the first layer wiring M1 is increased, and the electromigration resistance can be improved. As a result, good contact between the wiring and the plug can be achieved, and the reliability of the semiconductor integrated circuit device can be improved.

Further, as shown in FIG.
Even if a gap occurs between the plug 1 and the plug P2, a certain contact area can be secured, and the yield of the semiconductor integrated circuit device can be improved.

After the overetching, a reducing atmosphere (H2, CO, etc.) or an inert atmosphere (A
(r, Xe, etc.), the contaminants at the bottom of the contact hole C2 generated at the time of etching may be removed. Alternatively, the inside of the contact hole C2 may be cleaned by performing sputtering in a reducing atmosphere (H2, CO, etc.) or an inert atmosphere (Ar, Xe, etc.). By performing these processes, a better contact can be obtained.

Further, at the beginning of the formation of the barrier layer P2a,
After forming a Ti or Ti-rich TiN layer having a thickness of about 2 to 10 nm at the bottom of the contact hole, a TiN film or the like may be formed. If such a Ti layer or a Ti-rich TiN layer is formed, these layers and the underlying copper film M1b form an alloy layer, and copper atoms are less likely to move, so that the electromigration resistance is further improved. If a Ta film having a thickness of about 2 to 10 nm is formed at the bottom of the contact hole at the initial stage of the formation of the barrier layer P2a, the adhesion to the underlying copper film M1b is improved, so that the electromigration resistance is improved.

If a tungsten film having a thickness of about 10 to 80 nm is formed at the bottom of the contact hole by a sputtering method before forming the tungsten film P2b formed by the CVD method, the barrier layer P2a, the sputtered tungsten film and the CVD tungsten film are formed. The adhesion of the film can be further improved.

Next, as shown in FIG. 14, a copper diffusion preventing insulating film D2 and an interlayer insulating film TH are formed on the second layer wiring M2.
Form 3 These films are made of the copper diffusion preventing insulating film D
1 and the interlayer insulating film TH1. afterwards,
A contact hole C3 is formed in the copper diffusion prevention insulating film D2 and the interlayer insulating film TH3. When forming the contact hole C3, over-etching is performed as in the case of the contact hole C2. Next, a plug P3 is formed in the contact hole C3. This plug P
3 is formed similarly to the plug P2. Next, the wiring groove insulating film H3 and the wiring groove HM3 are formed on the interlayer insulating film TH3 and the plug P3 in the same manner as the wiring groove insulating film H1 and the wiring groove HM1, and the third layer wiring is formed in the same manner as the first layer wiring M1. The layer wiring M3 is formed.

The copper diffusion preventing insulating film (D3, D
4, D5) and interlayer insulating films (TH4, TH5), formation of plugs (P4, P5) formed in contact holes in these films, and wiring (M4,
By repeating the formation of M5), a semiconductor integrated circuit device having a multilayer wiring structure shown in FIG. 14 can be formed.
Although illustrations of the subsequent steps are omitted, the fifth layer wiring M5
A passivation film 20 made of a silicon nitride film, a silicon oxide film, or the like is formed thereon, and a portion of the passivation film 20 is removed by etching to expose a bonding pad portion on the fifth layer wiring M5.
Next, an under bump electrode made of gold or the like is formed on the exposed fifth layer wiring M5, and a bump electrode made of gold or solder is formed on the under bump electrode.

Thereafter, the semiconductor integrated circuit device is mounted on a package substrate or the like to complete the semiconductor integrated circuit device, but the description thereof is omitted.

In this embodiment, five layers of wiring are formed, but five or less layers or five or more layers may be formed.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. Needless to say,

In the present embodiment, the MISFETs Qn and Qp are formed as semiconductor elements. However, the present invention is not limited to these MISFETs. A bipolar transistor can also be formed, and a MISFET and a bipolar transistor can be formed on the same substrate. You can also.
Further, the present invention can be widely applied to a semiconductor integrated circuit device having a multilayer wiring structure in which wirings are connected by plugs.

[0051]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

In the method of manufacturing a semiconductor integrated circuit device according to the present invention, a plug formed between the first wiring and the second wiring is formed by etching an interlayer insulating film on the first wiring. Exposing the surface of the wiring and further etching (over-etching) the exposed surface of the first wiring to form a contact hole whose bottom reaches a position deeper than the surface of the first wiring;
Since the plug is formed by embedding a conductive film in the contact hole, the contact area between the first wiring and the plug can be increased, and the average current density in the contact portion can be reduced. Migration resistance can be improved. as a result,
Good contact between the wiring and the plug can be achieved, and the reliability of the semiconductor integrated circuit device can be improved.

Further, since the contact area between the first wiring and the plug can be increased, even if the first wiring and the plug are out of contact, a certain contact area is secured. And the yield of the semiconductor integrated circuit device can be improved.

Further, in the semiconductor integrated circuit device according to the present invention, the plug formed between the first wiring and the second wiring is connected to the first connecting portion existing on the first wiring and the first connection part. Since the plug is formed of the second connection portion existing in the wiring, the contact area between the first wiring and the plug can be increased, and the average current density in the contact portion can be reduced. Electromigration resistance can be improved. As a result, good contact between the wiring and the plug can be achieved, and the reliability of the semiconductor integrated circuit device can be improved.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view of a substrate, illustrating a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 3 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 8 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 10 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 11 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 12 is a diagram for explaining an effect of the present invention.

FIG. 13 is a cross-sectional view of a main part of the substrate when a gap occurs between a wiring and a plug.

FIG. 14 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2 element isolation 3 p-type well 4 n-type well 7 silicon oxide film 8 gate oxide film 9 gate electrode 9a polycrystalline silicon film 9c W film 10 silicon nitride film 11 n ^- type semiconductor region 12 p ^- type semiconductor region 13 Side wall spacer 14 n ⁺ type semiconductor region 15 p ⁺ type semiconductor region 20 insulating film C1 to C5 contact hole TH1 to TH5 interlayer insulating film H1 to H5 insulating film for wiring groove H1a to H5a silicon nitride film H1b to H5b silicon oxide film HM1 To HM5 wiring groove M1 to M5 wiring M1a to M5a barrier layer M1b to M5b copper film D1 to D5 copper diffusion prevention insulating film P1 to P5 plug P1a to P5a barrier layer P1b to P5b tungsten film C92 contact hole P92 plug Qn n-channel MISFET Qp p-channel type M ISFET

 ──────────────────────────────────────────────────続 き Continuing on the front page F term (reference)

Claims (5)

[Claims] (A) forming a first wiring on a semiconductor substrate; (b) forming an interlayer insulating film on the first wiring; and (c) etching the interlayer insulating film. And (d) further etching the exposed surface of the first wiring so that the bottom reaches a position deeper than the surface of the first wiring. Forming a contact hole; (e) forming a plug by burying a conductive film in the contact hole; and (f) forming a second wiring on the plug. A method for manufacturing a semiconductor integrated circuit device, comprising: 2. A step of forming a first copper wiring on a semiconductor substrate; a step of forming an interlayer insulating film on the first copper wiring; and a step of forming an interlayer insulating film on the first copper wiring. Exposing the surface of the first copper wiring by anisotropically etching; and (d) forming a contact hole by further anisotropically etching the exposed surface of the first copper wiring (E) forming a plug by burying a conductive film in the contact hole; and (f) forming a second copper wiring on the plug.
A method for manufacturing a semiconductor integrated circuit device, comprising: (A) forming a first insulating film for forming a wiring groove on a semiconductor substrate on which a semiconductor element is formed; and (b) etching a wiring forming region of the first insulating film. (C) forming a conductive film on the first insulating film including the inside of the wiring groove, and forming the conductive film on the first insulating film until the surface of the first insulating film is exposed. By polishing the conductive film, the first in the wiring groove is formed.
(E) forming an interlayer insulating film on the first wiring and the first insulating film; and (f) forming an interlayer insulating film on the first wiring anisotropically. (G) a step of exposing the surface of the first wiring by etching, and (g) a step of forming a contact hole by further anisotropically etching the exposed surface of the first wiring; A) forming a plug by embedding a second conductive film in the contact hole; and (i) forming a second wiring on the plug. Device manufacturing method. 4. A step of (a) forming a first insulating film for forming a wiring groove on a semiconductor substrate on which a semiconductor element is formed; and (b) etching a region of the first insulating film where a wiring is to be formed. (C) forming a copper film on the first insulating film including the inside of the wiring groove, and polishing the copper film until the surface of the first insulating film is exposed; (E) forming an interlayer insulating film on the first wiring and the first insulating film; and (f) forming the first insulating film on the first wiring and the first insulating film. Exposing the surface of the first wiring by anisotropically etching the interlayer insulating film on the wiring; and (g) etching the exposed surface of the first wiring further anisotropically. Forming a contact hole; and (h) the contact hole. A method of forming a plug by embedding a conductive film therein; and (i) forming a second wiring on the plug. 5. A semiconductor device comprising: (a) a first wiring having a contacted region formed on a semiconductor substrate; and (b) a first wiring formed on a region other than the contacted region on the first wiring. (C) a plug formed on the contacted region, a first connecting portion present on the first wiring, and a second connecting portion present on the first wiring. A semiconductor integrated circuit device, comprising: a plug comprising a connection portion; and (d) a second wiring formed on the plug.