JP2000260869A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which prevents the generation of junction leakage and whose yield rate can be improved and to provide its manufacturing method. SOLUTION: In this manufacturing method, a contact hole 104 is made in an interlayer insulating film 103 and an interlayer insulating film 110, in such a way that the surface of an impurity diffused layer 102 is exposed, and a contact layer composed of a Ti/TiN film 105 is formed so as to cover the bottom face and the inside face of the contact hole 104. After that, although it is subjected to annealing treatment, when the annealing treatment is executed at a lower temperature and in a shorter time as compared with conventional cases, a titanium monosilicide part 106 is formed in the interface between the Ti/TiN film 105 and a silicon substrate 101. The titanium monosilicide part 106 has a curvature which is smaller than that of a titanium monosilicide part which is formed in conventional cases, and a junction leakage is not generated between the titanium monosilicide part 106 and the diffused layer 102. Thereby, the yield of this semiconductor device is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a structure and a method of filling a contact hole formed on a surface of a semiconductor substrate.

[0002]

2. Description of the Related Art In recent years, as semiconductor devices have become finer and more integrated, dimensions of respective elements and contact portions have been reduced, and at the same time, the number of layers has been increased.

On the surface of a semiconductor substrate, a silicon (Si) surface or a titanium (Ti), cobalt (C)
An impurity diffusion layer is formed on the surface of the silicon compound such as o), and a contact hole for electrically connecting the upper wiring and the lower wiring in the multilayer wiring is formed on the surface of the impurity diffusion layer. The miniaturization of such a contact portion is also in progress. Then, on the surface of the impurity diffusion layer exposed at the bottom surface of the contact hole, there is a natural oxide film or a substance having non-conductivity due to contamination or the like in a reactive ion etching (hereinafter referred to as RIE) process. Exists. In order to remove such non-conductors, cleaning of the surface of the impurity diffusion layer and formation of a reducible metal such as Ti on the surface are performed.

[0004] In the following, Ti and titanium nitride (TiN) are formed on the surface of the diffusion layer to establish electrical continuity with the diffusion layer.
Further, a structure of a conventional contact portion in which the inside of a contact hole is filled with tungsten (W) (hereinafter referred to as a blanket W) and a method thereof will be described with reference to FIG.

[0005] As shown in FIG. 4 (a), an n ⁺ -type impurity and / or
And p ⁺ -type impurities are ion-implanted to form n-type impurity diffusion layer 2.
02 and / or p ⁺ -type impurity diffusion layers are formed.

As shown in FIG. 4B, an interlayer insulating film 203 such as a silicon oxide film or BPSG is deposited, and the surface is flattened. Then, a contact hole 204 is formed by using photolithography or RIE so that the surface of the impurity diffusion layer 202 is exposed.

As shown in FIG. 4C, a Ti / TiN film 205 or a tungsten nitride (WN) film is formed on at least the bottom and side surfaces of the contact hole by using a CVD method or a PVD method. The Ti / TiN film 205 corresponds to a glue layer (adhesion layer), and is formed of a film having adhesion to the hole bottom surface. This film 205
It is formed in order to prevent the occurrence of bonding failure due to Si molecules present on the surface of the semiconductor substrate 101 being sucked up by a filling material such as W or aluminum (Al).

Thereafter, annealing is performed in a nitrogen (N ₂ ) atmosphere to cause a silicidation reaction in the Ti / TiN film 205. Thus, titanium disilicide (TiSi ₂ ) 207 is formed as shown in FIG.

As shown in FIG. 4D, a blanket W208 is embedded in the contact hole 204, and the surface is flattened by a CMP method or the like.

[0010]

However, the above-mentioned conventional method has the following problems. When a silicidation reaction occurs in the annealing process in FIG. 4C, the impurity diffusion layer 202 and the Ti / TiN film 20 are removed.
5, TiSi ₂ 207 is formed at the interface. This T
iSi ₂ 207 grows with high curvature from Ti / TiN film 205 toward impurity diffusion layer 202. For this reason, TiSi ₂ 207 may erode the diffusion layer 202 and cause a junction leak. Such a phenomenon,
In the future, as the thickness of the impurity diffusion layer 202 becomes thinner with miniaturization, the impurity diffusion layer 202 becomes more remarkable and may cause a fatal defect.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor device capable of preventing the occurrence of junction leakage and improving the yield when filling a contact hole 204 and a method of manufacturing the same. Aim.

[0012]

According to the present invention, there is provided a semiconductor device comprising:
A semiconductor substrate containing silicon having an impurity diffusion layer formed on a surface thereof; an insulating film deposited on a surface of the semiconductor substrate and having an opening formed on the impurity diffusion layer; A first conductive film formed on the bottom surface and the inner side surface; and a second conductive film formed so as to fill the opening, wherein the first conductive film is formed of a conductive material containing a metal. An annealing process is performed after the deposition, and includes at least a metal silicide layer having a silicon to metal ratio of less than two.

It is preferable that the metal silicide layer has a ratio of silicon to the metal of 1 or less.

The impurity diffusion layer may be formed at a depth of 80 nm or less from the surface of the semiconductor substrate.

[0015] The metal silicide layer may include at least a metal monosilicide as a part thereof.

The metal contained in the first conductive film is Ti, N
Any of i, Co, W, Cu, Ag, Al, and Au may be used.

A metal silicide layer is formed on a surface portion of the semiconductor substrate.
It may be configured to include any of i, Ni, Co, and W.

According to the method of manufacturing a semiconductor device of the present invention, a step of forming an impurity diffusion layer on a surface portion of a semiconductor substrate containing silicon; a step of forming an interlayer insulating film on a surface of the semiconductor substrate; Forming a contact hole in the interlayer insulating film so that a surface of the layer is exposed; forming a first conductive film on at least a bottom surface and an inner surface of the contact hole; Embedding with a second conductive film, wherein in the forming the first conductive film, a conductive material containing a metal is deposited on the bottom surface and the inner surface of the contact hole, and at least the metal The annealing process is performed so as to include a metal silicide layer having a silicon ratio of less than 2.

Here, T is applied to the surface of the semiconductor substrate.
The method may further include a step of forming a metal silicide layer containing any of i, Ni, Co, and W.

The metal contained in the first conductive film is Ti, N
Any of i, Co, W, Cu, Ag, Al, and Au may be used.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. In this embodiment, before filling the inside of the contact hole with the blanket W, T
Taking an example in which an i / TiN film is formed as an adhesion layer on the bottom surface and the inner side surface of the contact hole, annealing treatment is performed at a low temperature for a short time to cause a silicidation reaction to form titanium monosilicide (TiSi). There is a feature in the point.

As shown in FIG. 1A, an n ⁺ -type impurity and / or an n ⁺ -type impurity are formed on a p-type semiconductor substrate 101 (silicon substrate).
Then, ion implantation of p ⁺ -type impurities is performed and high-temperature annealing at 800 ° C. or higher is performed to form the n ⁺ -type impurity diffusion layer 102 and / or the p ⁺ -type impurity diffusion layer.

As shown in FIG. 1B, a silicon oxide film or B
The interlayer insulating film 103 of PSG or the like is
The film is deposited to a thickness of 000 Å, and the surface is flattened to a thickness of 4000 to 8000 Å by a CMP method. Further, an insulating film 110 using tetraethoxysilane (TEOS) and oxygen (O ₂ ) as source gases is deposited on the surface of the interlayer insulating film 103 to a thickness of 3000 to 5000 angstroms.

After that, a contact hole 104 is formed by photolithography or RIE so that the surface of the impurity diffusion layer 102 is exposed.

As shown in FIG. 1C, a Ti / TiN film 1 corresponding to an adhesion layer is formed on at least the bottom and side surfaces of the contact hole by using a CVD method or a PVD method.
05 is formed with a thickness of 50 to 250 angstroms.

Thereafter, annealing is performed in an N ₂ atmosphere to cause a titanium silicidation reaction in the Ti / TiN film 105. Here, the annealing conditions are, for example, 30 to 90 minutes at 550 degrees Celsius, and 5 to
It is set at a lower temperature and shorter time than before, such as 15 minutes. Thereby, titanium monosilicide (TiS) is formed from the Ti / TiN film 205 toward the impurity diffusion layer 102.
i) 106 is formed with a thickness of 60 to 300 angstroms.

As shown in FIG. 1D, a blanket W107 is embedded in the contact hole 104, and the surface is flattened by a CMP method or the like.

According to the present embodiment, the Ti / TiN film 1
By performing annealing at a low temperature for a short time on TiN 05, Ti
The Si 106 is formed. Since the TiSi 106 has a smaller curvature than the conventionally formed TiSi ₂ , there is no possibility of causing a junction leak with the diffusion layer 102. In particular, even when the diffusion layer 102 is miniaturized to, for example, about 80 nm, it is possible to prevent the occurrence of junction leak.

Here, when the Ti / TiN layer is annealed, almost all of the titanium silicide layer becomes a TiSi layer depending on the annealing conditions. However, depending on the conditions, the titanium silicide layer is changed not only to the TiSi layer but also partly to TiSi ₂ . As shown in FIG. 5A, a Ti film 105a is first formed on at least the bottom and inner side surfaces of the contact hole 104, and a TiN film 105b is formed on the surface. Thereafter, as shown in FIG. 5B, the lower portion of the Ti film 105a which is in direct contact with the semiconductor substrate 101 is changed to TiSi2 105a2, and the upper surface of the Ti film 105a is TiSi2, as shown in FIG.
May remain without being TiSi ₂ .

As described above, even when TiSi ₂ is contained in a part of the adhesion layer, the occurrence of junction leakage is suppressed as compared with the conventional case where almost all of the adhesion layer is made of TiSi ₂ .

FIG. 3 shows a simulation result of the yield rate with respect to the junction leakage withstand voltage. Assuming that the yield rate of the semiconductor device manufactured by the conventional manufacturing method is about 52%, the semiconductor device according to the above-described embodiment has a yield of about 98%.
% Is greatly improved.

The above-described embodiment is an example and does not limit the present invention. For example, in the above embodiment, the case where the n ⁺ -type impurity diffusion layer 102 and / or the p ⁺ -type impurity diffusion layer are formed on the surface portion of the p-type semiconductor substrate 101 has been described as an example. However, the present invention can be similarly applied to a case where an n ⁺ -type impurity diffusion layer and / or a p ⁺ -type impurity diffusion layer are formed on a surface portion of an n-type semiconductor substrate.

Also, a case where a Ti / TiN film is formed as an adhesion layer in a contact hole has been described as an example. However, the present invention is not limited to this, and it is possible to use Cu, Ag, Al, Au, Ni, or a compound of Co and Si. There may be.

In the above embodiment, TiSi is formed at the interface between the adhesion layer and the surface of the semiconductor substrate by annealing. However, the ratio of metal to silicon is not limited to such a one-to-one ratio, and the ratio of silicon to metal may be less than 2, and is more preferably 1 or less.

Furthermore, as is often the case in logic circuits, a compound of metal and silicon is formed on the surface of a semiconductor substrate in order to enhance the conductivity on the surface of the semiconductor substrate and improve the operation speed. The present invention can also be applied to the present invention. For example, as shown in FIG. 2, a metal silicide layer 111, which is a compound of W, Ni, or Co and silicon, is formed on the surface of the semiconductor substrate 101, and impurities are formed on the surface of the substrate where the metal silicide layer 111 exists. The present invention can be applied to a case where the diffusion layer 102 is formed. That is, also in this case, it is possible to form the adhesion layer 105 in the contact hole 104 and perform an annealing process so that the metal silicide film 106 having a silicon to metal ratio of less than 2 is formed.

[0036]

As described above, according to the semiconductor device and the method of manufacturing the same of the present invention, an adhesion layer containing a metal is formed in a contact hole, and an annealing process is performed to reduce the ratio of metal to silicon. By forming a metal silicide that is less than the above, it is possible to prevent a junction leak from occurring with the impurity diffusion layer on the surface of the semiconductor substrate, and to improve the yield.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view of an element showing a structure of a semiconductor device and a method of manufacturing the same according to an embodiment of the present invention for each process.

FIG. 2 is a longitudinal sectional view of an element showing a structure of a semiconductor device according to another embodiment of the present invention and a method of manufacturing the same.

3 is a graph showing a comparison between a yield rate with respect to a junction leakage withstand voltage in the semiconductor device according to the embodiment shown in FIG. 1 and a conventional semiconductor device.

FIG. 4 is a longitudinal sectional view of an element showing a structure of a conventional semiconductor device and a method of manufacturing the same in each step.

FIG. 5 is an explanatory diagram showing in detail a configuration in a case where a part of a titanium monosilicide layer is changed to a titanium disilicide layer in the adhesion layer in the embodiment shown in FIG. 1;

[Explanation of symbols]

Reference Signs List 101 p ⁺ semiconductor substrate 102 n ⁺ impurity diffusion layer 103 interlayer insulating film (BPSG film or silicon oxide film) 104 contact hole 105 Ti / TiN film (adhesion layer) 105a Ti film 105b, 122 TiN film 106 TiSi 107 blanket W 110 interlayer Insulating film (TEOS film) 111 Metal silicide layer 121 TiSi film

Continuing on the front page F-term (reference) 4M104 AA01 BB20 BB21 BB25 BB28 BB38 DD78 DD84 FF16 FF22 HH04 5F033 JJ07 JJ08 JJ11 JJ13 JJ14 JJ18 JJ19 JJ25 JJ27 JJ28 JJ33 KK01 KK25 Q04 KK27 Q04 NN07 Q04 WW01 XX01 XX28

Claims (9)

[Claims] A semiconductor substrate including silicon having an impurity diffusion layer formed on a surface thereof; an insulating film deposited on a surface of the semiconductor substrate and having an opening formed on the impurity diffusion layer; A first conductive film formed on the bottom surface and the inner side surface of the opening, and a second conductive film formed so as to fill the opening, wherein the first conductive film is formed of a metal. A semiconductor device comprising: a metal silicide layer in which an annealing process is performed after a conductive material containing is deposited, and at least a ratio of silicon to the metal is less than 2. 2. The semiconductor device according to claim 1, wherein said metal silicide layer has a ratio of silicon to said metal of 1 or less. 3. The semiconductor device according to claim 1, wherein said impurity diffusion layer is formed at a depth of 80 nm or less from a surface of said semiconductor substrate. 4. The semiconductor device according to claim 1, wherein said metal silicide layer contains at least a metal monosilicide in a part thereof. 5. The method according to claim 1, wherein the metal contained in the first conductive film is Ti, N.
5. The semiconductor device according to claim 1, wherein the semiconductor device is any one of i, Co, W, Cu, Ag, Al, and Au. 6. A metal silicide layer is formed on a surface portion of said semiconductor substrate.
The semiconductor device according to claim 1, wherein the semiconductor device includes one of i, Ni, Co, and W. 7. A step of forming an impurity diffusion layer on a surface portion of a semiconductor substrate containing silicon, a step of forming an interlayer insulating film on a surface of the semiconductor substrate, and a step of exposing a surface of the impurity diffusion layer. Forming a contact hole in the interlayer insulating film, forming a first conductive film on at least the bottom surface and inner surface of the contact hole, and filling the contact hole with a second conductive film. In the step of forming the first conductive film, a conductive material containing a metal is deposited on a bottom surface and an inner surface of the contact hole, and at least a ratio of silicon to the metal is less than 2 A method for manufacturing a semiconductor device, comprising performing an annealing process so as to include a certain metal silicide layer. 8. The semiconductor substrate according to claim 1, wherein Ti, N
The method of manufacturing a semiconductor device according to claim 7, further comprising a step of forming a metal silicide layer containing any of i, Co, and W. 9. The metal included in the first conductive film is Ti, N
9. The method for manufacturing a semiconductor device according to claim 7, wherein the semiconductor device is any one of i, Co, W, Cu, Ag, Al, and Au.