WO2005038904A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2005038904A1
WO2005038904A1 PCT/JP2004/012448 JP2004012448W WO2005038904A1 WO 2005038904 A1 WO2005038904 A1 WO 2005038904A1 JP 2004012448 W JP2004012448 W JP 2004012448W WO 2005038904 A1 WO2005038904 A1 WO 2005038904A1
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WO
WIPO (PCT)
Prior art keywords
film
wiring
insulating film
semiconductor device
opening
Prior art date
Application number
PCT/JP2004/012448
Other languages
French (fr)
Japanese (ja)
Inventor
Hiroshi Ashihara
Takayuki Oshima
Kensuke Ishikawa
Tatsuyuki Saito
Tomio Iwasaki
Original Assignee
Renesas Technology Corp.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp. filed Critical Renesas Technology Corp.
Publication of WO2005038904A1 publication Critical patent/WO2005038904A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865—Selective removal of parts of the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device having a buried wiring including a main conductor film containing copper as a main component.
  • the elements of the semiconductor device are connected by, for example, a multilayer wiring structure to form a circuit.
  • embedded wiring structures have been developed as wiring structures.
  • the buried wiring structure uses damascene (Single-Damascene) technology and single-damascene technology in wiring openings such as wiring grooves and holes (vias) formed in the insulating film. It is formed by embedding wiring material using Dual-Damascene) technology.
  • Japanese Patent Application Laid-Open No. 2002-343859 discloses W—WN to improve the adhesion between the upper layer wiring and the barrier metal and the adhesion between the barrier metal and the lower layer wiring in order to prevent the generation of voids in the via portion of the copper wiring.
  • —W or Ta—TaN—Ta structure is disclosed (see Patent Document 1).
  • Japanese Patent Application Laid-Open No. 2003-68848 discloses a structure in which W is selectively grown on a lower copper wiring in a via portion (see Patent Document 2).
  • Japanese Patent Application Laid-Open No. 2001-319928 discloses that W is selectively grown on Cu of a lower layer wiring and a W plug is formed on the W selective growth film (see Patent Document 3).
  • Japanese Patent Application Laid-Open No. 2002-64138 discloses a technique of forming a "W-blag" after over-etching the surface of the lower wiring in order to increase the contact area between the plug and the lower wiring (see Patent Document 4). .
  • Patent Document 1 Japanese Patent Application Laid-Open No. 2002-343859
  • Patent Document 3 Japanese Patent Application Laid-Open No. 2001-319928
  • Patent Document 4 Japanese Patent Application Laid-Open No. 2002-64138 Disclosure of the invention
  • failure may occur due to stress migration or the like.
  • the electrical resistance of the buried copper wiring increases. This is because voids or voids are formed between the upper surface of the lower buried copper wiring and the via part (via buried part) of the upper buried copper wiring, and the connection area between the lower wiring and the upper wiring is reduced. To do that. Such a phenomenon reduces the reliability of the semiconductor device having the embedded copper wiring.
  • An object of the present invention is to provide a technology capable of improving the reliability of a semiconductor device having embedded copper wiring.
  • a cap conductive film is formed on a lower copper wiring, the cap conductive film is removed at the bottom of the via when forming a via connected to the lower copper wiring, and the cap conductive film is formed again on the lower copper wiring at the bottom of the via.
  • a barrier conductor film for forming an upper copper wiring and a conductor film containing copper as a main component are formed.
  • the present invention also provides a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a first opening formed in the first insulating film, and formed on a side wall and a bottom of the first opening.
  • a first wiring having a first parier conductive film and a first conductive film containing copper as a main component formed on the first parier conductive film so as to fill the inside of the first opening; and formed on the first conductive film.
  • Item 1 (a) a step of preparing a semiconductor substrate
  • a method for manufacturing a semiconductor device comprising:
  • Item 2 The method for manufacturing a semiconductor device according to Item 1,
  • the step (d) includes:
  • a method for manufacturing a semiconductor device comprising: Item 3: In the method for manufacturing a semiconductor device according to Item 1,
  • a method for manufacturing a semiconductor device comprising:
  • Item 4 The method for manufacturing a semiconductor device according to Item 1,
  • the first cap conductor film is formed by selectively or preferentially growing the first cap conductor film on the first wiring.
  • Item 5 The method for manufacturing a semiconductor device according to Item 1,
  • the second cap conductor film is selectively grown or preferentially grown on the first conductor film exposed at the bottom of the second opening to form the second cap conductor film.
  • Item 6 The method for manufacturing a semiconductor device according to Item 1,
  • the first cap conductor film is made of tungsten, a tungsten alloy, cobalt, a cobalt alloy, nickel, or nickel alloy.
  • Item 7 The method for manufacturing a semiconductor device according to Item 1,
  • the second cap conductor film is made of tungsten, a tungsten alloy, cobalt, a cobalt alloy, nickel, or nickel alloy.
  • Item 8 The method for manufacturing a semiconductor device according to Item 1,
  • a thickness of the first cap conductor film formed in the step (e) is in a range of 2 to 20 nm.
  • Item 9 The method for manufacturing a semiconductor device according to Item 1,
  • a thickness of the second cap conductor film formed in the step (h) is in a range of 2 to 20 nm.
  • Item 10 In the method of manufacturing a semiconductor device according to Item 1,
  • the first parier conductor film includes a high melting point metal film other than tungsten, In the method (e), the first cap conductor film is formed by an electroless plating method.
  • Item 11 In the method for manufacturing a semiconductor device according to Item 1,
  • the first capacitor conductor film does not include a refractory metal film other than tungsten, and in the step (e), the first cap conductor film is formed by a CVD method or an electroless plating method. A method for manufacturing a semiconductor device.
  • Item 12 In the method for manufacturing a semiconductor device according to Item 1,
  • the second opening is formed so that the first barrier conductor film is not exposed at the bottom of the second opening;
  • the second cap conductor film is formed by a CVD method or an electroless plating method.
  • Item 13 In the method for manufacturing a semiconductor device according to Item 1,
  • the first barrier conductor film does not include a refractory metal film other than tungsten, and in the step (g), the second opening is formed such that the first barrier conductor film is exposed at the bottom of the second opening.
  • the second cap conductor film is formed by a CVD method or an electroless plating method.
  • Item 14 The method for manufacturing a semiconductor device according to Item 1,
  • the first parier conductor film includes a high melting point metal film other than tungsten,
  • the second opening is formed so that the first barrier conductor film is exposed at the bottom of the second opening
  • the second cap conductor film is formed by an electroless plating method.
  • Clause 15 In the method of manufacturing a semiconductor device according to clause 1,
  • Item 16 In the method for manufacturing a semiconductor device according to Item 15,
  • the upper surface of the first cap conductor film and the upper surface of the first insulating film Forming the first cap conductive film such that the first cap conductor film is substantially flat.
  • Item 17 In the method for manufacturing a semiconductor device according to Item 1,
  • the second opening having a wiring groove formed in the second insulating film and a via reaching from the bottom of the wiring groove to the first conductive film is formed; Forming a second cap conductor film on the first conductor film exposed at the bottom of the via.
  • Item 18 In the method for manufacturing a semiconductor device according to Item 1,
  • the second insulating film including a plurality of insulating films including a first insulating film and a barrier insulating film formed on the first cap conductive film is formed. Manufacturing method.
  • Item 19 (a) the step of preparing a semiconductor substrate
  • a method for manufacturing a semiconductor device comprising:
  • Item 20 (a) a step of preparing a semiconductor substrate
  • a method for manufacturing a semiconductor device comprising: Brief Description of Drawings
  • FIG. 1 is a fragmentary cross-sectional view of a semiconductor device according to an embodiment of the present invention during a manufacturing step.
  • FIG. 2 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG.
  • FIG. 3 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG.
  • FIG. 4 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG.
  • FIG. 5 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG.
  • FIG. 6 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG.
  • FIG. 7 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG.
  • FIG. 8 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG.
  • FIG. 9 is an explanatory diagram showing the relationship between the material of the conductive parer film and the method of forming the metal cap film.
  • FIG. 10 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG.
  • FIG. 11 is a cross-sectional view of a main part showing a state where a paria insulating film is formed without forming the depression 21.
  • FIG. 12 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG.
  • FIG. 13 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG.
  • FIG. 14 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG.
  • FIG. 15 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG.
  • FIG. 16 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG.
  • FIG. 17 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG.
  • FIG. 18 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG.
  • FIG. 19 is a cross-sectional view of a main part of a semiconductor device of a comparative example.
  • FIG. 20 is a cross-sectional view of a main part of a semiconductor device in which the upper surface of a copper wiring is covered with a metal cap.
  • FIG. 21 is a sectional view of a main part of a semiconductor device according to an embodiment of the present invention.
  • FIG. 22 is a fragmentary cross-sectional view of a semiconductor device according to another embodiment of the present invention during a manufacturing step.
  • FIG. 23 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG.
  • FIG. 24 is an explanatory diagram showing the relationship between the material of the conductive barrier film and the method of forming the metal cap film when the via can be missed.
  • FIG. 25 is an explanatory diagram showing the relationship between the material of the conductive barrier film and the method of forming the metal cap film in the case where the via does not miss.
  • FIG. 26 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG.
  • FIG. 27 is a fragmentary cross-sectional view of a semiconductor device according to another embodiment of the present invention during a manufacturing step.
  • FIG. 28 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG.
  • FIG. 29 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG.
  • FIG. 30 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG.
  • FIG. 31 is a fragmentary cross-sectional view of a semiconductor device according to another embodiment of the present invention during a manufacturing step.
  • FIG. 32 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG.
  • FIG. 33 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG.
  • FIG. 34 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG.
  • FIG. 35 is a cross-sectional view of a principal part in a manufacturing step of a semiconductor device according to another embodiment of the present invention.
  • FIG. 36 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG.
  • FIG. 37 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG.
  • FIG. 38 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 37
  • FIG. 39 is a fragmentary cross-sectional view of a semiconductor device according to another embodiment of the present invention during a manufacturing step.
  • FIG. 40 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG.
  • FIG. 41 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG.
  • FIG. 42 is a cross-sectional view of a main part of a semiconductor device according to another embodiment of the present invention.
  • hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Also, hatching may be used even in a plan view so as to make the drawings easy to see. (Embodiment 1)
  • FIG. 1 is a cross-sectional view of a main part of a semiconductor device according to an embodiment of the present invention, for example, a manufacturing process of a metal insulator semiconductor field effect transistor (MISFET).
  • MISFET metal insulator semiconductor field effect transistor
  • an element isolation region 2 is formed on a main surface of a semiconductor substrate (semiconductor wafer) 1 made of p-type single crystal silicon or the like having a specific resistance of about 1 to: L 0 ⁇ cm.
  • the element isolation region 2 is made of silicon oxide or the like, and is formed by, for example, an STI (Shallow Trench Isolation) or LOCus (Local Oxidization of Silicon) method.
  • a p-type well 3 is formed in a region of the semiconductor substrate 1 where an n- channel MISFET is to be formed.
  • the p-type well 3 is formed, for example, by ion-implanting an impurity such as boron (B).
  • the gate insulating film 4 is made of, for example, a thin silicon oxide film, and can be formed by, for example, a thermal oxidation method.
  • a gate electrode 5 is formed on the gate insulating film 4 of the p-type well 3.
  • a polycrystalline silicon film is formed on the semiconductor substrate 1, phosphorus (P) or the like is ion-implanted into the polycrystalline silicon film to form a low-resistance n-type semiconductor film, and the polycrystalline silicon film is dry-etched.
  • the gate electrode 5 made of a polycrystalline silicon film can be formed.
  • an n-type semiconductor region 6 is formed by ion-implanting an impurity such as phosphorus into both sides of the gate electrode 5 of the P-type well 3.
  • a side wall spacer or a side wall 7 made of, for example, silicon oxide is formed on the side wall of the gate electrode 5.
  • the sidewall 7 can be formed, for example, by depositing a silicon oxide film on the semiconductor substrate 1 and anisotropically etching the silicon oxide film.
  • the n + type semiconductor region 8 (source, drain) 1 It is formed by ion-implanting impurities such as.
  • the n + type semiconductor region 8 has a higher impurity concentration than the n ⁇ type semiconductor region 6.
  • the gate electrode 5 and the n + type semiconductor region 8 are separated.
  • a silicide film 5a and a silicide film 8a are formed on the surface, respectively.
  • MISFET Metal Insulator Semiconductor Field Effect lransistor
  • an insulating film 1 1 made of silicon nitride or the like and an insulating film 11 made of silicon oxide or the like are sequentially deposited on the semiconductor substrate 1.
  • a contact hole 12 is formed in the upper portion of the n + type semiconductor region (source, drain) 8 by sequentially performing dry etching on the insulating film 11 and the insulating film 10.
  • a part of the main surface of the semiconductor substrate 1, for example, a part of the n + type semiconductor region 8 and a part of the gate electrode 5 are exposed.
  • a plug 13 made of tungsten (W) or the like is formed in the contact horn 12.
  • the plug 13 is formed, for example, by forming a titanium nitride film 13a as a parier film on the insulating film 11 including the inside of the contact hole 12 and then forming a tungsten film by a CVD (Chemical Vapor Deposition) method or the like.
  • a contact horn layer 12 is formed on the titanium nitride film 13a so as to fill it, and an unnecessary tungsten film and the titanium nitride film 13a on the insulating film 11 are removed by a CMP (Chemical Mechanical Polishing) method or an etch pack method. It can be formed by removing with a method such as.
  • CMP Chemical Mechanical Polishing
  • FIGS. 2 to 8 are cross-sectional views of main parts of the semiconductor device during the manufacturing process following that of FIG. In addition, in order to facilitate understanding, in FIGS. 2 to 8, portions corresponding to the structure below the insulating film 11 in FIG. 1 are omitted.
  • an insulating film (etching film) 14 is formed on the insulating film 11 in which the plug 13 is embedded.
  • the insulating film 14 is made of, for example, a silicon carbide (SiC) film.
  • SiC silicon carbide
  • Other materials of the insulating film 1 4, silicon nitride (S i x N y) film Etc. can also be used.
  • Insulating film 14 may be constituted by a laminated film of a silicon carbide (S i C) film and a nitride divorced (S i x N y) film.
  • the insulating film 14 When the insulating film 14 is formed by etching grooves and holes for wiring on the insulating film (interlayer insulating film) 15 on the upper layer, excessive digging may damage the lower layer or degrade the processing dimensional accuracy. Is formed in order to avoid That is, the insulating film 14 can function as an etching stopper when the insulating film (interlayer insulating film) 15 is etched. Next, an insulating film (interlayer insulating film) 15 is formed on the insulating film 14.
  • the insulating film 15 is preferably made of a low dielectric constant material (a so-called Low-K insulating film, Low-K # ⁇ ).
  • an insulating film having a low dielectric constant is an insulating film having a dielectric constant lower than that of a silicon oxide film (for example, TEOS (Tetraethoxysilane) oxide film) included in the passivation film.
  • Examples of the low dielectric constant material that can be used for the insulating film 15 include an organic polymer, an organic silica glass, FSG (SiO OF material, silicon oxide to which fluorine (F) is added), HSQ (hydrogen Silsesquioxane) materials, MSQ (methyl silsesquioxane) materials, porous HSQ materials, porous MSQ materials, or porous organic materials can be used.
  • FSG SiO OF material, silicon oxide to which fluorine (F) is added
  • HSQ hydrogen Silsesquioxane
  • MSQ methyl silsesquioxane
  • the insulating film 15 may be formed of a laminated film of the above-described low dielectric constant material film and the protective film formed thereon.
  • the protective film on the low dielectric constant material film is oxidized typified example if two Sani ⁇ silicon (S i O 2). Recon (S i O x) film or a silicon oxynitride (S i ON) film
  • the insulating film 15 can have functions such as securing mechanical strength, surface protection, and moisture resistance during the CMP process.
  • the low dielectric constant material film is made of, for example, a silicon oxide film (Si OF film) containing fluorine (F)
  • the protective film can also function to prevent diffusion of fluorine.
  • the formation of the protective film can be omitted.
  • the insulating film 15 is made of silicon oxide. It can also be formed by a single film of a capacitor film.
  • the insulating film 15 and the insulating film 14 are selectively removed to form a wiring groove (opening) 17 as a wiring opening.
  • the upper surface of the plug 13 is exposed at the bottom of the wiring groove 17.
  • the photoresist pattern (not shown) (and the anti-reflection film) used as an etching mask is removed by asking or the like.
  • the insulating film 15 is made of a material that can be damaged by oxygen plasma, for example, an organic polymer material or a porous organic material
  • the insulating film 15 is made of NH.
  • the photoresist pattern (and the anti-reflection film) can be removed by ashes while etching by reducing plasma processing such as 3 plasma processing or N 2 / H 2 plasma processing.
  • the entire surface on the main surface of the semiconductor substrate 1 (that is, on the insulating film 15 including the bottom of the wiring groove 17 and the side wall) is compared with, for example, a thickness of about 50 nm.
  • An electrically thin conductive palier film (parier conductor film) 18 is formed.
  • a sputtering method, a CVD method, an atomic layer deposition (ALD) method, or the like can be used.
  • the conductive barrier film 18 has, for example, a function of suppressing or preventing the diffusion of copper for forming a main conductor film described later, a function of improving the wettability of copper when the main conductor film is reflowed, or an adhesion of copper (copper film). It has functions to enhance the performance.
  • the material of the conductive barrier film 18 include a high-melting-point metal such as titanium (T i), tantalum (Ta) or tungsten (W), and an alloy film thereof (for example, titanium nitride (T iN), high melting point metal nitride such as tantalum (TaN) or tungsten nitride (WN), or silicon (Si) added to such high melting point metal nitride. Materials (eg, TiSiN, TaSiN, WSiN) can be used. Further, as the conductive barrier film 18, not only a single film of the above-mentioned material film but also a laminated film can be used.
  • a main conductor film (copper film) 19 made of relatively thick copper is formed on the conductive barrier film 18.
  • the main conductor film 19 can be formed by using, for example, a CVD method, a sputtering method, or a plating method.
  • the main conductor film 19 is a conductor film containing copper as a main component, for example, copper or a copper alloy (containing Cu as a main component, For example, Mg, Ag, Pd, Ti, Ta, A1, Nb, Zr or Zn are included.
  • a relatively thin copper (or copper alloy) seed film is formed on the conductive barrier film 18 by a sputtering method or a CVD method, and then, a relatively thick copper (or copper alloy) is formed on the seed film.
  • the main conductor film 19 made of copper alloy) can be formed by a plating method (electrolytic plating method). This seed film can function to improve the adhesion between the main conductor film 19 and the conductive barrier film 18. Thereafter, a heat treatment is performed on the semiconductor substrate 1 in a non-oxidizing atmosphere (for example, a hydrogen atmosphere) at about 475 ° C. to reflow the main conductor film 19, and copper is deposited inside the wiring groove 17. Embedded without gaps.
  • a non-oxidizing atmosphere for example, a hydrogen atmosphere
  • the main conductor film 19 and the conductive barrier film 18 are polished by, for example, a CMP method until the upper surface of the insulating film 15 is exposed. Unnecessary conductive barrier film 18 and main conductor film 19 on insulating film 15 (that is, outside wiring groove 17) are removed, and conductive barrier film 18 in wiring groove 17 as a wiring opening is removed.
  • a wiring (first layer wiring) 2 composed of a relatively thin conductive barrier film 18 and a relatively thick main conductor film 19 is formed. 0 is formed (embedded) in the distribution groove 17.
  • the formed wiring 20 is electrically connected to the ⁇ + type semiconductor region (source, drain) 8 and the gate electrode 5 via the plug 13. Unnecessary conductive barrier film 18 and main conductor film 19 can also be removed by etching (such as electrolytic etching).
  • the upper part of the main conductor film 19 remaining in the wiring groove 17 is removed, and the upper surface of the main conductor film 19 in the wiring groove 17 is It is recessed from the upper surface to form a recess (Recess) 21.
  • the upper surface of the main conductor film 19 is located lower than the upper surface of the insulating film 15. That is, the upper surface of the main conductor film 19 is lower than the upper surface of the insulating film 15.
  • the depression 21 can be formed by, for example, a technique of chemically etching.
  • a copper film (the main conductor film 1 9) with high selectivity i.e. the copper etching Etching is performed (selectively under conditions that increase the rate), and the etching time is adjusted to remove only the upper portion of the main conductor film 19, thereby forming the depression 21.
  • the other hand that forms the depression 21 As a method, when the main conductor film 19 and the conductive barrier film 18 are subjected to the CMP process (that is, in the step of FIG. 6), the recess 21 may be formed by performing over polishing. When the depression 21 is formed by overpolishing, dishing in which the upper surface of the main conductor film 19 has a dish shape is prevented.
  • a process for removing metal contamination on the insulating film 15 is performed. For example, removing the metal contamination on the insulating film 15 by cleaning the surface of the semiconductor substrate 1 (the surface of the main conductor film 19 and the insulating film 15) with a solution containing hydrogen fluoride (HF). Can be. If metal contamination occurs on the insulating film 15, the material of the metal cap film 22 may grow on the metal contaminant during the formation of the metal cap film 22 described later. By removing the metal contamination on the insulating film 15 as described above, the growth of the material of the metal cap film 22 on the insulating film 15 is suppressed or prevented, and the wiring is formed. It is possible to form the metal cap film 22 on the 20 (main conductor film 19) with higher selectivity and higher priority.
  • HF hydrogen fluoride
  • a treatment for reducing the activity of dangling pounds on the surface of the insulating film 15 is performed.
  • a treatment for reducing the activity of dangling pounds on the surface of the insulating film 15 is performed.
  • an annealing treatment heat treatment
  • an atmosphere containing a reducing gas for example, in an atmosphere containing hydrogen
  • the activity of dangling bonds on the surface of the insulating film 15 can be reduced.
  • a metal cap film (first cap conductor film) 22 is selectively grown or preferentially grown as a first metal cap film on the wiring 20 (main conductor film 19).
  • the metal cap film 22 is made of, for example, a tungsten (W) film or a tungsten alloy film (or a conductor film containing tungsten as a main component).
  • the metal cap film 22 can be formed by a selective tungsten CVD method or the like. For example, by using a CVD method using tungsten hexafluoride (WF 6 ) and hydrogen (H 2 ) gas, the upper surface of the wiring 20 (main conductor film 19) exposed from the insulating film 15 is formed.
  • metal cap film 22 by selective deposition of z film be able to.
  • a metal cap film 22 made of CoWP, CoWB, CoW, or the like is selectively formed on the upper surface of the wiring 20 (main conductor film 19) exposed from the insulating film 15 by an electroless plating method.
  • the material of the metal cap film 22 include tungsten (W), a tungsten alloy (a W alloy, an alloy containing W as a main component), cobalt (Co), a cobalt alloy (a Co alloy, a component mainly containing Co). Alloys), nickel (Ni) or nickel alloys (Ni alloys, Ni-based alloys).
  • W, WN, WNC or W-based materials can be used.
  • W, WN, WNC or W-based materials are Co, CoP, CoW, CoWP, CoWB, CoSnP, CoMoP, or NiMo, whose main component is copanoleto, Ni, NiW, NiP or the like can be used.
  • FIG. 9 is an explanatory diagram (table) showing the relationship between the material of the conductive barrier film 18 and the method of forming the metal cap film 22.
  • the conductive barrier film 18 is made of a refractory metal film (for example, a titanium (T i) film, a tantalum (Ta) film, a tungsten (W) film, or the like). Is more preferable.
  • a refractory metal nitride such as titanium nitride (TiN), tantalum nitride (TaN) or tungsten nitride (WN), or such a high-melting metal.
  • TiN titanium nitride
  • TaN tantalum nitride
  • WN tungsten nitride
  • a material obtained by adding silicon (S i) to the melting point metal nitride can be used.
  • the conductive barrier film 18 includes a refractory metal film (pure metal film) (for example, a single film of a tantalum (Ta) film or a tantalum (Ta) film and a nitride film).
  • a refractory metal film for example, a single film of a tantalum (Ta) film or a tantalum (Ta) film and a nitride film.
  • the metal cap film 22 is selectively formed on the wiring 20 by using the selective tungsten CVD method. It was found that tungsten (metal cap film 22) could grow abnormally on the exposed end of 18.
  • the conductive barrier film 18 contains a high-melting-point metal film (pure metal film)
  • the abnormal growth is caused by the reduction action of the high-melting-point metal (pure metal) by tungsten hexafluoride (WF 6 ) gas. Is preferentially reduced there, and it is thought that tungsten (metal cap film 22) grows preferentially.
  • WF 6 tungsten hexafluoride
  • tungsten (metal cap film 22) grows preferentially.
  • Abnormal growth reduces the power coverage of the insulating film 23 described later in the vicinity of the upper end of the wiring 20 (the end of the metal cap film 22), and withstands dielectric breakdown between adjacent wirings. May be reduced. For this reason, as described above, when the selective tungsten CVD method is used as the method of forming the metal cap film 22, it is more preferable that the conductive barrier film 18 does not include a high melting point metal film (pure metal film). Good.
  • the conductive barrier film 18 contains a high-melting-point metal film (pure metal film). It was also found that abnormal growth of tungsten (metal cap film 22) did not occur. For this reason, when the electroless plating method is used as the method for forming the metal cap film 22, the conductive barrier 18 may include a high melting point metal film. Therefore, when the electroless plating method is used as the method for forming the metal cap film 22, the conductive barrier film 18 may be made of, for example, titanium (T i), tantalum (T a), or tungsten (W).
  • High melting point metal or alloy film thereof for example, high melting point metal nitride such as titanium nitride (TiN), tantalum nitride (TaN) or tungsten nitride (WN), or such high melting point metal
  • TiN titanium nitride
  • TaN tantalum nitride
  • WN tungsten nitride
  • a single film or a stacked film of silicon (S i) added to a nitride can be used.
  • the metal cap film 22 is preferably formed by an electroless plating method.
  • the metal cap film 22 can be formed by selective tungsten CVD or electroless plating.
  • the thickness (deposition thickness) of the metal cap film 22 is preferably in the range of 2 to 20 nm.
  • the selectivity of the metal cap film 22 is easily broken, and the material of the metal cap film 22 may be deposited on the insulating film 15. There is. This may reduce the dielectric breakdown (TDDB) time between adjacent same-level interconnects.
  • the thickness of the metal cap film 22 is smaller than 2 nm, the effect obtained by forming the metal cap film 22 can be obtained, that is, as will be described later. As described above, the effect of improving the electromigration and stress migration characteristics of the wiring and improving the reliability of the buried copper wiring and the semiconductor device having the buried copper wiring may be reduced.
  • the depth of the depression 21 is substantially the same as the thickness of the metal cap film 22.
  • the height position of the upper surface of the metal cap film 22 (the height position in the direction perpendicular to the main surface of the semiconductor substrate 1)
  • the height position of the upper surface of the insulating film 15 (the height position in the direction perpendicular to the main surface of the semiconductor substrate 1) can be made substantially the same.
  • the upper surface of the metal cap film 22 and the upper surface of the insulating film 15 are substantially on the same plane, and the upper surface of the metal cap film 22 and the upper surface of the insulating film 15 are substantially flat. .
  • the selective growth of the metal cap film 22 is broken and the material of the metal cap film 22 (the conductor material, here, tungsten or (Tungsten alloy) may be deposited.
  • the conductor material deposited on the insulating film 15 may reduce the resistance to dielectric breakdown between adjacent wirings in the same layer. For this reason, after the formation of the metal cap film 22, the surface of the semiconductor substrate 1 is cleaned using a solution containing a small amount of hydrofluoric acid (hydrofluoric acid: HF), for example, and the entire region near the extreme surface of the insulating film 15 is cleaned.
  • hydrofluoric acid hydrofluoric acid
  • FIG. 10 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 8, and a portion corresponding to a structure below the insulating film 11 in FIG. 1 is omitted.
  • the insulating film 23 is made of, for example, a silicon carbonitride (SiCN) film and functions as a barrier insulating film for copper wiring.
  • the insulating film 23 suppresses or prevents copper in the main conductor film 19 of the wiring 20 from diffusing into the insulating film 24 or the like.
  • Insulation film 2 3 Other materials, for example, using a silicon nitride (S i x N y) film, a silicon carbide (S i C) film, a silicon oxynitride (S i ON) film or Sansumyi ⁇ silicon (S i OC) film Is also good.
  • the height position of the upper surface of the metal cap film 22 and the height position of the insulating film 15 are different without forming the depression 21 (the upper surface of the metal cap film 22). If the height position is higher than the height position of the upper surface of the insulating film 15), a step occurs between the upper surface of the metal cap film 22 and the upper surface of the insulating film 15, and when the insulating film 23 is formed. In addition, a step occurs in the insulating film 23 reflecting the step of the base.
  • FIG. 11 shows a state in which the insulating film 23 is formed when the height position of the upper surface of the metal cap film 22 and the height position of the insulating film 15 are different without forming the depression 21.
  • FIG. 11 It is a principal part sectional view, and corresponds to FIG. 10 of this Embodiment.
  • the force coverage or the step force rage of the insulating film 23 deteriorates. .
  • the step strength of the insulating film (cap insulating film) 23 is poor, the barrier property of copper (Cu) at the end of the wiring 20 is deteriorated, and the leakage current level between adjacent wirings increases, There is a possibility that insulation rupture resistance may be reduced (TDDB life may be shortened).
  • the depression 21 is formed before the formation of the metal cap film 22, and the depth of the depression 21 is made substantially the same as the thickness W of the metal cap film 22. Is preferred.
  • the upper surface of the metal cap film 22 and the upper surface of the insulating film 15 can be made substantially flat (substantially the same plane). Therefore, as shown in FIG. 10, a step is prevented from being formed in the insulating film 23, and a force paradigm of the insulating film 23 in a region near the upper end of the wiring 20 (end of the metal cap film 22) is prevented. And the resistance to rupture of insulation between adjacent wirings can be improved.
  • the copper (Cu) component of the wiring 20 may decrease and the resistance value of the wiring 20 may increase.
  • the thickness of the metal cap film 22 is relatively small, but since the insulating film 23 having copper parity is formed on the insulating film 15 and the metal cap film 22, Wiring 20 by this insulating film 23 In this case, sufficient barrier properties can be ensured, the leakage current level between the adjacent wirings 20 can be reduced, and the insulation breakdown resistance can be improved (the TDDB life can be increased).
  • FIGS. 12 to 18 are cross-sectional views of essential parts of the semiconductor device during the manufacturing process following FIG. In addition, for simplicity of understanding, also in FIGS. 12 to 18, parts corresponding to the structure below the insulating film 11 in FIG. 1 are not shown.
  • the insulating film (interlayer insulating film) 24, the insulating film (etching stopper film) 25, and the insulating film (interlayer insulating film) are formed on the insulating film 23.
  • the insulating film 24 can be formed of the same material (low dielectric constant material) as the insulating film 15, and the insulating film 25 can be formed of the same material as the insulating film 14 or the insulating film 23.
  • the insulating film 26 can be formed of the same material (low dielectric constant material) as the insulating film 15.
  • the insulating films 23 to 26 are dry-etched (selectively removed) by using a photolithography method or the like to reach the wiring opening, that is, the wiring 20.
  • a through hole or via (opening) 30 and a wiring groove (opening) 31 are formed.
  • all or part of the metal cap film 22 has been removed (etched) at the bottom of the via 30, exposing the upper surface of the main conductor film 19.
  • the wiring groove 31 is formed by selectively removing the insulating films 25 and 26, and the via 30 is formed at the bottom of the wiring groove 31 by the insulating films 23 and 24 and the metal cap film. It is formed by selectively removing a part of 22.
  • the via 30 penetrates from the bottom of the wiring groove 31 through the insulating films 23 and 24 and a part of the metal cap film 22 to reach the main conductor film 19, and is formed at the bottom of the via 30.
  • the main conductor film 19 is exposed.
  • the thickness of the metal cap film 22 is relatively small as described above, unlike the present embodiment, if the metal cap film 22 is formed so that the metal cap film 22 remains at the bottom of the via 30, the dry formation of the via 30 is performed. When the etching is performed, there is a possibility that a portion of the insulating film 23 on the metal cap film 22 remains at the bottom of the via 30 due to insufficient etching, and the via 20 does not reach the wiring 20. This lowers the reliability of the electrical connection between the upper wiring (wiring 35 described later) and the lower wiring (wiring 20).
  • the bottom of via 30 is also removed, and the dry etching for forming the via 30 is performed so that the main conductor film 19 is exposed at the bottom of the via 30. That is, over-etching is performed when the via 30 is formed, that is, until the main conductor film 19 is exposed, and the via 30 is formed from the bottom of the wiring groove 31 by the insulating films 23 and 24 and the metal cap film 22. To reach the main conductor film 19. For this reason, insufficient etching (the insulating film 23 remains at the bottom of the via 30) is unlikely to occur, and the via 30 can reliably reach the wiring 20. Therefore, the reliability of the electrical connection between the upper layer distribution (wiring 35 described later) and the lower layer distribution ⁇ (wiring 20) can be improved.
  • a cleaning process for removing etching residues on the bottom and side walls of the via 30 and an annealing process in an atmosphere containing a reducing gas are performed.
  • the etching residue on the bottom and side walls of the via 30 is removed and cleaned, and the copper oxide formed on the surface of the wiring 20 (main conductor film 19) exposed at the bottom of the via 30 is removed ( Thus, the exposed surface of the wiring 20 (main conductor film 19) can be cleaned (cleaned).
  • a second conductive layer 19 on the bottom of the via 30 (the main conductive layer 19) is covered with the second conductive layer 19 to cover the main conductive layer 19 exposed at the bottom of the via 30.
  • a metal cap film (second cap conductor film) 32 is selectively grown or preferentially grown as a metal cap film.
  • the metal cap film 32 is connected to the metal cap film 22, and the upper surface of the main conductor film 19 is covered with the metal cap film 22 and the metal cap film 32.
  • the metal cap film 32 can be formed of the same material as the metal cap film 22 and is made of, for example, a tungsten (W) film or a tungsten alloy film (or a conductor film containing tungsten as a main component).
  • the metal cap film 32 can be formed by the same method as the metal cap film 22.
  • the metal cap film 32 can be formed by a selective tungsten CVD method.
  • a tungsten film is selectively formed on the wiring 20 (main conductor film 19) exposed at the bottom of the via 30 by a CVD method using tungsten hexafluoride (WF 6 ) and hydrogen (H 2 ) gas.
  • WF 6 tungsten hexafluoride
  • H 2 hydrogen
  • the metal cap film 32 can be formed.
  • the metal cap film 32 made of Co WP, Co WB, or Co W is exposed at the bottom of the via 30 by the electroless plating method.
  • 20 (main conductor film 19) can also be selectively formed.
  • Examples of the material of the metal cap film 32 include tungsten (W), tungsten alloy (W alloy, alloy containing W as a main component), conort (Co), and cobalt alloy (Co alloy, containing Co as a main component). Gold), nickel (Ni) or a nickel alloy (Ni alloy, Ni-based alloy) can be used.
  • W is a material (main component).
  • W, WN, WNC Alternatively, Co, CoP, CoW, CoWP, CoWP, CoWB, CoSnP, CoMoP or Ni using cobalt as a material (main component) and Ni, NiW, NiP or the like can be used.
  • Thickness (deposition thickness) W 2 of the metal cap film 32 is preferably in the range of 2 to 20 nm. If the thickness W 2 of the metal cap film 32 is greater than 20 nm, the specific resistance of the W (tungsten) film is larger than that of the Cu (copper) film, so that the resistance is increased by increasing the W (tungsten) component. Alternatively, the coverage of the conductive barrier film 33 may decrease due to an increase in the surface irregularities of the W (tungsten) film (metal cap film 32). When the thickness W of the metal cap film 22 is smaller than 2 nm, the effect obtained by forming the metal cap film 22, that is, as described later, the electromigration of the wiring and the stress migration characteristics are improved and the embedding is improved. There is a possibility that the effect of improving the reliability of the embedded copper wiring and the reliability of the semiconductor device having the embedded copper wiring is reduced.
  • selectivity may be slightly broken. The reason is that even if the material (conductor material) of the metal cap film 32 is slightly deposited on the insulating film 26, the unnecessary conductor material on the insulating film 26 is removed in the CMP process for forming the wiring 35 described later. Because you can. For this reason, before forming the metal cap film 22, a process of removing metal contamination on the insulating film 15 by cleaning with a solution containing hydrogen fluoride (HF) was performed before forming the metal cap film 22, a process of removing metal contamination on the insulating film 15 by cleaning with a solution containing hydrogen fluoride (HF) was performed. However, it is also possible to omit the process of removing metal contamination on the insulating film 26 by cleaning with a solution containing hydrogen fluoride (HF). Thereby, the number of manufacturing steps can be reduced.
  • HF hydrogen fluoride
  • annealing treatment is performed in an atmosphere containing a reducing gas (for example, in an atmosphere containing hydrogen) to reduce dangling bonds on the surface of the insulating film 15.
  • a reducing gas for example, in an atmosphere containing hydrogen
  • this reducing gas It is more preferable to perform the annealing treatment in an atmosphere including the following before the metal cap film 32 is formed.
  • the surface of the semiconductor substrate 1 is washed with a solution containing a small amount of hydrofluoric acid (hydrofluoric acid: HF) to remove unnecessary conductors on the insulating film 15.
  • a solution containing a small amount of hydrofluoric acid hydrofluoric acid: HF
  • the cleaning treatment with a solution containing hydrofluoric acid was performed after the formation of the metal cap film 32. Can also be omitted. Thereby, the number of manufacturing steps can be reduced.
  • the metal cap film 32 After the formation of the metal cap film 32, as shown in FIG. 15, as shown in FIG. 15, the entire surface of the semiconductor substrate 1 (including the bottom and side walls of the via 3 ° and the bottom and side walls of the wiring groove 31) On the insulating film 26), a relatively thin conductive barrier film (paria conductor film) 33 having a thickness of, for example, about 50 nm is formed. Therefore, at the bottom of the via 30, the conductive barrier film 33 is formed on the metal cap film 32.
  • the conductive barrier film 33 can be formed by a method similar to that of the conductive barrier film 18 and is formed by using a sputtering method, a CVD method, an atomic layer deposition (ALD) method, or the like. be able to.
  • the conductive barrier film 33 like the conductive barrier film 18, has, for example, a function of suppressing or preventing the diffusion of copper for forming a main conductor film described later and a function of improving the wettability of copper during reflow of the main conductor film. Or, it has a function to enhance the adhesiveness of copper (copper film).
  • the same material as that of the conductive barrier film 18 can be used, for example, such as titanium (T i), tantalum (T a), or tungsten (W).
  • Refractory metal or its alloy film for example, refractory metal nitride such as titanium nitride (T iN), tantalum peroxide (T aN) or tungsten nitride (WN), or such refractory metal nitride
  • refractory metal nitride such as titanium nitride (T iN), tantalum peroxide (T aN) or tungsten nitride (WN), or such refractory metal nitride
  • a material obtained by adding silicon (Si) to an object for example, TiSiN, TaSiN, WSiN
  • the conductive barrier film 33 not only a single film of the above-mentioned material film but also a laminated film can be used.
  • a pre-treatment before the formation of the conductive barrier film 33 physical damping wiring is generally subjected to physical sputter etching using argon (Ar) ions. Since the metal cap film 32 at the bottom of the via 30 may be removed by performing physical sputter etching using argon (Ar) ions, in the present embodiment, before the conductive barrier film 33 is formed, As the treatment, it is more preferable to carry out a reactive plasma treatment in an atmosphere containing a reducing gas (for example, a hydrogen atmosphere). This prevents the metal cap film 32 at the bottom of the via 30 from being removed, and at the same time, reduces the surface of the metal cap film 32 so that the via 3 including on the metal cap film 32 can be reduced.
  • the conductive barrier film 33 can be accurately formed on the bottom surface and the side wall of the wiring groove 31.
  • a main conductor film (copper film) 34 made of relatively thick copper is formed on the conductive barrier film 33 (that is, on the semiconductor substrate 1).
  • the main conductor film 34 can be formed by a method similar to that of the main conductor film 19, and can be formed by using, for example, a CVD method, a sputtering method, or a plating method.
  • the main conductor film 34 can be formed of the same material as the main conductor film 19, and can be a conductor film containing copper as a main component, for example, copper or a copper alloy (containing Cu as a main component, for example, M g, Ag, Pd, Ti, Ta, Al, Nb, Zr, or Zn).
  • a relatively thin seed film made of copper (or copper alloy) is formed on the conductive barrier film 33 by a sputtering method or a CVD method, and then, a relatively thick copper (or copper alloy) is formed on the seed film.
  • the main conductor film 34 made of copper alloy or the like may be formed by a plating method (electrolytic plating method). This seed film can function to improve the adhesion between the main conductor film 34 and the conductive barrier film 33. Thereafter, the main conductor film 34 is reflowed by subjecting the semiconductor substrate 1 to a heat treatment in a non-oxidizing atmosphere (for example, a hydrogen atmosphere) at about 475 ° C. It is embedded in the wiring groove 31 without any gap.
  • a non-oxidizing atmosphere for example, a hydrogen atmosphere
  • the main conductor film 34 and the conductive barrier film 33 are polished by, eg, CMP until the upper surface of the insulating film 26 is exposed. Unnecessary conductive barrier film 33 and main conductor film 34 on insulating film 26 (ie, outside of via 30 and wiring groove 31) are removed, and conductive film in wiring groove 31 and via 30 is removed.
  • a wiring composed of a relatively thin conductive barrier film 33 and a relatively thick main conductor film 34 ( 2nd layer wiring) 35 is formed (buried in the wiring groove 31 and the via 30).
  • the wiring portion of the formed wiring 35 (the conductive barrier film 33 and the main conductor film 34 buried in the wiring groove 31) is a via portion of the wiring 35 (the conductive film buried in the via 30). It is electrically connected to the wiring 20 via the conductive barrier film 33 and the main conductor film 34). Further, when the material of the metal cap film 32 is deposited on the insulating film 26 due to the breakage of the selectivity, it can be removed together with the main conductor film 34 and the conductive barrier film 33 in this CMP step. . Unnecessary conductive barrier film 33 and main conductor film 34 can also be removed by etching (such as electrolytic etching) instead of CMP.
  • FIG. 18 After forming a depression similar to the depression 21 on the wiring 35, a metal cap film 42 as a first metal cap film is formed on the wiring 35 as a first metal cap film. 22 and then formed on the insulating film 26 in which the wiring 35 is embedded by the same process and material as the process of forming the insulating films 23 to 26.
  • (Paria insulating film) 43, insulating film (interlayer insulating film) 44, insulating film (etching stopper film) 45, and insulating film (interlayer insulating film) 46 are formed.
  • the insulating films 43 to 46 are dry-etched using a photolithography method or the like, so that the metal cap film 42 reaches the wirings 35 in the same manner as the vias 30 and the wiring grooves 31.
  • a via (opening) 50 and a wiring groove (opening) 51 are formed to penetrate and expose the main conductor film 34 of the wiring 35, and the wiring 35 (main conductor film) exposed at the bottom of the via 50 is formed.
  • a metal cap film 52 is formed thereon as a second metal cap film using the same material and method as the metal cap film 32.
  • a conductive barrier film (paria conductor film) 53 is formed on the conductive barrier film 18, 3.
  • the main conductor film 54 is formed by the same material and method as that of the main conductor film 53 so as to fill the via 50 and the wiring groove 51 on the conductive PAR film 53.
  • the unnecessary main conductor film 54 and conductive barrier film 53 on the insulating film 46 are removed by the CMP method to fill the via 50 and the wiring groove 51 and electrically connect to the wiring 35.
  • the connected wiring (third layer wiring) 55 is formed.
  • an upper layer wiring (fourth layer wiring) can be formed. Its illustration and description are omitted.
  • FIG. 19 is a cross-sectional view of a main part of the semiconductor device of the comparative example, and is a partially enlarged view of a region near the wirings 20 and 35.
  • the structure of FIG. 19 substantially corresponds to the case where the formation of the metal cap films 22, 32, 42, 52 is omitted in the wirings 20, 35 of the present embodiment.
  • buried copper wiring is formed by forming vias and wiring grooves in the insulating film and forming a conductive barrier film that is a copper (Cu) diffusion prevention film and a copper main conductor film that is the main wiring part.
  • the damascene method is adopted, which is embedded in the wiring groove, and unnecessary portions are removed by polishing (CMP) to form a distribution.
  • CMP polishing
  • the bottom and side surfaces of the copper main conductor film 19 are covered with the conductive barrier film 18, but the upper surface of the main conductor film 19 is made of copper.
  • the structure is covered with an insulating film 23 having high diffusion prevention performance.
  • the migration of copper (Cu) atoms is dominated by surface diffusion rather than diffusion inside the crystal.
  • the insulating film 23 over the wiring 20 Since the adhesiveness of the surface covered with is lower than that of the other surface, the interface between the insulating film 23 and the main conductor film 19 of the copper wiring can serve as a migration path for copper (Cu) atoms. The same applies to the wiring 35.
  • a phenomenon (SIV: Stress-Induced Voiding) occurs in which the resistance of the via portion of the copper wiring (the portion embedded in the via 30 of the wiring 35) increases due to the stress migration.
  • the failure phenomena due to stress migration include the mode in which copper (Cu) inside via 30 is sucked up by the upper wiring and voids are generated, and the interface between via 30 and wiring 20 as the lower copper wiring.
  • the use of tantalum (T a) as the conductive barrier film, improvement of the via shape, and, in some cases, the improvement of the coverage of the conductive barrier film and the copper seed film should be taken. Can be.
  • the reason for the stress gradient is that the via is subjected to a force in the direction of reducing the diameter of the via by the insulating film (paria insulating film) on the copper wiring, but the copper wiring (copper main conductor film) at the bottom of the via is This is because the reaction tends to expand the via, so that a large stress difference is generated between the bottom portion of the via and the underlying wiring portion.
  • the diffusion of the void means that copper (Cu) is relatively diffused in the opposite direction, and suppresses (eliminates) the copper (Cu) diffusion path. Is considered to be effective in preventing the occurrence of voids in the via bottom and the resulting defects.
  • FIG. 20 is a cross-sectional view of a main part of a semiconductor device in which the upper surface of a copper wiring is covered with a metal cap, and is a partially enlarged view of a region near the wirings 20 and 35. This corresponds to a structure in which metal cap films 22 and 42 are further formed on the structure of FIG.
  • the selectivity of the selective growth of the metal cap film 22 is not perfect, but is partially broken, and the metal cap film 22 is also formed on the surface of the insulating film 15 in which the wiring 20 is embedded. Metal material may grow. The same applies to the metal cap film 42. It is considered that the selectivity is broken because metal contamination on the surface of the insulating film causes the growth of the metal film (the metal material constituting the metal cap film) based on the metal contamination. The growth of the metal material that forms the metal cap film on the insulating film (breaking of selectivity) may reduce the dielectric breakdown resistance between adjacent wirings on the same layer and may reduce the reliability of semiconductor devices. .
  • the thickness of the metal cap film 22 is preferably 20 nm or less. The same applies to the metal cap film 42.
  • the thickness of the metal cap film 22 is reduced, the following problem occurs. That is, when the via 30 is formed (opened) on the wiring 20, the etching stop cannot be performed on the metal cap film 22, and the metal cap film 22 formed on the wiring 20 cannot be stopped. The point is that it is removed by etching.
  • the bottom of the via 30 there is no metal cap film on the main conductor film 19. If the volume (length, depth, depth) of the copper wiring is large, the total amount of internal voids will also increase, so a place without a metal cap film (the bottom of the via 30) is the only weak point. That is, it is the only part that is not covered with the conductive barrier film 18 and the metal cap film 22 and becomes a part that becomes a copper diffusion path (diffusion path).
  • the bottom of the via 30 that is not covered with the metal cap film 22 of the main conductor film 19 as described above has a copper diffusion path (diffusion path). ).
  • FIG. 21 is a cross-sectional view of a main part of the semiconductor device of the present embodiment, and is a partially enlarged view of a region near wirings 20 and 35.
  • the metal cap films 22, 32, 4 2 and 52 (the metal cap film 52 is not shown in FIG. 21).
  • the metal cap film 22 when forming (opening) the via 30 on the wiring 20, the metal cap film 22 is removed at the bottom of the via 30, but is exposed at the bottom of the via 30.
  • the wiring 20 can be formed with a material having good adhesion (conductive barrier film 18 and metal cap films 22 and 32). Completely cover the surface (top, bottom and side). Therefore, a portion (weak point, copper diffusion path) where the main conductor film 19 is exposed on the side of the wiring 20 is eliminated, and it is possible to prevent the void from being concentrated around the bottom of the via 30.
  • wiring 35 the same applies to wiring 35.
  • the metal cap film 22 is formed relatively thin on the wiring 20, the selective growth of the metal cap film 22 can be improved, and the dielectric breakdown resistance between adjacent wirings can be improved.
  • the via 30 is formed (opened) on the wiring 20 so as to remove the metal cap film 22 at the bottom of the via 30, the wiring 20 is surely exposed at the bottom of the via 30. Thus, the reliability of the electrical connection between the upper wiring and the lower wiring can be improved.
  • the present embodiment can be applied to any embedded copper wiring constituting the multilayer wiring structure.
  • any wiring layer for example, inferiority due to stress migration occurs.
  • the present embodiment can be applied only to a wiring layer having an easy structure. Defects due to stress migration are likely to occur in wiring layers with a structure in which relatively wide wiring parts are connected to via parts having relatively small diameters. In such a wiring structure, deterioration due to stress migration, such as an increase in resistance due to high temperature storage, is likely to occur.
  • the wiring layer having a structure in which inferiority due to such stress migration is likely to occur is a relatively lower wiring layer in the multilayer wiring structure, for example, a lower copper wiring (for example, wiring 20 or 3 5 ), A first metal film (metal cap film 22, 42) is formed on the copper wiring (wiring 20, 35), and a via () connected to the copper wiring is formed.
  • the first metal cap film is removed at the bottom of the via and a second metal cap film (metal cap films 32 and 52) is formed on the copper wiring exposed at the bottom of the via be able to.
  • FIGS. 22 and 23 are cross-sectional views of essential parts during a manufacturing process of a semiconductor device according to another embodiment of the present invention. Since the manufacturing steps up to FIG. 12 are almost the same as those in the first embodiment, the description is omitted here, and the manufacturing steps following FIG. 12 will be described. In FIGS. 22 and 23, the portions corresponding to the structure below the insulating film 11 in FIG. 1 are not shown.
  • the insulating films 23 to 26 are dry-etched by using a photolithography method or the like. Then, a wiring opening, that is, a through hole or via (opening) 30 reaching the wiring 20 and a wiring groove (opening) 31 are formed.
  • the via 30 shifts in the pattern of the wiring 20, that is, a so-called gap occurs due to misalignment of the exposure photomask in the photoresist pattern forming process.
  • a so-called gap occurs due to misalignment of the exposure photomask in the photoresist pattern forming process.
  • marginal design is used, or the design of the wiring pattern of the semiconductor device cannot be avoided.
  • it is necessary to increase the width of the wiring pattern but this leads to an increase in the size of the semiconductor device.
  • a metal cap film (conductive cap film) 32 is selectively grown or preferentially grown on the wiring 20 exposed at the bottom of the via 30.
  • the metal cap film 32 is made of, for example, a tungsten (W) film or a tungsten alloy film (or a conductor film containing tungsten as a main component).
  • the metal cap film 22 can be formed by a selective tungsten CVD method or the like. For example, by selectively depositing a tungsten film on the upper surface of the wiring 20 exposed at the bottom of the via 30 by a CVD method using tungsten hexafluoride (WF 6 ) and hydrogen (H 2 ) gas, The cap film 32 can be formed.
  • FIG. 24 is an explanatory diagram (table) showing the relationship between the material of the conductive barrier film 18 and the method of forming the metal cap film 32 in the case where the via 30 may be missed.
  • the conductive barrier film 18 includes a high melting point metal film (for example, a pure metal film such as a titanium (T i) film, a tantalum (T a) film, and a tundast (W) film),
  • a high melting point metal film for example, a pure metal film such as a titanium (T i) film, a tantalum (T a) film, and a tundast (W) film
  • tungsten (metal cap film 32) abnormally grows on the end of the conductive barrier film 18 exposed at the bottom of the via 30a. I will.
  • the tungsten hexafluoride (WF 6 ) gas is preferentially reduced there by the reducing action of the refractory metal (pure metal) and the tungsten grows preferentially.
  • Anomalous growth of rice tungsten lowers the force paradigm of the conductive barrier film 33 and the copper seed film formed on the conductive barrier film 33, so voids are generated inside the via 30a. There is a possibility that it will be. For this reason, in a layout rule that may cause the via 30 to be out of place, the selective tungsten CVD method is used as the method for forming the metal cap film 32.
  • the conductive barrier film 18 does not include a refractory metal film (pure metal film).
  • a high melting point metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), or the like.
  • TiN titanium nitride
  • TaN tantalum nitride
  • WN tungsten nitride
  • a material obtained by adding silicon (Si) to a high melting point metal nitride can be used.
  • the conductive barrier film 18 includes a high melting point metal film, that is, a single film of a high melting point metal or a high melting point metal film and a high melting point metal alloy film (for example, a high melting point metal nitride)
  • the layout rule for the formation of via 30 should be controlled so as not to cause the via 30 to be out of alignment, or the via 30 should be prevented from being out of alignment.
  • the metal cap film 32 is formed by an electroless plating method, while allowing. Even if the conductive barrier film 18 is exposed in the via 30 a where the opening has occurred, the conductive barrier film 18 can be formed in a high quality by forming the metal cap film 32 by the electroless plating method. Irrespective of whether a melting point metal film (pure metal film) is included or not, abnormal growth of tungsten (metal cap film 32) can be prevented.
  • the metal cap film 32 Is formed by an electroless plating method. If the conductive barrier film 18 does not include a high melting point metal film (pure metal film), a metal cap film 32 is selected. A tungsten CVD method or an electroless plating method is used. I do. Further, in a semiconductor device having a multilayer wiring structure, since a relatively lower wiring layer has a relatively narrow wiring interval and is likely to be out of shape, a metal cap film 32 as shown in FIG. 24 is formed. The law may be applied. Thereby, the reliability of the semiconductor device having the embedded copper wiring can be further improved.
  • FIG. 25 is an explanatory view (table) showing the relationship between the material of the conductive barrier film 18 and the method of forming the metal cap film 32 when the vias 30 do not miss. If the via 30 does not miss, the main conductor film 19 is exposed at the bottom of the via 30 and the conductive barrier film 18 is exposed as shown in FIG. 13 in the first embodiment. Therefore, the metal cap film 32 is selectively formed by either the tungsten CVD method or the electroless plating method.
  • the metal cap film 32 can be formed by a selective tungsten CVD method or an electroless plating method. Further, in a semiconductor device having a multilayer wiring structure, a relatively high wiring layer has a relatively wide wiring interval and is hard to be out of shape, so that a metal cap film 32 as shown in FIG. 25 is formed. What is necessary is to apply. As a result, the reliability of the semiconductor device having the embedded wiring can be further improved.
  • FIG. 26 is a cross-sectional view of a main part of another manufacturing step of the semiconductor device, following the step shown in FIG. In FIG. 26, portions corresponding to the structure below the insulating film 11 in FIG. 1 are not shown for easy understanding.
  • the steps after the step of forming the metal cap film 32 are almost the same as those in the first embodiment. That is, as shown in FIG. 26, the entire surface on the main surface of the semiconductor substrate 1 (that is, the bottom and side walls of the via 30 (via 30a) and the bottom and side walls of the wiring groove 31) are A conductive barrier film 33 and a main conductive film 34 are formed on the insulating film 26 including the insulating film 26, and the main conductive film 34 and the conductive barrier film 33 are formed by CMP until the upper surface of the insulating film 26 is exposed. Polishing is performed to form the wiring 35.
  • FIGS. 27 to 30 are main-portion cross-sectional views of a semiconductor device according to another embodiment of the present invention during the manufacturing steps thereof. Since the manufacturing steps up to FIG. 17 are substantially the same as those in the first embodiment, the description thereof is omitted here, and the manufacturing steps following FIG. 17 will be described. In FIGS. 27 to 30, portions corresponding to the structure below the insulating film 11 in FIG. 1 are not shown.
  • FIG. 27 After the structure of FIG. 17 is obtained in the same manner as in the first embodiment, the structure is shown in FIG. 27.
  • a metal cap film 42 is formed on the wiring 35 by the same material and method as the metal cap film 22.
  • the insulating film (paria insulating film) 43 and the insulating film (interlayer insulating film) are formed on the insulating film 26 in which the wirings 35 are embedded by the same process and material as the process of forming the insulating films 23 to 26 above. 4)
  • An insulating film (etching stopper film) 45 and an insulating film (interlayer insulating film) 46 are formed. Then, as shown in FIG.
  • the vias reaching the wirings 35 and exposing the main conductor film 34 of the wirings 35 are formed in the same manner as the vias 30 and the wiring grooves 31 as the wiring openings.
  • (Opening) 50 and wiring groove (opening) 51 are formed. Thereafter, as shown in FIG. 29, in the present embodiment, the metal cap film is not formed on the wiring 35 (main conductor film 34) exposed from the via 50 (that is, in the first embodiment described above).
  • the main conductor film 54 is formed by the same material and method as those of the films 18 and 33, and the main conductor film 54 is filled on the conductive barrier film 53 so as to fill the via 50 and the wiring groove 51. It is formed by the same material and method as described above. Then, as shown in FIG. 30, the unnecessary main conductor film 54 and the conductive barrier film 53 on the insulating film 46 are removed by the CMP method to fill the via 50 and the wiring groove 51 and to perform wiring. Wiring (third layer wiring) 55 electrically connected to 35 is formed.
  • the metal cap film 52) may be omitted.
  • the volume of the lower wiring it means that the width and depth of the wiring are approximately equal to or smaller than the crystal grain size of copper (Cu) constituting the main conductor film.
  • the crystal grain size of copper (Cu) is, for example, about 1.5 ⁇ .
  • the metal cap film (here, the metal cap film 52) at the bottom of the via 50) can be omitted.
  • the number of manufacturing steps can be reduced and the manufacturing process of the semiconductor device can be simplified, and the resistance of the via portion of the wiring can be prevented from increasing.
  • the formation of the metal cap film at the bottom of the via 50 is omitted, as a pretreatment before the formation of the conductive barrier film 53, physical sputter etching using argon (Ar) ions or reduction Reactive plasma treatment in an atmosphere containing a gas (eg, a hydrogen atmosphere) can be used.
  • FIG. 31 to 34 are main-portion cross-sectional views of a semiconductor device according to another embodiment of the present invention during the manufacturing steps thereof. Since the manufacturing steps up to FIG. 17 are substantially the same as those in the first embodiment, the description thereof is omitted here, and the manufacturing steps following FIG. 17 will be described. In FIG. 31 to FIG. 34, portions corresponding to the structure below the insulating film 11 in FIG. 1 are not shown.
  • the insulating films 23 to 2 are embedded on the insulating film 26 in which the wirings 35 are embedded.
  • the wiring 35 is embedded without forming a metal cap film on the wiring 35 (that is, omitting the metal cap film 42 in the first embodiment).
  • the insulating films 43 to 46 are formed on the insulating film 26 thus formed. Then, as shown in FIG. 32, as the wiring opening, the via () that reaches the wiring 35 and exposes the main conductor film 34 of the wiring 35 in the same manner as the via 30 and the wiring groove 31. An opening) 50 and a wiring groove (opening) 51 are formed. Thereafter, as shown in FIG. 33, in the present embodiment, the metal cap film is not formed on the wiring 35 (main conductor film 34) exposed from the via 50 (that is, in the above-described embodiment). 1, the conductive cap film 52 is omitted, and the conductive barrier film 53 is formed on the semiconductor substrate 1 (on the insulating film 46 including the bottom and side walls of the via 50 and the wiring groove 51).
  • the main conductor film 54 is formed by the same material and method as those of 18 and 33, and the main conductor film 54 and the main conductor films 19 and 34 are filled on the conductive barrier film 53 so as to fill the via 50 and the wiring groove 51. It is formed using the same materials and techniques. Then, as shown in FIG. 34, the unnecessary main conductor film 54 and the conductive barrier film 53 on the insulating film 46 are removed by the CMP method to fill the via 50 and the wiring groove 51. And wiring electrically connected to wiring 35 (third layer wiring H) Form 5 5
  • the metal cap film (here, the metal cap film 42) of the wiring 35) and the metal cap film (here, the metal cap film) at the bottom of the via (here, the via 50) that connects to (or reaches) the underlying wiring 5 2) can also be omitted.
  • the number of manufacturing steps can be reduced, the manufacturing steps of the semiconductor device can be simplified, and an increase in the resistance of the via portion of the wiring can be prevented.
  • 35 to 38 are main-portion cross-sectional views of a semiconductor device according to another embodiment of the present invention during the manufacturing steps thereof. Since the manufacturing steps up to FIG. 17 are substantially the same as those in the first embodiment, the description thereof is omitted here, and the manufacturing steps following FIG. 17 will be described. Note that, also in FIGS. 35 to 38, parts corresponding to the structure below the insulating film 11 in FIG. 1 are not shown. Note that, in the present embodiment, the description will be made assuming that the wiring 35 is a wiring in a layer relatively higher than the semiconductor device.
  • FIG. 17 After the structure shown in FIG. 17 is obtained in the same manner as in the first embodiment, as shown in FIG. 35, a recess similar to the recess 21 is formed in the wire 35, and then the wire 35 A metal cap film 42 is formed thereon by the same material and method as the metal cap film 22. Then, on the insulating film 26 in which the wirings 35 are embedded, the insulating film (paria insulating film) 63 and the insulating film ( An interlayer insulating film) 64 is formed.
  • through holes or vias 65 reaching the wirings 35 are formed by, for example, dry etching the insulating films 63 and 64 using a photolithography method.
  • all or a part of the metal cap film 42 has been removed (etched), and the upper surface of the main conductor film 34 is exposed. As a result, the structure shown in FIG. 35 is obtained.
  • a titanium (Ti) film and a titanium nitride (TiN) film are formed on the entire surface on the main surface of the semiconductor substrate 1 (that is, on the insulating film 64 including the bottom of the via 65 and the side wall).
  • a conductive barrier film 66 made of a laminated film of the above is formed.
  • the conductive barrier film 66 can be formed by a sputtering method, a CVD method, an atomic layer deposition (ALD) method, or the like.
  • ALD atomic layer deposition
  • a tungsten film 67 is formed on the conductive barrier film 66 so as to fill the via 65 by a CVD method or the like, and the unnecessary tungsten film 67 and the conductive barrier film 66 on the insulating film 64 (that is, outside the via 65) are formed.
  • a plug 68 made of a conductive film 66 and a tungsten film 67 filling the via 65 is formed. As a result, the structure shown in FIG. 36 is obtained.
  • a conductive film 69a composed of a laminated film of a titanium (Ti) film and a titanium nitride (TiN) film is formed by, for example, a sputtering method.
  • a conductive film 69c formed in this order.
  • a material of the conductive film 69b an aluminum alloy containing copper (Cu) at about 0.5% by weight, for example, can be used.
  • the conductor films 69a and 69c are laminated films in which the lower layer is a titanium film and the upper layer is a titanium nitride film.
  • the conductor films 69a and 69c can function as a parier conductor film, and the conductor film 69c can also function as an anti-reflection film in a photolithographic process.
  • the laminated structure (laminated film) is dry-etched and processed into a predetermined pattern to form wiring (aluminum wiring) 69.
  • wiring (aluminum wiring) 69 As a result, the structure shown in FIG. 37 is obtained.
  • the wiring 69 is electrically connected to the wiring 35 via a plug 68.
  • the wiring 69 serving as this upper wiring can function as a pad (PAD) electrode.
  • an insulating film 70 is formed on the insulating film 64 so as to cover the wiring 69 as a protection layer of the wiring 69 as a pad electrode.
  • the insulating film 70 includes, for example, at least one material film selected from a silicon oxide film (TEOS oxide film), a silicon nitride (SIN) film, a SOG (Spin On Glass) film, and the like. It is formed of a single film or a laminated film.
  • a via 71 is formed in the insulating film 70 by, for example, etching the insulating film 70 using a photolithography method.
  • the arrangement as a pad electrode, ⁇ 69, is exposed.
  • an extraction electrode is connected to the wiring 69 exposed from the via 71, and the semiconductor device can be integrated with the package.
  • FIG. 39 to FIG. 41 are cross-sectional views of main parts during a manufacturing process of a semiconductor device according to another embodiment of the present invention. Since the manufacturing steps up to FIG. 17 are almost the same as those of the fifth embodiment, the description is omitted here, and the manufacturing steps following FIG. 17 will be described. In FIG. 39 to FIG. 41, portions corresponding to the structure below the insulating film 11 in FIG. 1 are not shown. Note that, in the present embodiment, the description will be made assuming that the wiring 35 is a wiring in a layer relatively higher than the semiconductor device.
  • a depression similar to the depression 21 is formed in the arrangement 35 and the wiring is formed.
  • a metal cap film 42 is formed on 35 using the same material and method as the metal cap film 22. Then, on the insulating film 26 in which the wirings 35 are embedded, the insulating film (paria insulating film) 63 and the insulating film ( An interlayer insulating film) 64 is formed.
  • through holes or vias 85 reaching the wirings 35 are formed by, for example, dry etching the films 6 3 and 6 4 using photolithography. o At this time, at the bottom of the via 85, all or part of the metal cap film 42 has been removed (etched), and the upper surface of the main conductor film 34 is exposed.
  • Conductive film 89 a composed of a laminated film of a film and a titanium nitride (TiN) film, and relatively thick aluminum (A 1) alone or mainly containing aluminum such as an aluminum alloy
  • a conductor film (aluminum film) 89b and a conductor film 89c composed of a laminated film of a titanium (Ti) film and a titanium nitride (TiN) film are sequentially formed.
  • the material film formed first after the formation of the via 85 be a titanium (T i) film in order to enhance the adhesion (adhesion) of the underlying copper to the main conductor film 34.
  • the conductor films 89a and 89c are laminated films in which the lower layer is a titanium film and the upper layer is a titanium nitride film.
  • As a material of the conductor film 89b an aluminum alloy containing, for example, about 0.5% by weight of copper (Cu) can be used. However, if aluminum is a main component, Cu and other additives are used.
  • An object (such as Si) may be contained in an arbitrary ratio.
  • the laminated structure (laminated film) of the conductor films 89a, 89b, and 89c is dry-etched using a photolithography method or the like into a predetermined pattern.
  • the wiring 89 is electrically connected to the wiring 35 via a portion embedded in the via 85.
  • the insulation of the fifth embodiment is covered on the insulating film 64 so as to cover the wiring 89.
  • An insulating film 90 is formed using the same material as the film 70.
  • a via (opening) 91 is formed in the insulating film 90 by, for example, etching the insulating film 90 using a photolithography method.
  • the arrangement 89 as a pad electrode layer is exposed.
  • a lead electrode is connected to a wiring 89 serving as a pad electrode layer exposed from the via 91, and the semiconductor device can be integrated with the package.
  • FIG. 42 is a cross-sectional view of a main part of a semiconductor device according to another embodiment of the present invention.
  • the semiconductor device of the present embodiment has a multilayer wiring structure.
  • an element isolation region 102 and a p-type region (p-type or n-type p-type region) 103 are formed in the semiconductor substrate 101, and a third insulating film 104,
  • a plurality of MI SFETs (n-channel or P-channel MI SFETs) 109 having a gate electrode 105 and a semiconductor region (n-type or p-type semiconductor region) 108 as a source and a drain are formed. .
  • the wiring 1 15 and the sixth-layer wiring 1 16 are formed on the semiconductor substrate 101 by an insulating film 122 as an interlayer insulating film, an insulating film 122 as an etching stopper film, and an insulating film as a paria insulating film. It is formed in a laminated structure of a film 123 and an insulating film 124 as a protective film.
  • the first-layer wiring 111 electrically connected to the MI SFET 109 via the plug 131 is formed by a damascene method (single damascene method).
  • the wiring 111 is a tungsten wiring. Therefore, the first-layer wiring 111 is formed by forming a tungsten film and a barrier film such as titanium nitride in the wiring groove formed in the insulating films 122 and 122, and forming unnecessary tungsten outside the wiring groove. It is formed by removing the film and the titanium nitride film by a CMP method. In the Tungsten hot spring, the copper diffusion phenomenon does not occur because there is no copper film. Therefore, it is not necessary to form a metal cap film on the upper surface of the first layer wiring 111 made of tungsten wiring.
  • the second-layer wiring 112 to the fifth-layer wiring 115 are formed by a damascene method (in the example of FIG. 42, a dual damascene method). Therefore, each of the second-layer wiring 112 to the fifth-layer wiring 115 has a conductive parier film and a copper main conductor film in wiring openings (wiring grooves and vias) formed in the insulating film. Is formed by removing unnecessary main conductor films and conductive barrier films outside the wiring openings by the CMP method.
  • the steps from the second layer wiring 112 to the third layer wiring 113 of the second layer wiring 112 to the fifth layer wiring 115 are the same as the steps from the wiring 35 to the wiring 55 in the first embodiment. It is formed in the same way as the process up to.
  • the structure of the region 132a is similar to the structure of the region near the upper surface of the wiring 35 of the first embodiment as shown in FIG. It is. For this reason, a metal cap film 112 a corresponding to the metal cap film 42 is formed on the second-layer wiring 112, and a metal cap film 111 corresponding to the metal cap film 52 is further formed. 2 b force is formed on the copper main conductor film of the second layer wiring 112 exposed at the bottom of the via for forming the third layer wiring 113.
  • the second-layer wiring 112 which is a relatively lower wiring layer, has a relatively narrow wiring interval, in the region 132b, as in the case of the via 30a according to the second embodiment described above, a gap occurs. ing.
  • Embodiment 2 (FIG. 24) to the method of forming the metal cap film 112b.
  • the steps from the third layer wiring 113 to the fourth layer wiring 114 are formed in the same manner as the steps from the wiring 35 to the wiring 55 in the fourth embodiment. That is, the structure of the region 133 is the same as the structure of the region near the upper surface of the wiring 35 of the fourth embodiment as shown in FIG. Therefore, no metal cap film is formed on the third layer wiring 113.
  • the steps from the fourth layer wiring 114 to the fifth layer wiring 115 are formed in the same manner as the steps from the wiring 35 to the wiring 55 in the first embodiment. That is, the structure of the region 134 is the same as the structure of the region near the upper surface of the wiring 35 of the first embodiment as shown in FIG. Therefore, a metal cap film 114 a corresponding to the metal cap film 42 is formed on the fourth layer wiring 114, and a metal cap film 111 corresponding to the metal cap film 52 is further formed. 4 b force Fifth layer wiring 111 is formed on the copper main conductor film of fourth layer wiring 114 exposed at the bottom of via. Further, since the fourth-layer wiring 114, which is a relatively upper wiring layer, has a relatively large wiring interval, there is no gap as in the via 30a of the second embodiment.
  • the fifth-layer wiring 115 is electrically connected to a sixth-layer wiring 116 which is an aluminum wiring via a plug 116a.
  • the fifth-layer wiring 1 15, plug 1 16 a and sixth-layer wiring 1 16 are formed in the same manner as the wiring 35, plug 68 and wiring 69 of the fifth embodiment. That is, the structure of the region 135 is the same as the structure of the region near the upper surface of the wiring 35 of the fifth embodiment as shown in FIG. For this reason, a metal cap film 115 a corresponding to the metal cap film 42 is formed on the fifth layer wiring 115.
  • a lead electrode (for example, a bump electrode) 144 is formed on the top.
  • the multilayer wiring structure of the semiconductor device can be formed by appropriately combining the first to sixth embodiments.
  • the semiconductor device having the MISFET has been described.
  • the present invention is not limited to this, and is applicable to various semiconductor devices having a wiring including a main conductor film containing copper as a main component. can do.
  • the semiconductor device of the present invention is effective when applied to a semiconductor device having embedded copper wiring.

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Abstract

A wiring groove is formed in insulating films (14, 15). A conductive barrier film (18) and a copper main conductive film (19) are formed over the insulating film (15) including the bottom and side wall of the wiring groove. The unnecessary part is removed by a CMP method to form a wiring (20). A metal cap film (22) of tungsten is formed over the main conductive film (19) by selective growing. Insulating films (23 to 26) are formed over the insulting film (15) where the wiring (20) is buried. A via (30) which extends through the metal cap film (22) to expose the main conductive film (19) is formed, and a wiring groove (31) is formed. A metal cap film (32) of tungsten is formed over the main conductive film (19) exposed at the bottom of the via (30) by selective growing. A conductive barrier film (33) and a copper main conductive film (34) are formed over the insulting film (26) including the inside of the via (30) and the inside of the wiring groove (31). The unnecessary part is removed by a CMP method to form a wiring (35).

Description

技術分野 Technical field
本発明は、 半導体装置に関し、 特に、 銅を主成分とする主導体膜を含む埋込配 線を有する半導体装置に適用して有効な技術に関する。  The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device having a buried wiring including a main conductor film containing copper as a main component.
明 背景技術 田  Akira Background technology
半導体装置の素子間は、例えば多層配線構造により結線され回路が構成される。 微細化に伴!、配線構造として埋込配線構造が開発されている。 埋込配線構造は、 例えば絶縁膜に形成された配線溝ゃ孔 （ビア） などのような配線開口部内に、 ダ マシン （Damascene) 技術、 シングルダマシン （Single- Damascene) 技術おょぴデ ユアノレダマシン （Dual-Damascene) 技術によって、 配線材料を埋め込むことで形 成される。  The elements of the semiconductor device are connected by, for example, a multilayer wiring structure to form a circuit. With miniaturization, embedded wiring structures have been developed as wiring structures. The buried wiring structure uses damascene (Single-Damascene) technology and single-damascene technology in wiring openings such as wiring grooves and holes (vias) formed in the insulating film. It is formed by embedding wiring material using Dual-Damascene) technology.
特開 2002— 343859号公報には、 銅配線のビア部でのボイドの発生を 防止するために上層配線とパリア金属の密着性とパリア金属と下層配線の密着性 を上げるために、 W— WN—Wまたは T a— T aN— T a構造にする開示がある (特許文献 1参照)。 また、特開 2003 _ 68848号公報には、 ビア部におい て下層銅配線上に選択的に Wを成長させた構造の開示がある （特許文献 2参照)。 また、 特開 2001— 319928号公報には、 下層配線の C u上に Wを選択成 長させて Wプラグをその W選択成長膜の上に形成する開示がある （特許文献 3参 照)。 また、特開 2002-64138号公報には、 プラグと下層配線の接触面積 を大きくするために下層配線の表面をオーバーェツチングした後に" Wブラグを形 成する開示がある （特許文献 4参照)。  Japanese Patent Application Laid-Open No. 2002-343859 discloses W—WN to improve the adhesion between the upper layer wiring and the barrier metal and the adhesion between the barrier metal and the lower layer wiring in order to prevent the generation of voids in the via portion of the copper wiring. —W or Ta—TaN—Ta structure is disclosed (see Patent Document 1). Japanese Patent Application Laid-Open No. 2003-68848 discloses a structure in which W is selectively grown on a lower copper wiring in a via portion (see Patent Document 2). Also, Japanese Patent Application Laid-Open No. 2001-319928 discloses that W is selectively grown on Cu of a lower layer wiring and a W plug is formed on the W selective growth film (see Patent Document 3). Further, Japanese Patent Application Laid-Open No. 2002-64138 discloses a technique of forming a "W-blag" after over-etching the surface of the lower wiring in order to increase the contact area between the plug and the lower wiring (see Patent Document 4). .
【特許文献 1】 特開 2002-343859号公報  (Patent Document 1) Japanese Patent Application Laid-Open No. 2002-343859
【特許文献 2】 特開 2003— 68848号公報  [Patent Document 2] JP-A-2003-68848
【特許文献 3】 特開 2001— 319928号公報  [Patent Document 3] Japanese Patent Application Laid-Open No. 2001-319928
【特許文献 4】 特開 2002-64138号公報 発明の開示 [Patent Document 4] Japanese Patent Application Laid-Open No. 2002-64138 Disclosure of the invention
本発明者の検討によれば、 次のような問題があることを見出した。  According to the study by the present inventors, it has been found that there are the following problems.
銅を主成分とする埋込銅配線構造においては、 ス トレスマイグレーションなど により不良が発生することがある。 例えば、 高温放置試験のように埋込銅配線へ 熱ストレス負荷をかけると、 埋込銅配線の電気抵抗が上昇する。 これは、 下層埋 込銅配線の上面と上層埋込銅配線のビア部 （ビア埋込部） との間に空隙またはボ ィドが形成され、 下層配線と上層配線の間の接続面積が低減するためである。 こ のような現象は、 埋込銅配線を有する半導体装置の信頼性を低減させる。  In a buried copper wiring structure containing copper as a main component, failure may occur due to stress migration or the like. For example, when a thermal stress load is applied to the buried copper wiring as in a high-temperature storage test, the electrical resistance of the buried copper wiring increases. This is because voids or voids are formed between the upper surface of the lower buried copper wiring and the via part (via buried part) of the upper buried copper wiring, and the connection area between the lower wiring and the upper wiring is reduced. To do that. Such a phenomenon reduces the reliability of the semiconductor device having the embedded copper wiring.
本発明の目的は、 埋込銅配線を有する半導体装置の信頼性を向上させることが できる技術を提供することにある。  An object of the present invention is to provide a technology capable of improving the reliability of a semiconductor device having embedded copper wiring.
本発明の前記ならびにその他の目的と新規な特徴は、 本明細書の記述および添 付図面から明らかになるであろう。  The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、 次のとおりである。 .  The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. .
本発明は、 下層銅配線上にキャップ導体膜を形成し、 下層銅配線に接続するビ ァ形成時にビア底部でそのキヤップ導体膜を除去し、 ビア底部の下層銅配線上に 再度キヤップ導体膜を形成した後に、 上層銅配線形成用のパリア導体膜と銅を主 成分とする導体膜とを形成したものである。  According to the present invention, a cap conductive film is formed on a lower copper wiring, the cap conductive film is removed at the bottom of the via when forming a via connected to the lower copper wiring, and the cap conductive film is formed again on the lower copper wiring at the bottom of the via. After formation, a barrier conductor film for forming an upper copper wiring and a conductor film containing copper as a main component are formed.
また、 本発明は、 半導体基板と、 半導体基板上に形成された第 1絶縁膜と、 第 1絶縁膜に形成された第 1開口部と、 第 1開口部の側壁および底部上に形成され た第 1パリァ導体膜と第 1開口部内を埋めるように第 1パリァ導体膜上に形成さ れた銅を主成分とする第 1導体膜とを有する第 1配線と、 第 1導体膜上に形成さ れた第 1キヤップ導体膜と、 第 1絶縁膜および第 1キヤップ導体膜上に形成され た第 2絶縁膜と、 第 2絶縁膜に形成されその底部で第 1導体膜を露出する第 2開 口部と、 第 2開口部の底部で露出する第 1導体膜上に形成された第 2キャップ導 体膜と、 第 2開口部の側壁上と底部の第 2キヤップ導体膜上に形成された第 2パ リァ導体膜と、 第 2開口部内を埋めるように第 2パリア導体膜上に形成された銅 を主成分とする第 2導体膜とを有するものである。 更に、 本願に記載されたその他の発明の概要を箇条書きにして以下に示す。 す なわち、 The present invention also provides a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a first opening formed in the first insulating film, and formed on a side wall and a bottom of the first opening. A first wiring having a first parier conductive film and a first conductive film containing copper as a main component formed on the first parier conductive film so as to fill the inside of the first opening; and formed on the first conductive film. A first cap conductive film, a second insulating film formed on the first insulating film and the first cap conductive film, and a second conductive film formed on the second insulating film and exposing the first conductive film at the bottom thereof. An opening; a second cap conductive film formed on the first conductive film exposed at the bottom of the second opening; and a second cap conductive film formed on the side wall of the second opening and on the bottom of the second cap conductive film. A second pariconductor film formed on the second pariconductor film so as to fill the second opening, And it has a. Further, the outlines of other inventions described in the present application are shown below in a bulleted list. That is,
項 1 ： ( a ) 半導体基板を準備する工程、 Item 1: (a) a step of preparing a semiconductor substrate,
( b ) 前記半導体基板上に第 1絶縁膜を形成する工程、  (b) forming a first insulating film on the semiconductor substrate,
( c ) 前記第 1絶縁膜に第 1開口部を形成する工程、  (c) forming a first opening in the first insulating film,
( d ) 前記第 1開口部の側壁および底部上に形成された第 1パリア導体膜と、 前 記第 1開口部内を埋めるように前記第 1パリァ導体膜上に形成された銅を主成分 とする第 1導体膜とを有する第 1配線を形成する工程、  (d) a first barrier conductor film formed on the side wall and the bottom of the first opening, and copper formed on the first pariconductor film so as to fill the first opening; Forming a first wiring having a first conductor film to be formed,
( e ) 前記第 1配線上に第 1キヤップ導体膜を形成する工程、  (e) forming a first cap conductor film on the first wiring,
( f ) 前記第 1絶縁膜および前記第 1キヤップ導体膜上に第 2絶縁膜を形成する 工程、  (f) forming a second insulating film on the first insulating film and the first cap conductor film,
( g ) 前記第 2絶縁膜および前記第 1キャップ導体膜を選択的に除去して、 その 底部で前記第 1導体膜を露出する第 2開口部を形成する工程、  (g) a step of selectively removing the second insulating film and the first cap conductive film to form a second opening exposing the first conductive film at the bottom thereof;
( h ) 前記第 2開口部の底部で露出する前記第 1導体膜上に第 2キヤップ導体膜 を形成する工程、  (h) forming a second cap conductor film on the first conductor film exposed at the bottom of the second opening,
( i ) 前記第 2開口部の内部を含む前記第 2絶縁膜上に第 2パリァ導体膜を形成 する工程、  (i) forming a second parier conductor film on the second insulating film including the inside of the second opening;
( j ) 前記第 2開口部内を埋めるように前記第 2パリァ導体膜上に銅を主成分と する第 2導体膜を形成する工程、  (j) forming a second conductive film containing copper as a main component on the second parier conductive film so as to fill the inside of the second opening;
を有することを特徴とする半導体装置の製造方法。  A method for manufacturing a semiconductor device, comprising:
項 2 ：項 1記載の半導体装置の製造方法において、 Item 2: The method for manufacturing a semiconductor device according to Item 1,
前記 ( d ) 工程は、  The step (d) includes:
( d 1 ) 前記第 1開口部の内部を含む前記第 1絶縁膜上に前記第 1パリァ導体膜 を形成する工程、  (d1) forming the first pariconductor film on the first insulating film including the inside of the first opening;
( d 2 ) 前記第 1開口部内を埋めるように前記第 1パリア導体膜上に銅を主成分 とする前記第 1導体膜を形成する工程、  (d2) forming the first conductor film containing copper as a main component on the first barrier conductor film so as to fill the first opening;
( d 3 ) 前記第 1開口部外部の前記第 1導体膜および前記第 1パリァ導体膜を除 去して前記第 1開口部内に前記第 1配線を形成する工程、  (d3) forming the first wiring in the first opening by removing the first conductor film and the first parer conductor film outside the first opening;
を有することを特徴とする半導体装置の製造方法。 項 3 ：項 1記載の半導体装置の製造方法において、 A method for manufacturing a semiconductor device, comprising: Item 3: In the method for manufacturing a semiconductor device according to Item 1,
前記 ( j ) 工程後に、 更に、  After the step (j),
( k ) 前記第 2開口部外部の前記第 2導体膜および前記第 2パリア導体膜を除去 する工程、  (k) removing the second conductor film and the second barrier conductor film outside the second opening;
を有することを特徴とする半導体装置の製造方法。  A method for manufacturing a semiconductor device, comprising:
項 4 ：項 1記載の半導体装置の製造方法において、 Item 4: The method for manufacturing a semiconductor device according to Item 1,
前記 ( e ) 工程では、 前記第 1配線上に前記第 1キャップ導体膜を選択成長ま たは優先成長させることにより、 前記第 1キヤップ導体膜を形成することを特徴 とする半導体装置の製造方法。  In the step (e), the first cap conductor film is formed by selectively or preferentially growing the first cap conductor film on the first wiring. .
項 5 ：項 1記載の半導体装置の製造方法において、 Item 5: The method for manufacturing a semiconductor device according to Item 1,
前記 ( h ) 工程では、 前記第 2開口部の底部で露出する前記第 1導体膜上に前 記第 2キヤップ導体膜を選択成長または優先成長させることにより、 前記第 2キ ャップ導体膜を形成することを特徴とする半導体装置の製造方法。  In the step (h), the second cap conductor film is selectively grown or preferentially grown on the first conductor film exposed at the bottom of the second opening to form the second cap conductor film. A method of manufacturing a semiconductor device.
項 6 ：項 1記載の半導体装置の製造方法において、 Item 6: The method for manufacturing a semiconductor device according to Item 1,
前記第 1キャップ導体膜は、 タングステン、 タングステン合金、 コバルト、 コ パルト合金、 二ッケルまたは二ッケル合金からなることを特徴とする半導体装置 の製造方法。  The method of manufacturing a semiconductor device according to claim 1, wherein the first cap conductor film is made of tungsten, a tungsten alloy, cobalt, a cobalt alloy, nickel, or nickel alloy.
項 7 ：項 1記載の半導体装置の製造方法において、 Item 7: The method for manufacturing a semiconductor device according to Item 1,
前記第 2キャップ導体膜は、 タングステン、 タングステン合金、 コバルト、 コ パルト合金、 二ッケルまたは二ッケル合金からなることを特徴とする半導体装置 の製造方法。  The method of manufacturing a semiconductor device according to claim 1, wherein the second cap conductor film is made of tungsten, a tungsten alloy, cobalt, a cobalt alloy, nickel, or nickel alloy.
項 8 ：項 1記載の半導体装置の製造方法において、 Item 8: The method for manufacturing a semiconductor device according to Item 1,
前記 （e ) 工程で形成される前記第 1キャップ導体膜の膜厚は、 2〜2 0 n m の範囲内であることを特徴とする半導体装置の製造方法。  The method for manufacturing a semiconductor device, wherein a thickness of the first cap conductor film formed in the step (e) is in a range of 2 to 20 nm.
項 9 ：項 1記載の半導体装置の製造方法において、 Item 9: The method for manufacturing a semiconductor device according to Item 1,
前記 （ h ) 工程で形成される前記第 2キヤップ導体膜の膜厚は、 2〜 2 0 n m の範囲内であることを特徴とする半導体装置の製造方法。  The method of manufacturing a semiconductor device, wherein a thickness of the second cap conductor film formed in the step (h) is in a range of 2 to 20 nm.
項 1 0 ：項 1記載の半導体装置の製造方法において、 Item 10: In the method of manufacturing a semiconductor device according to Item 1,
前記第 1パリァ導体膜がタングステン以外の高融点金属膜を含み、 前記 (e) 工程では、 無電解めつき法により前記第 1キャップ導体膜を形成す ることを特徴とする半導体装置の製造方法。 The first parier conductor film includes a high melting point metal film other than tungsten, In the method (e), the first cap conductor film is formed by an electroless plating method.
項 1 1 ：項 1記載の半導体装置の製造方法において、 Item 11: In the method for manufacturing a semiconductor device according to Item 1,
前記第 1パリァ導体膜がタングステン以外の高融点金属膜を含んでおらず、 前記 （e) 工程では、 CVD法または無電解めつき法により前記第 1キャップ 導体膜を形成することを特徴とする半導体装置の製造方法。  The first capacitor conductor film does not include a refractory metal film other than tungsten, and in the step (e), the first cap conductor film is formed by a CVD method or an electroless plating method. A method for manufacturing a semiconductor device.
項 1 2 ：項 1記載の半導体装置の製造方法において、 Item 12: In the method for manufacturing a semiconductor device according to Item 1,
前記 （g) 工程では、 前記第 2開口部の底部で第 1パリア導体膜が露出しない ように前記第 2開口部を形成し、  In the step (g), the second opening is formed so that the first barrier conductor film is not exposed at the bottom of the second opening;
前記 (h) 工程では、 CVD法または無電解めつき法により前記第 2キャップ 導体膜を形成することを特徴とする半導体装置の製造方法。  In the method (h), the second cap conductor film is formed by a CVD method or an electroless plating method.
項 1 3 ：項 1記載の半導体装置の製造方法において、 Item 13: In the method for manufacturing a semiconductor device according to Item 1,
前記第 1パリァ導体膜がタングステン以外の高融点金属膜を含んでおらず、 前記 （g) 工程では、 前記第 2開口部の底部で第 1バリア導体膜が露出するよ うに前記第 2開口部を形成し、  The first barrier conductor film does not include a refractory metal film other than tungsten, and in the step (g), the second opening is formed such that the first barrier conductor film is exposed at the bottom of the second opening. Form
前記 (h) 工程では、 CVD法または無電解めつき法により前記第 2キャップ 導体膜を形成することを特徴とする半導体装置の製造方法。  In the method (h), the second cap conductor film is formed by a CVD method or an electroless plating method.
項 14 ：項 1記載の半導体装置の製造方法において、 Item 14: The method for manufacturing a semiconductor device according to Item 1,
前記第 1パリァ導体膜がタングステン以外の高融点金属膜を含み、  The first parier conductor film includes a high melting point metal film other than tungsten,
前記 （g) 工程では、 前記第 2開口部の底部で第 1パリア導体膜が露出するよ うに前記第 2開口部を形成し、  In the step (g), the second opening is formed so that the first barrier conductor film is exposed at the bottom of the second opening;
前記 （h) 工程では、 無電解めつき法により前記第 2キャップ導体膜を形成す ることを特徴とする半導体装置の製造方法。  The method of manufacturing a semiconductor device, wherein in the step (h), the second cap conductor film is formed by an electroless plating method.
項 1 5 ：項 1記載の半導体装置の製造方法において、 Clause 15: In the method of manufacturing a semiconductor device according to clause 1,
前記 (e) 工程前に、 更に、  Before the step (e),
(e l) 前記第 1配,線の上面を前記第 1絶縁膜の上面よりも後退させる工程、 を有することを特徴とする半導体装置の製造方法。  (e1) a step of retreating the upper surface of the first wiring from the upper surface of the first insulating film.
項 1 6 ：項 1 5記載の半導体装置の製造方法において、 Item 16: In the method for manufacturing a semiconductor device according to Item 15,
前記 （e) 工程では、 前記第 1キャップ導体膜の上面と前記第 1絶縁膜の上面 とが略平面になるように、 前記第 1キヤップ導体膜を形成することを特徴とする 半導体装置の製造方法。 In the step (e), the upper surface of the first cap conductor film and the upper surface of the first insulating film Forming the first cap conductive film such that the first cap conductor film is substantially flat.
項 1 7 ：項 1記載の半導体装置の製造方法において、 Item 17: In the method for manufacturing a semiconductor device according to Item 1,
前記 （g ) 工程では、 前記第 2絶縁膜に形成された配線溝と前記配線溝の底部 から前記第 1導体膜まで到達するビアとを有する前記第 2開口部を形成し、 前記 ( h ) 工程では、 前記ビアの底部で露出する前記第 1導体膜上に前記第 2 キヤップ導体膜を形成することを特徴とする半導体装置の製造方法。  In the step (g), the second opening having a wiring groove formed in the second insulating film and a via reaching from the bottom of the wiring groove to the first conductive film is formed; Forming a second cap conductor film on the first conductor film exposed at the bottom of the via.
項 1 8 ：項 1記載の半導体装置の製造方法において、 Item 18: In the method for manufacturing a semiconductor device according to Item 1,
前記 （ f ) 工程では、 前記第 1絶縁膜および前記第 1キヤップ導体膜上に形成 されたパリア絶縁膜を含む複数の絶縁膜からなる前記第 2絶縁膜を形成すること を特徴とする半導体装置の製造方法。  In the step (f), the second insulating film including a plurality of insulating films including a first insulating film and a barrier insulating film formed on the first cap conductive film is formed. Manufacturing method.
項 1 9 ： ( a ) 半導体基板を準備する工程、 Item 19: (a) the step of preparing a semiconductor substrate,
( b ) 前記半導体基板上に第 1絶縁膜を形成する工程、  (b) forming a first insulating film on the semiconductor substrate,
( c ) 前記第 1絶縁膜に第 1開口部を形成する工程、  (c) forming a first opening in the first insulating film,
( d ) 前記第 1開口部の側壁および底部上に形成された第 1パリア導体膜と、 前 記第 1開口部内を埋めるように前記第 1パリァ導体膜上に形成された銅を主成分 とする第 1導体膜とを有する第 1配線を形成する工程、  (d) a first barrier conductor film formed on the side wall and the bottom of the first opening, and copper formed on the first pariconductor film so as to fill the first opening; Forming a first wiring having a first conductor film to be formed,
( e ) 前記第 1配線上に選択的に第 1キャップ導体膜を形成する工程、  (e) selectively forming a first cap conductor film on the first wiring,
( f ) 前記第 1絶縁膜および前記第 1キヤップ導体膜上に第 2絶縁膜を形成する 工程、  (f) forming a second insulating film on the first insulating film and the first cap conductor film,
( g ) 前記第 2絶縁膜および前記第 1キャップ導体膜の一部分を選択的に除去し て、 その底部で前記第 1導体膜を露出する第 2開口部を形成する工程、  (g) a step of selectively removing a part of the second insulating film and the first cap conductor film to form a second opening exposing the first conductor film at the bottom thereof;
( h ) 前記第 2開口部の底部で露出する前記第 1導体膜上に第 2キヤップ導体膜 を形成する工程、  (h) forming a second cap conductor film on the first conductor film exposed at the bottom of the second opening,
( i ) 前記第 2開口部の内部を含む前記第 2絶縁膜上に第 2パリア導体膜を形成 する工程、  (i) forming a second barrier conductor film on the second insulating film including the inside of the second opening;
( j ) 前記第 2開口部内を埋めるように前記第 2パリア導体膜上に銅を主成分と する第 2導体膜を形成し、 前記第 2絶縁膜上の前記第 2パリア導体膜および第 2 導体膜を除去して前記第 2開口部内に前記第 2パリァ導体膜および第 2導体膜を 残して埋め込む工程、 (j) forming a second conductor film containing copper as a main component on the second barrier conductor film so as to fill the second opening; and forming the second conductor film and the second conductor film on the second insulating film. The conductor film is removed, and the second parer conductor film and the second conductor film are placed in the second opening. Leaving and embedding process,
を有することを特徴とする半導体装置の製造方法。  A method for manufacturing a semiconductor device, comprising:
項 2 0 : ( a ) 半導体基板を準備する工程、 Item 20 : (a) a step of preparing a semiconductor substrate,
( b ) 前記半導体基板上に第 1絶縁膜を形成する工程、  (b) forming a first insulating film on the semiconductor substrate,
( c ) 前記第 1絶縁膜に第 1開口部を形成する工程、  (c) forming a first opening in the first insulating film,
( d ) 前記第 1開口部の側壁および底部上に形成された第 1パリア導体膜と、 前 記第 1開口部内を埋めるように前記第 1パリァ導体膜上に形成された銅を主成分 とする第 1導体膜とを有する第 1配線を形成し、 前記第 1導体膜の上面を選択的 にェツチングして前記第 1絶縁膜の上面より低く形成する工程、  (d) a first barrier conductor film formed on the side wall and the bottom of the first opening, and copper formed on the first pariconductor film so as to fill the first opening; Forming a first wiring having a first conductive film to be formed, and selectively etching the upper surface of the first conductive film to be lower than the upper surface of the first insulating film;
( e ) 前記第 1配線上に選択的に第 1キャップ導体膜を形成する工程、  (e) selectively forming a first cap conductor film on the first wiring,
( f ) 前記第 1絶縁膜および前記第 1キヤップ導体膜上に第 2絶縁膜を形成する 工程、  (f) forming a second insulating film on the first insulating film and the first cap conductor film,
( g ) 前記第 2絶縁膜および前記第 1キャップ導体膜の一部分を選択的に除去し て、 その底部で前記第 1導体膜を露出する第 2開口部を形成する工程、  (g) a step of selectively removing a part of the second insulating film and the first cap conductor film to form a second opening exposing the first conductor film at the bottom thereof;
( h ) 前記第 2開口部の底部で露出する前記第 1導体膜上に第 2キャップ導体膜 を形成する工程、  (h) forming a second cap conductor film on the first conductor film exposed at the bottom of the second opening,
( i ) 前記第 2開口部の内部を含む前記第 2絶縁膜上に第 2バリァ導体膜を形成 する工程、  (i) forming a second barrier conductor film on the second insulating film including the inside of the second opening;
( j ) 前記第 2開口部内を埋めるように前記第 2パリア導体膜上に銅を主成分と する第 2導体膜を形成し、 前記第 2絶縁膜上の前記第 2パリア導体膜および第 2 導体膜を除去して前記第 2開口部内に前記第 2パリァ導体膜および第 2導体膜を 残して埋め込む工程、  (j) forming a second conductor film containing copper as a main component on the second barrier conductor film so as to fill the second opening; and forming the second conductor film and the second conductor film on the second insulating film. Removing the conductor film and embedding the second parer conductor film and the second conductor film in the second opening,
を有することを特徴とする半導体装置の製造方法。 図面の簡単な説明  A method for manufacturing a semiconductor device, comprising: Brief Description of Drawings
図 1は、 本発明の一実施の形態である半導体装置の製造工程中の要部断面図で ある。  FIG. 1 is a fragmentary cross-sectional view of a semiconductor device according to an embodiment of the present invention during a manufacturing step.
図 2は、 図 1に続く半導体装置の製造工程中における要部断面図である。 図 3は、 図 2に続く半導体装置の製造工程中における要部断面図である。 図 4は、 図 3に続く半導体装置の製造工程中における要部断面図である。 図 5は、 図 4に続く半導体装置の製造工程中における要部断面図である。 図 6は、 図 5に続く半導体装置の製造工程中における要部断面図である。 図 7は、 図 6に続く半導体装置の製造工程中における要部断面図である。 図 8は、 図 7に続く半導体装置の製造工程中における要部断面図である。 図 9は、 導電性パリァ膜の材料と金属キヤップ膜の形成方法の関係を示す説明 図である。 FIG. 2 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. FIG. 3 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. FIG. 4 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. FIG. 5 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. FIG. 6 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. FIG. 7 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. FIG. 8 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. FIG. 9 is an explanatory diagram showing the relationship between the material of the conductive parer film and the method of forming the metal cap film.
図 1 0は、 図 8に続く半導体装置の製造工程中における要部断面図である。 図 1 1は、 窪み 2 1を形成せずにパリア絶縁膜を形成した状態を示す要部断面 図である。  FIG. 10 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. FIG. 11 is a cross-sectional view of a main part showing a state where a paria insulating film is formed without forming the depression 21.
図 1 2は、 図 1 0に続く半導体装置の製造工程中における要部断面図である。 図 1 3は、 図 1 2に続く半導体装置の製造工程中における要部断面図である。 図 1 4は、 図 1 3に続く半導体装置の製造工程中における要部断面図である。 図 1 5は、 図 1 4に続く半導体装置の製造工程中における要部断面図である。 図 1 6は、 図 1 5に続く半導体装置の製造工程中における要部断面図である。 図 1 7は、 図 1 6に続く半導体装置の製造工程中における要部断面図である。 図 1 8は、 図 1 7に続く半導体装置の製造工程中における要部断面図である。 図 1 9は、 比較例の半導体装置の要部断面図である。  FIG. 12 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. FIG. 13 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. FIG. 14 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. FIG. 15 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. FIG. 16 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. FIG. 17 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. FIG. 18 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. FIG. 19 is a cross-sectional view of a main part of a semiconductor device of a comparative example.
図 2 0は、 銅配線の上面を金属キャップで被覆した半導体装置の要部断面図で ある。  FIG. 20 is a cross-sectional view of a main part of a semiconductor device in which the upper surface of a copper wiring is covered with a metal cap.
図 2 1は、 本発明の一実施の形態である半導体装置の要部断面図である。 図 2 2は、 本発明の他の実施の形態である半導体装置の製造工程中の要部断面 図である。  FIG. 21 is a sectional view of a main part of a semiconductor device according to an embodiment of the present invention. FIG. 22 is a fragmentary cross-sectional view of a semiconductor device according to another embodiment of the present invention during a manufacturing step.
図 2 3は、 図 2 2に続く半導体装置の製造工程中における要部断面図である。 図 2 4は、 ビアに目外れが生じ得る場合の導電性パリア膜の材料と金属キヤッ プ膜の形成方法の関係を示す説明図である。  FIG. 23 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. FIG. 24 is an explanatory diagram showing the relationship between the material of the conductive barrier film and the method of forming the metal cap film when the via can be missed.
図 2 5は、 ビアに目外れが生じない場合の導電性パリア膜の材料と金属キヤッ プ膜の形成方法の関係を示す説明図である。  FIG. 25 is an explanatory diagram showing the relationship between the material of the conductive barrier film and the method of forming the metal cap film in the case where the via does not miss.
図 2 6は、 図 2 3に続く半導体装置の製造工程中における要部断面図である。 図 2 7は、 本発明の他の実施の形態である半導体装置の製造工程中の要部断面 図である。 FIG. 26 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. FIG. 27 is a fragmentary cross-sectional view of a semiconductor device according to another embodiment of the present invention during a manufacturing step.
図 2 8は、 図 2 7に続く半導体装置の製造工程中における要部断面図である。 図 2 9は、 図 2 8に続く半導体装置の製造工程中における要部断面図である。 図 3 0は、 図 2 9に続く半導体装置の製造工程中における要部断面図である。 図 3 1は、 本発明の他の実施の形態である半導体装置の製造工程中の要部断面 図である。  FIG. 28 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. FIG. 29 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. FIG. 30 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. FIG. 31 is a fragmentary cross-sectional view of a semiconductor device according to another embodiment of the present invention during a manufacturing step.
図 3 2は、 図 3 1に続く半導体装置の製造工程中における要部断面図である。 図 3 3は、 図 3 2に続く半導体装置の製造工程中における要部断面図である。 図 3 4は、 図 3 3に続く半導体装置の製造工程中における要部断面図である。 図 3 5は、 本発明の他の実施の形態である半導体装置の製造工程中の要部断面 図である。  FIG. 32 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. FIG. 33 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. FIG. 34 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. FIG. 35 is a cross-sectional view of a principal part in a manufacturing step of a semiconductor device according to another embodiment of the present invention.
図 3 6は、 図 3 5に続く半導体装置の製造工程中における要部断面図である。 図 3 7は、 図 3 6に続く半導体装置の製造工程中における要部断面図である。 図 3 8は、 図 3 7に続く半導体装置の製造工程中における要部断面図である。 図 3 9は、 本発明の他の実施の形態である半導体装置の製造工程中の要部断面 図である。  FIG. 36 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. FIG. 37 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. FIG. 38 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 37; FIG. 39 is a fragmentary cross-sectional view of a semiconductor device according to another embodiment of the present invention during a manufacturing step.
図 4 0は、 図 3 9に続く半導体装置の製造工程中における要部断面図である。 図 4 1は、 図 4 0に続く半導体装置の製造工程中における要部断面図である。 図 4 2は、 本発明の他の実施の形態である半導体装置の要部断面図である。 発明を実施するための最良の形態  FIG. 40 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. FIG. 41 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. FIG. 42 is a cross-sectional view of a main part of a semiconductor device according to another embodiment of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION
以下、 本発明の実施の形態を図面に基づいて詳細に説明する。 なお、 実施の形 態を説明するための全図において、 同一の機能を有する部材には同一の符号を付 し、 その繰り返しの説明は省略する。 また、 以下の実施の形態では、 特に必要な とき以外は同一または同様な部分の説明を原則として繰り返さない。  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and their repeated description is omitted. Further, in the following embodiments, description of the same or similar parts will not be repeated in principle unless particularly necessary.
また、 実施の形態で用いる図面においては、 断面図であっても図面を見易くす るためにハッチングを省略する場合もある。 また、 平面図であっても図面を見易 くするためにハッチングを付す場合もある。 (実施の形態 1 ) Further, in the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Also, hatching may be used even in a plan view so as to make the drawings easy to see. (Embodiment 1)
本実施の形態の半導体装置およびその製造工程を図面を参照して説明する。 図 A semiconductor device according to the present embodiment and a manufacturing process thereof will be described with reference to the drawings. Figure
1は、 本発明の一実施の形態である半導体装置、 例えば M I S F E T (Metal Insulator Semiconductor Field Effect Transistor) , の製造工程中の要部断面 図である。 1 is a cross-sectional view of a main part of a semiconductor device according to an embodiment of the present invention, for example, a manufacturing process of a metal insulator semiconductor field effect transistor (MISFET).
図 1に示すように、 例えば 1〜： L 0 Ω c m程度の比抵抗を有する p型の単結晶 シリコンなどからなる半導体基板 （半導体ウェハ） 1の主面に素子分離領域 2が 形成される。素子分離領域 2は酸化シリコンなどからなり、例えば S T I (Shallow Trench Isolation) または L O C u S (Local Oxidization of Silicon ) 法な どにより形成される。  As shown in FIG. 1, for example, an element isolation region 2 is formed on a main surface of a semiconductor substrate (semiconductor wafer) 1 made of p-type single crystal silicon or the like having a specific resistance of about 1 to: L 0 Ω cm. The element isolation region 2 is made of silicon oxide or the like, and is formed by, for example, an STI (Shallow Trench Isolation) or LOCus (Local Oxidization of Silicon) method.
次に、 半導体基板 1の nチャネル型 M I S F E Tを形成する領域に p型ゥエル 3を形成する。 p型ウエノレ 3は、 例えばホウ素 （B ) などの不純物をイオン注入 することなどによって形成される。 Next, a p-type well 3 is formed in a region of the semiconductor substrate 1 where an n- channel MISFET is to be formed. The p-type well 3 is formed, for example, by ion-implanting an impurity such as boron (B).
次に、 P型ゥエル 3の表面にゲート絶縁膜 4が形成される。ゲート絶縁膜 4は、 例えば薄い酸ィ匕シリコン膜などからなり、 例えば熱酸化法などによって形成する ことができる。  Next, a gate insulating film 4 is formed on the surface of the P-type well 3. The gate insulating film 4 is made of, for example, a thin silicon oxide film, and can be formed by, for example, a thermal oxidation method.
次に、 p型ゥエル 3のゲ一ト絶縁膜 4上にゲート電極 5が形成される。例えば、 半導体基板 1上に多結晶シリコン膜を形成し、その多結晶シリコン膜にリン（P ) などをイオン注入して低抵抗の n型半導体膜とし、 その多結晶シリコン膜をドラ ィエッチングによってパターニングすることにより、 多結晶シリコン膜からなる ゲート電極 5を形成することができる。  Next, a gate electrode 5 is formed on the gate insulating film 4 of the p-type well 3. For example, a polycrystalline silicon film is formed on the semiconductor substrate 1, phosphorus (P) or the like is ion-implanted into the polycrystalline silicon film to form a low-resistance n-type semiconductor film, and the polycrystalline silicon film is dry-etched. By patterning, the gate electrode 5 made of a polycrystalline silicon film can be formed.
次に、 P型ゥエル 3のゲート電極 5の両側の領域にリンなどの不純物をイオン 注入することにより、 n一型半導体領域 6が形成される。  Next, an n-type semiconductor region 6 is formed by ion-implanting an impurity such as phosphorus into both sides of the gate electrode 5 of the P-type well 3.
次に、 ゲート電極 5の側壁上に、 例えば酸ィ匕シリコンなどからなる側壁スぺー サまたはサイドウオール 7が形成される。 サイドウオール 7は、 例えば、 半導体 基板 1上に酸化シリコン膜を堆積し、 この酸ィ匕シリコン膜を異方性エッチングす ることによつて形成することができる。  Next, on the side wall of the gate electrode 5, a side wall spacer or a side wall 7 made of, for example, silicon oxide is formed. The sidewall 7 can be formed, for example, by depositing a silicon oxide film on the semiconductor substrate 1 and anisotropically etching the silicon oxide film.
サイドウォール 7の形成後、 n +型半導体領域 8 (ソース、 ドレイン） 1 例 えば、 p型ウエノレ 3のゲート電極 5およびサイドウオール 7の両側の領域にリン などの不純物をイオン注入することにより形成される。 n +型半導体領域 8は、 n -型半導体領域 6よりも不純物濃度が高い。 After the formation of the side wall 7, the n + type semiconductor region 8 (source, drain) 1 It is formed by ion-implanting impurities such as. The n + type semiconductor region 8 has a higher impurity concentration than the n − type semiconductor region 6.
次に、 ゲート電極 5および n +型半導体領域 8の表面を露出させ、 例えばコパ ルト （C o ) 膜を堆積して熱処理することによって、 ゲート電極 5と n +型半導 体領域 8との表面に、 それぞれシリサイド膜 5 aおよびシリサイド膜 8 aを形成 する。 これにより、 n +型半導体領域 8の拡散抵抗と、 コンタクト抵抗とを低抵 抗化することができる。 その後、 未反応のコバルト膜は除去する。  Next, by exposing the surfaces of the gate electrode 5 and the n + type semiconductor region 8, for example, depositing a cobalt (Co) film and performing heat treatment, the gate electrode 5 and the n + type semiconductor region 8 are separated. A silicide film 5a and a silicide film 8a are formed on the surface, respectively. Thus, the resistance of the diffusion resistance of the n + type semiconductor region 8 and the contact resistance can be reduced. Thereafter, the unreacted cobalt film is removed.
このようにして、 p型ゥエル 3に nチャネル型の M I S F E T (Metal Insulator Semiconductor Field Effect lransistor) 9力 s形成される。 In this way, an n-channel type MISFET (Metal Insulator Semiconductor Field Effect lransistor) 9 s is formed in the p-type well 3.
次に、 半導体基板 1上に窒化シリコンなどからなる絶縁膜 1◦と、 酸化シリコ ンなどからなる絶縁膜 1 1を順次堆積する。 それから、 絶縁膜 1 1および絶縁膜 1 0を順次ドライエッチングすることにより、 n +型半導体領域 （ソース、 ドレ イン) 8の上部などにコンタクトホール 1 2を形成する。 コンタクトホール 1 2 の底部では、 半導体基板 1の主面の一部、 例えば n +型半導体領域 8の一部、 や ゲート電極 5の一部などが露出される。  Next, an insulating film 1 1 made of silicon nitride or the like and an insulating film 11 made of silicon oxide or the like are sequentially deposited on the semiconductor substrate 1. Then, a contact hole 12 is formed in the upper portion of the n + type semiconductor region (source, drain) 8 by sequentially performing dry etching on the insulating film 11 and the insulating film 10. At the bottom of the contact hole 12, a part of the main surface of the semiconductor substrate 1, for example, a part of the n + type semiconductor region 8 and a part of the gate electrode 5 are exposed.
次に、 コンタクトホーノレ 1 2内に、 タングステン (W) などからなるプラグ 1 3が形成される。 プラグ 1 3は、 例えば、 コンタクトホール 1 2の内部を含む絶 縁膜 1 1上にパリァ膜として例えば窒化チタン膜 1 3 aを形成した後、 タングス テン膜を C V D (Chemical Vapor Deposition) 法などによって窒化チタン膜 1 3 a上にコンタクトホーノレ 1 2を埋めるように形成し、 絶縁膜 1 1上の不要なタン ダステン膜および窒化チタン膜 1 3 aを CMP (Chemical Mechanical Polishing ) 法またはエッチパック法などによって除去することにより形成することができ る。  Next, a plug 13 made of tungsten (W) or the like is formed in the contact horn 12. The plug 13 is formed, for example, by forming a titanium nitride film 13a as a parier film on the insulating film 11 including the inside of the contact hole 12 and then forming a tungsten film by a CVD (Chemical Vapor Deposition) method or the like. A contact horn layer 12 is formed on the titanium nitride film 13a so as to fill it, and an unnecessary tungsten film and the titanium nitride film 13a on the insulating film 11 are removed by a CMP (Chemical Mechanical Polishing) method or an etch pack method. It can be formed by removing with a method such as.
図 2〜図 8は、 図 1に続く半導体装置の製造工程中における要部断面図を示し ている。 なお、 理解を簡単にするために、 図 2〜図 8では、 図 1の絶縁膜 1 1よ り下の構造に対応する部分は図示を省略している。  2 to 8 are cross-sectional views of main parts of the semiconductor device during the manufacturing process following that of FIG. In addition, in order to facilitate understanding, in FIGS. 2 to 8, portions corresponding to the structure below the insulating film 11 in FIG. 1 are omitted.
図 2に示されるように、 プラグ 1 3が埋め込まれた絶縁膜 1 1上に絶縁膜 （ェ ツチングストツノ、。膜） 1 4を形成する。 絶縁膜 1 4は、 例えば炭化シリコン （S i C) 膜からなる。 絶縁膜 1 4の他の材料として、 窒化シリコン （S i xN y) 膜 などを用いることもできる。 絶縁膜 14は、 炭化シリコン （S i C) 膜と窒化シ リコン （S i xNy) 膜との積層膜で構成してもよい。 絶縁膜 14は、 その上層の 絶縁膜 （層間絶縁膜） 1 5に配線形成用の溝ゃ孔をエッチングにより形成する際 に、 その掘り過ぎにより下層に損傷を与えたり、 加工寸法精度が劣化したりする ことを回避するために形成される。 すなわち、 絶縁膜 14は絶縁膜 （層間絶縁膜） 1 5をエッチングする際にエッチングストッパとして機能することができる。 次に、 絶縁膜 14上に絶縁膜 （層間絶縁膜） 1 5を形成する。 絶縁膜 1 5は、 低誘電率材料 （いわゆる L ow— K絶縁膜、 L ow-K#^) からなることが好 ましい。 低誘電率材料を用いることで絶縁膜 1 5の誘電率を下げることができる ので、 半導体装置の配線の総合的な誘電率を下げることが可能であり、 配線遅延 を改善できる。 なお、 低誘電率な絶縁膜 （L ow_K絶縁膜） とは、 パッシベー ション膜に含まれる酸化シリコン膜 （たとえば T EOS (Tetraethoxysilane) 酸 化膜） の誘電率よりも低い誘電率を有する絶縁膜を例示できる。 一般的には、 T EOS酸化膜の比誘電率 ε = 4 · 1〜 4. 2程度以下を低誘電率な絶縁膜と言う。 絶縁膜 15に用いることができる低誘電率材料としては、例えば、有機ポリマー、 有機シリカガラス、 F SG (S i OF系材料、 フッ素 （F) が添加された酸化シ リ コン） 、 H S Q (hydrogen silsesquioxane ) 系材料、 M S Q (methyl silsesquioxane) 系材料、 ポーラス HSQ系材料、 ポーラス MS Q材料またはポ 一ラス有機系材料などを用いることができる。 As shown in FIG. 2, an insulating film (etching film) 14 is formed on the insulating film 11 in which the plug 13 is embedded. The insulating film 14 is made of, for example, a silicon carbide (SiC) film. Other materials of the insulating film 1 4, silicon nitride (S i x N y) film Etc. can also be used. Insulating film 14 may be constituted by a laminated film of a silicon carbide (S i C) film and a nitride divorced (S i x N y) film. When the insulating film 14 is formed by etching grooves and holes for wiring on the insulating film (interlayer insulating film) 15 on the upper layer, excessive digging may damage the lower layer or degrade the processing dimensional accuracy. Is formed in order to avoid That is, the insulating film 14 can function as an etching stopper when the insulating film (interlayer insulating film) 15 is etched. Next, an insulating film (interlayer insulating film) 15 is formed on the insulating film 14. The insulating film 15 is preferably made of a low dielectric constant material (a so-called Low-K insulating film, Low-K # ^). Since the dielectric constant of the insulating film 15 can be reduced by using a low dielectric constant material, the overall dielectric constant of the wiring of the semiconductor device can be reduced, and the wiring delay can be improved. Note that an insulating film having a low dielectric constant (Low_K insulating film) is an insulating film having a dielectric constant lower than that of a silicon oxide film (for example, TEOS (Tetraethoxysilane) oxide film) included in the passivation film. Can be illustrated. Generally, a dielectric constant of the TEOS oxide film of about ε = 4.1 44.2 or less is called an insulating film having a low dielectric constant. Examples of the low dielectric constant material that can be used for the insulating film 15 include an organic polymer, an organic silica glass, FSG (SiO OF material, silicon oxide to which fluorine (F) is added), HSQ (hydrogen Silsesquioxane) materials, MSQ (methyl silsesquioxane) materials, porous HSQ materials, porous MSQ materials, or porous organic materials can be used.
また、 絶縁膜 1 5を上記のような低誘電率材料膜とその上に形成された保護膜 との積層膜により構成することもできる。 この低誘電率材料膜上の保護膜は、 例 えば二酸ィ匕シリコン （S i O2) に代表される酸化シ.リコン （S i Ox) 膜または 酸窒化シリコン （S i ON) 膜を用いることができ、 例えば CMP処理時におけ る絶縁膜 1 5の機械的強度の確保、 表面保護および耐湿性の確保等のような機能 を有することができる。 また、 低誘電率材料膜が例えばフッ素 （F) を含む酸化 シリコン膜 （S i OF膜） からなる場合は、 上記保護膜は、 フッ素の拡散を防止 するように機能することもできる。 また、 例えば低誘電率材料膜が CMP工程に おける耐性を有する場合などは、 上記保護膜の形成を省略することもできる。 ま た、 配線間の容量がそれほど問題にならない場合などは、 絶縁膜 1 5を酸化シリ コン膜の単体膜などにより形成することもできる。 Further, the insulating film 15 may be formed of a laminated film of the above-described low dielectric constant material film and the protective film formed thereon. The protective film on the low dielectric constant material film is oxidized typified example if two Sani匕silicon (S i O 2). Recon (S i O x) film or a silicon oxynitride (S i ON) film For example, the insulating film 15 can have functions such as securing mechanical strength, surface protection, and moisture resistance during the CMP process. Further, when the low dielectric constant material film is made of, for example, a silicon oxide film (Si OF film) containing fluorine (F), the protective film can also function to prevent diffusion of fluorine. In addition, for example, when the low dielectric constant material film has resistance in the CMP process, the formation of the protective film can be omitted. In addition, when the capacitance between wiring lines is not so important, the insulating film 15 is made of silicon oxide. It can also be formed by a single film of a capacitor film.
次に、 図 3に示されるように、 フォトリソグラフィ法およびドライエッチング 法を用いて、 絶縁膜 1 5および絶縁膜 14を選択的に除去して配線開口部として の配線溝 （開口部） 1 7を形成する。 このとき、 配線溝 1 7の底部では、 プラグ 1 3の上面が露出される。 その後、 エッチングマスクとして用いた図示しないフ オトレジストパターン （および反射防止膜） をアツシングなどにより除去する。 絶縁膜 1 5が、 例えば有機ポリマー系の材料やポーラス有機系材料などのように 酸素プラズマによりダメージを受け得る材料からなる場合は、 絶縁膜 1 5を NH Next, as shown in FIG. 3, using photolithography and dry etching, the insulating film 15 and the insulating film 14 are selectively removed to form a wiring groove (opening) 17 as a wiring opening. To form At this time, the upper surface of the plug 13 is exposed at the bottom of the wiring groove 17. Thereafter, the photoresist pattern (not shown) (and the anti-reflection film) used as an etching mask is removed by asking or the like. When the insulating film 15 is made of a material that can be damaged by oxygen plasma, for example, an organic polymer material or a porous organic material, the insulating film 15 is made of NH.
3プラズマ処理または N 2/H 2プラズマ処理などの還元性ブラズマ処理によって エッチングしながら、 フォトレジストパターン (および反射防止膜) をアツシン グして除去することもできる。 The photoresist pattern (and the anti-reflection film) can be removed by ashes while etching by reducing plasma processing such as 3 plasma processing or N 2 / H 2 plasma processing.
次に、 図 4に示されるように、 半導体基板 1の主面上の全面 （すなわち配線溝 1 7の底部および側壁上を含む絶縁膜 1 5上） に、 例えば厚さ 50 nm程度の比 較的薄い導電性パリァ膜 （パリァ導体膜） 1 8を形成する。 導電性パリア膜 1 8 の成膜には、 スパッタリング法、 CVD法または原子層デポジション （ALD： Atomic Layer Deposition)法などを用いることができる。導電性パリア膜 1 8は、 例えば後述の主導体膜形成用の銅の拡散を抑制または防止する機能や主導体膜の リフロー時に銅の濡れ性を向上させる機能、 あるいは銅 （銅膜） の接着性を高め る機能などを有している。 このような導電性パリア膜 1 8の材料としては、 例え ばチタン （T i ) 、 タンタノレ (T a) またはタングステン （W) などのような高 融点金属や、 その合金膜 （例えば窒化チタン （T i N) 、 窒ィ匕タンタル （T aN) または窒化タングステン （WN) などのような高融点金属窒化物、 またはそのよ うな高融点金属窒ィ匕物にシリコン （S i ) を添カ卩した材料 （例えば T i S i N, T a S i N, WS i N) など） を用いることができる。 また、 導電性パリア膜 1 8としては、 上記材料膜の単体膜だけでなく積層膜を用いることもできる。  Next, as shown in FIG. 4, the entire surface on the main surface of the semiconductor substrate 1 (that is, on the insulating film 15 including the bottom of the wiring groove 17 and the side wall) is compared with, for example, a thickness of about 50 nm. An electrically thin conductive palier film (parier conductor film) 18 is formed. For forming the conductive barrier film 18, a sputtering method, a CVD method, an atomic layer deposition (ALD) method, or the like can be used. The conductive barrier film 18 has, for example, a function of suppressing or preventing the diffusion of copper for forming a main conductor film described later, a function of improving the wettability of copper when the main conductor film is reflowed, or an adhesion of copper (copper film). It has functions to enhance the performance. Examples of the material of the conductive barrier film 18 include a high-melting-point metal such as titanium (T i), tantalum (Ta) or tungsten (W), and an alloy film thereof (for example, titanium nitride (T iN), high melting point metal nitride such as tantalum (TaN) or tungsten nitride (WN), or silicon (Si) added to such high melting point metal nitride. Materials (eg, TiSiN, TaSiN, WSiN) can be used. Further, as the conductive barrier film 18, not only a single film of the above-mentioned material film but also a laminated film can be used.
次に、 図 5に示されるように、 導電性パリア膜 1 8上に、 相対的に厚い銅から なる主導体膜 （銅膜） 1 9を形成する。 主導体膜 1 9は、 例えば CVD法、 スパ ッタリング法またはめつき法などを用いて形成することができる。 また、 主導体 膜 1 9は銅を主成分とする導体膜、 例えば銅または銅合金 （Cuを主成分とし、 例えば M g， A g , P d , T i， T a , A 1 , N b， Z rまたは Z nなどを含む） により形成することができる。 また、 導電性パリア膜 1 8上に、 相対的に薄い銅 (または銅合金） などからなるシード膜をスパッタリング法または C V D法など によって形成し、 その後、 シード膜上に相対的に厚い銅 （または銅合金） などか らなる主導体膜 1 9をめつき法 （電解めつき法） などによって形成することもで きる。 このシード膜は、 主導体膜 1 9と導電性パリア膜 1 8の密着性を向上させ るよう機能することができる。その後、例えば 4 7 5 °C程度の非酸化性雰囲気（例 えば水素雰囲気） 中において半導体基板 1に対して熱処理を施すことにより主導 体膜 1 9をリフローさせ、 銅を配線溝 1 7の内部に隙間なく埋め込む。 Next, as shown in FIG. 5, a main conductor film (copper film) 19 made of relatively thick copper is formed on the conductive barrier film 18. The main conductor film 19 can be formed by using, for example, a CVD method, a sputtering method, or a plating method. The main conductor film 19 is a conductor film containing copper as a main component, for example, copper or a copper alloy (containing Cu as a main component, For example, Mg, Ag, Pd, Ti, Ta, A1, Nb, Zr or Zn are included. Also, a relatively thin copper (or copper alloy) seed film is formed on the conductive barrier film 18 by a sputtering method or a CVD method, and then, a relatively thick copper (or copper alloy) is formed on the seed film. The main conductor film 19 made of copper alloy) can be formed by a plating method (electrolytic plating method). This seed film can function to improve the adhesion between the main conductor film 19 and the conductive barrier film 18. Thereafter, a heat treatment is performed on the semiconductor substrate 1 in a non-oxidizing atmosphere (for example, a hydrogen atmosphere) at about 475 ° C. to reflow the main conductor film 19, and copper is deposited inside the wiring groove 17. Embedded without gaps.
次に、 図 6に示されるように、 主導体膜 1 9および導電性パリア膜 1 8を例え ば CMP法によって、 絶縁膜 1 5の上面が露出するまで研磨する。 絶縁膜 1 5上 の （すなわち配線溝 1 7外部の） 不要な導電性パリア膜 1 8および主導体膜 1 9 を除去し、 配線開口部としての配線溝 1 7内に導電性パリア膜 1 8および主導体 膜 1 9を残すことにより、 図 6に示されるように、 相対的に薄い導電性バリァ膜 1 8と相対的に厚い主導体膜 1 9とからなる配線 （第 1層配線） 2 0を配 ϋ溝 1 7内に形成する （埋込む)。 形成された配線 2 0は、 プラグ 1 3を介して η +型半 導体領域 （ソース、 ドレイン） 8やゲート電極 5と電気的に接続されている。 あ るいはエッチング （電解エッチングなど） により、 不要な導電性パリア膜 1 8お よび主導体膜 1 9を除去することもできる。  Next, as shown in FIG. 6, the main conductor film 19 and the conductive barrier film 18 are polished by, for example, a CMP method until the upper surface of the insulating film 15 is exposed. Unnecessary conductive barrier film 18 and main conductor film 19 on insulating film 15 (that is, outside wiring groove 17) are removed, and conductive barrier film 18 in wiring groove 17 as a wiring opening is removed. By leaving the main conductor film 19 and the main conductor film 19, as shown in FIG. 6, a wiring (first layer wiring) 2 composed of a relatively thin conductive barrier film 18 and a relatively thick main conductor film 19 is formed. 0 is formed (embedded) in the distribution groove 17. The formed wiring 20 is electrically connected to the η + type semiconductor region (source, drain) 8 and the gate electrode 5 via the plug 13. Unnecessary conductive barrier film 18 and main conductor film 19 can also be removed by etching (such as electrolytic etching).
次に、 図 7に示されるように、 配線溝 1 7内に残存する主導体膜 1 9の上部を 除去して、 配線溝 1 7内の主導体膜 1 9の上面を絶縁膜 1 5の上面よりも後退さ せ、 窪み （Recess : リセス） 2 1を形成する。 これにより、 主導体膜 1 9の上面 は、 絶縁膜 1 5の上面よりも下方に位置することになる。 すなわち、 主導体膜 1 9の上面は、 絶縁膜 1 5の上面よりも低くなる。 この窪み 2 1は、 例えば化学的 にエッチングする手法などにより形成することができる。 この場合、 例えば過酸 化水素水 (H 2 02) と塩酸 (H C 1 ) との混合液などを用いて、 銅膜 （主導体膜 1 9 ) を高選択比で （すなわち銅膜のエッチングレートが高くなるような条件で 選択的に） エッチングし、 エッチング時間を調整して主導体膜 1 9の上部だけを 除去して、 窪み 2 1を形成することができる。 また、 窪み 2 1を形成する他の手 法として、 主導体膜 1 9および導電性パリア膜 1 8を CMP処理する際に （すな わち図 6の工程で)、オーバーポリッシングを行って、窪み 2 1を形成することも できる。 オーバーポリツシングによって窪み 2 1を形成する場合は、 主導体膜 1 9の上面が皿型形状となるディッシングが生じないようにする。 Next, as shown in FIG. 7, the upper part of the main conductor film 19 remaining in the wiring groove 17 is removed, and the upper surface of the main conductor film 19 in the wiring groove 17 is It is recessed from the upper surface to form a recess (Recess) 21. As a result, the upper surface of the main conductor film 19 is located lower than the upper surface of the insulating film 15. That is, the upper surface of the main conductor film 19 is lower than the upper surface of the insulating film 15. The depression 21 can be formed by, for example, a technique of chemically etching. In this case, for example, by using a mixed solution of peroxide of hydrogen water (H 2 0 2) and hydrochloric acid (HC 1), a copper film (the main conductor film 1 9) with high selectivity (i.e. the copper etching Etching is performed (selectively under conditions that increase the rate), and the etching time is adjusted to remove only the upper portion of the main conductor film 19, thereby forming the depression 21. Also, the other hand that forms the depression 21 As a method, when the main conductor film 19 and the conductive barrier film 18 are subjected to the CMP process (that is, in the step of FIG. 6), the recess 21 may be formed by performing over polishing. When the depression 21 is formed by overpolishing, dishing in which the upper surface of the main conductor film 19 has a dish shape is prevented.
次に、 絶縁膜 1 5上の金属汚染を除去する処理を行う。 例えば、 半導体基板 1 の表面 （主導体膜 1 9および絶縁膜 1 5の表面） をフッ化水素 （H F ) を含む溶 液で洗浄することにより、 絶縁膜 1 5上の金属汚染を除去することができる。 絶 縁膜 1 5上に金属汚染が生じていると、 後述する金属キャップ膜 2 2の成膜の際 に、 その金属汚染物上にも金属キャップ膜 2 2の材料が成長してしまう可能性が ある力 S、 上記のように絶縁膜 1 5上の金属汚染を除去することで、 そのような金 属キャップ膜 2 2の材料の絶縁膜 1 5上での成長を抑制または防止し、 配線 2 0 (主導体膜 1 9 )上に金属キャップ膜 2 2をより選択性よく ほたは優先性よく） 形成することが可能になる。  Next, a process for removing metal contamination on the insulating film 15 is performed. For example, removing the metal contamination on the insulating film 15 by cleaning the surface of the semiconductor substrate 1 (the surface of the main conductor film 19 and the insulating film 15) with a solution containing hydrogen fluoride (HF). Can be. If metal contamination occurs on the insulating film 15, the material of the metal cap film 22 may grow on the metal contaminant during the formation of the metal cap film 22 described later. By removing the metal contamination on the insulating film 15 as described above, the growth of the material of the metal cap film 22 on the insulating film 15 is suppressed or prevented, and the wiring is formed. It is possible to form the metal cap film 22 on the 20 (main conductor film 19) with higher selectivity and higher priority.
それから、 絶縁膜 1 5表面の未結合手 （ダングリングポンド） の活性を低下さ せる処理を行う。 例えば、 還元性ガスを含む雰囲気中 （例えば水素を含む雰囲気 中） でァニール処理 （熱処理） することにより、 絶縁膜 1 5表面の未結合手の活 性を低下させることができる。 これにより、 後述する金属キャップ膜 2 2の成膜 の際に、配線 2 0 (主導体膜 1 9 )上に金属キヤップ膜 2 2をより選択性よく （ま たは優先性よく） 形成することが可能になる。 なお、 この処理においては、 モノ シランガス ( S i H 4) などの銅 ( C u ) と反応して合金を形成するような雰囲 気は、 配線抵抗値を著しく増大させてしまう可能性があるので、 適していない。 次に、 図 8に示されるように、 配線 2 0 (主導体膜 1 9 ) 上に第 1の金属キヤ ップ膜として金属キャップ膜 （第 1キャップ導体膜） 2 2を選択成長または優先 成長させる。 金属キャップ膜 2 2は、 例えばタングステン （W) 膜またはタンダ ステン合金膜 （あるいはタングステンを主成分とする導体膜） などからなる。 金 属キャップ膜 2 2は、 選択タングステン C V D法などによって形成することがで きる。 例えば、 六フッ化タングステン (WF 6) および水素 （H 2) ガスを用いた C V D法により、 絶縁膜 1 5から露出した配線 2 0 (主導体膜 1 9 ) の上面上に Then, a treatment for reducing the activity of dangling pounds on the surface of the insulating film 15 is performed. For example, by performing an annealing treatment (heat treatment) in an atmosphere containing a reducing gas (for example, in an atmosphere containing hydrogen), the activity of dangling bonds on the surface of the insulating film 15 can be reduced. This allows the metal cap film 22 to be formed more selectively (or more preferentially) on the wiring 20 (main conductor film 19) when forming the metal cap film 22 described later. Becomes possible. Incidentally, in this process, Kiri囲gas so as to form an alloy by reacting with copper (C u), such as mono-silane gas (S i H 4), there is a possibility that significantly increases the wiring resistance value Not so suitable. Next, as shown in FIG. 8, a metal cap film (first cap conductor film) 22 is selectively grown or preferentially grown as a first metal cap film on the wiring 20 (main conductor film 19). Let it. The metal cap film 22 is made of, for example, a tungsten (W) film or a tungsten alloy film (or a conductor film containing tungsten as a main component). The metal cap film 22 can be formed by a selective tungsten CVD method or the like. For example, by using a CVD method using tungsten hexafluoride (WF 6 ) and hydrogen (H 2 ) gas, the upper surface of the wiring 20 (main conductor film 19) exposed from the insulating film 15 is formed.
z膜を選択的に堆積することにより、 金属キャップ膜 2 2を形成する ことができる。 また、 無電解めつき法によって、 C oWP、 C oWBまたは Co Wなどからなる金属キャップ膜 22を絶縁膜 1 5から露出した配線 20 (主導体 膜 1 9) の上面上に選択的に形成することもできる。 金属キャップ膜 22の材料 としては、 タングステン (W)、 タングステン合金 (W合金、 Wを主成分とする合 金)、 コバルト (C o), コバルト合金 (C o合金、 C oを主成分とする合金）、 二 ッケル (N i ) またはニッケル合金 (N i合金、 N iを主成分とする合金) など を用いることができ、 例えば、 Wを材料 （主成分） とする W， WN, WNCまた はコパノレトを材料（主成分) とする C o， Co P, C oW, C oWP, CoWB, C o S nP, C oMo Pまたは N iを材料 （主成分） とする N i , N i W, N i Pなどを用いることができる。 Forming metal cap film 22 by selective deposition of z film be able to. In addition, a metal cap film 22 made of CoWP, CoWB, CoW, or the like is selectively formed on the upper surface of the wiring 20 (main conductor film 19) exposed from the insulating film 15 by an electroless plating method. You can also. Examples of the material of the metal cap film 22 include tungsten (W), a tungsten alloy (a W alloy, an alloy containing W as a main component), cobalt (Co), a cobalt alloy (a Co alloy, a component mainly containing Co). Alloys), nickel (Ni) or nickel alloys (Ni alloys, Ni-based alloys). For example, W, WN, WNC or W-based materials (main components) can be used. Are Co, CoP, CoW, CoWP, CoWB, CoSnP, CoMoP, or NiMo, whose main component is copanoleto, Ni, NiW, NiP or the like can be used.
図 9は、 導電性パリア膜 1 8の材料と金属キャップ膜 22の形成方法の関係を 示す説明図 （表） である。  FIG. 9 is an explanatory diagram (table) showing the relationship between the material of the conductive barrier film 18 and the method of forming the metal cap film 22.
金属キャップ膜 22の形成法として選択タングステン CVD法を用いる場合は、 導電性パリア膜 1 8が高融点金属膜 （例えばチタン （T i ) 膜、 タンタル (T a) 膜、 タングステン （W) 膜などの純金属膜） を含んでいなければより好ましい。 この場合、 導電性パリア膜 1 8として、例えば窒化チタン （T i N)、 窒化タンタ ル （T aN) または窒化タングステン （WN) などのような高融点金属窒ィ匕物、 またはそのような高融点金属窒ィ匕物にシリコン （S i ) を添加した材料を用いる ことができる。  When the selective tungsten CVD method is used as the method for forming the metal cap film 22, the conductive barrier film 18 is made of a refractory metal film (for example, a titanium (T i) film, a tantalum (Ta) film, a tungsten (W) film, or the like). Is more preferable. In this case, as the conductive barrier film 18, for example, a refractory metal nitride such as titanium nitride (TiN), tantalum nitride (TaN) or tungsten nitride (WN), or such a high-melting metal. A material obtained by adding silicon (S i) to the melting point metal nitride can be used.
本発明者の検討によれば、 導電性バリア膜 1 8が高融点金属膜 （純金属膜） を 含んでいる場合 （例えばタンタル （T a) 膜の単体膜またはタンタル （T a) 膜 と窒化タンタル (T aN) 膜との積層膜により導電性バリア膜 1 8を形成した場 合など） には、 配線 20上に金属キャップ膜 22を選択タングステン CVD法を 用いて形成すると、 導電性パリア膜 1 8の露出する端部上でタングステン （金属 キャップ膜 22) が異常成長する可能性があることが分かった。 導電性パリア膜 1 8が高融点金属膜 （純金属膜） を含んでいる場合に上記異常成長が生じる原因 は、 高融点金属 （純金属） による還元作用によって六フッ化タングステン （WF 6) ガスがそこで優先的に還元され、 タングステン （金属キャップ膜 22) が優 先的に成長する作用によるものと考えられる。 導電性パリア膜 1 8の端部上での )異常成長は、 配線 2 0の上面端部 （金属キャップ膜 2 2の端部） 近傍領域において後述する絶縁膜 2 3の力パレージ （coverage) を低下させ、 隣 り合う配線間の絶縁破壊耐性を低下させる可能性がある。 このため、 上記のよう に、 金属キャップ膜 2 2の形成法として選択タングステン C V D法を用いる場合 は、 導電性パリア膜 1 8が高融点金属膜 （純金属膜） を含んでいなければより好 ましい。 According to the study of the present inventor, when the conductive barrier film 18 includes a refractory metal film (pure metal film) (for example, a single film of a tantalum (Ta) film or a tantalum (Ta) film and a nitride film). In the case where the conductive barrier film 18 is formed of a laminated film with a tantalum (TaN) film, for example), the metal cap film 22 is selectively formed on the wiring 20 by using the selective tungsten CVD method. It was found that tungsten (metal cap film 22) could grow abnormally on the exposed end of 18. When the conductive barrier film 18 contains a high-melting-point metal film (pure metal film), the abnormal growth is caused by the reduction action of the high-melting-point metal (pure metal) by tungsten hexafluoride (WF 6 ) gas. Is preferentially reduced there, and it is thought that tungsten (metal cap film 22) grows preferentially. On the end of the conductive barrier film 18 ) Abnormal growth reduces the power coverage of the insulating film 23 described later in the vicinity of the upper end of the wiring 20 (the end of the metal cap film 22), and withstands dielectric breakdown between adjacent wirings. May be reduced. For this reason, as described above, when the selective tungsten CVD method is used as the method of forming the metal cap film 22, it is more preferable that the conductive barrier film 18 does not include a high melting point metal film (pure metal film). Good.
また、 本発明者の検討によれば、 金属キャップ膜 2 2の形成法として無電解め つき法を用いる場合は、 導電性パリア膜 1 8が高融点金属膜 （純金属膜） を含ん でいてもタングステン （金属キャップ膜 2 2 ) の異常成長は生じないことが分か つた。 このため、 金属キャップ膜 2 2の形成法として無電解めつき法を用いる場 合は、 導電性パリア虞 1 8が高融点金属膜を含んでいてもよレ、。 このため、 金属 キャップ膜 2 2の形成法として無電解めつき法を用いる場合は、 導電性パリア膜 1 8として、 例えばチタン （T i )、 タンタル (T a ) またはタングステン (W) などのような高融点金属や、 その合金膜（例えば窒化チタン（T i N) ,窒化タン タル（T a N)または窒化タングステン（WN)などのような高融点金属窒化物、 またはそのような高融点金属窒化物にシリコン （S i ) を添加した材料など） の 単体膜または積層膜を用いることができる。  According to the study of the present inventors, when the electroless plating method is used as the method for forming the metal cap film 22, the conductive barrier film 18 contains a high-melting-point metal film (pure metal film). It was also found that abnormal growth of tungsten (metal cap film 22) did not occur. For this reason, when the electroless plating method is used as the method for forming the metal cap film 22, the conductive barrier 18 may include a high melting point metal film. Therefore, when the electroless plating method is used as the method for forming the metal cap film 22, the conductive barrier film 18 may be made of, for example, titanium (T i), tantalum (T a), or tungsten (W). High melting point metal or alloy film thereof (for example, high melting point metal nitride such as titanium nitride (TiN), tantalum nitride (TaN) or tungsten nitride (WN), or such high melting point metal A single film or a stacked film of silicon (S i) added to a nitride can be used.
従って、 図 9に示されるように、 導電性パリア膜 1 8が高融点金属膜 （純金属 膜） を含む場合は金属キャップ膜 2 2を無電解めつき法により形成することが好 ましく、 導電性パリア膜 1 8が高融点金属膜 （純金属膜） を含まない場合は金属 キャップ膜 2 2を選択タングステン C V D法または無電解めっき法により形成す ることができる。  Therefore, as shown in FIG. 9, when the conductive barrier film 18 includes a refractory metal film (pure metal film), the metal cap film 22 is preferably formed by an electroless plating method. When the conductive barrier film 18 does not include a high melting point metal film (pure metal film), the metal cap film 22 can be formed by selective tungsten CVD or electroless plating.
また、 金属キャップ膜 2 2の膜厚 （堆積厚み） は、 2〜2 0 n mの範囲内 であることが好ましい。 金属キャップ膜 2 2の膜厚 が 2 0 n mよりも厚いと 、 金属キャップ膜 2 2の選択性が破れやすくなり、 絶縁膜 1 5上にも金属キヤッ プ膜 2 2の材料が堆積する可能性がある。 これは、 隣り合う同層配線間の絶縁破 壊而ォ性 (T D D B (Time Dependence on Dielectric Breakdown) 寿命） を低下さ せる可能性がある。 また、 金属キャップ膜 2 2の膜厚 が 2 n mよりも薄いと 、 金属キャップ膜 2 2を形成したことにより得られる効果、 すなわち後述するよ うに配線のエレクトロマイグレーシ 3ンゃストレスマイグレーション特性を向上 し、 埋込銅配線の信頼性および埋込銅配線を有する半導体装置の信頼性を向上で きるという効果が低下してしまう可能性がある。 The thickness (deposition thickness) of the metal cap film 22 is preferably in the range of 2 to 20 nm. When the thickness of the metal cap film 22 is larger than 20 nm, the selectivity of the metal cap film 22 is easily broken, and the material of the metal cap film 22 may be deposited on the insulating film 15. There is. This may reduce the dielectric breakdown (TDDB) time between adjacent same-level interconnects. When the thickness of the metal cap film 22 is smaller than 2 nm, the effect obtained by forming the metal cap film 22 can be obtained, that is, as will be described later. As described above, the effect of improving the electromigration and stress migration characteristics of the wiring and improving the reliability of the buried copper wiring and the semiconductor device having the buried copper wiring may be reduced.
また、 上記の窪み 2 1の深さ は、 金属キャップ膜 2 2の膜厚 とほぼ同じ であれば、 より好ましい。 窪み 2 1の深さ と金属キャップ膜 2 2の膜厚 と を同じにすることで、 金属キャップ膜 2 2の上面の高さ位置 （半導体基板 1の主 面に垂直な方向の高さ位置） と絶縁膜 1 5の上面の高さ位置 （半導体基板 1の主 面に垂直な方向の高さ位置） とをほぼ同じにすることができる。 これにより、 金 属キャップ膜 2 2の上面と絶縁膜 1 5の上面とがほぼ同一面上にあることになり 、 金属キャップ膜 2 2の上面と絶縁膜 1 5の上面とが略平面になる。  Further, it is more preferable that the depth of the depression 21 is substantially the same as the thickness of the metal cap film 22. By making the depth of the depression 21 equal to the thickness of the metal cap film 22, the height position of the upper surface of the metal cap film 22 (the height position in the direction perpendicular to the main surface of the semiconductor substrate 1) And the height position of the upper surface of the insulating film 15 (the height position in the direction perpendicular to the main surface of the semiconductor substrate 1) can be made substantially the same. As a result, the upper surface of the metal cap film 22 and the upper surface of the insulating film 15 are substantially on the same plane, and the upper surface of the metal cap film 22 and the upper surface of the insulating film 15 are substantially flat. .
また、 金属キャップ膜 2 2の成膜の際には、 金属キャップ膜 2 2の選択成長性 が破れて絶縁膜 1 5上にも金属キャップ膜 2 2の材料 （導体材料、 ここではタン ダステンまたはタングステン合金） が堆積する可能性がある。 配 ,镰を微細化した 場合は、 この絶縁膜 1 5上に堆積した導体材料が、 隣り合う同層配線間の絶縁破 壊耐性を低下させる可能性がある。 このため、 金属キャップ膜 2 2の形成後に、 例えばフッ酸 （フッ化水素酸： H F ) を少量含む溶液などを用いて半導体基板 1 の表面を洗浄し、 絶縁膜 1 5の極表面近傍領域ごとリフトオフして、 絶縁膜 1 5 上の不要な導体材料を完全に除去することがより好ましい。 これにより、 金属キ ヤップ膜 2 2の成膜の際に絶縁膜 1 5上に導体材料が成長し （選択性の破れが生 じ）、あるいは絶縁膜 1 5上の金属汚染物上に導体材料が成長した場合であっても 、 絶縁膜 1 5上のこれらの不要な導体材料および金属汚染物をエッチングし、 除 去することが可能となる。  In addition, when the metal cap film 22 is formed, the selective growth of the metal cap film 22 is broken and the material of the metal cap film 22 (the conductor material, here, tungsten or (Tungsten alloy) may be deposited. In the case where the wirings and wires are miniaturized, the conductor material deposited on the insulating film 15 may reduce the resistance to dielectric breakdown between adjacent wirings in the same layer. For this reason, after the formation of the metal cap film 22, the surface of the semiconductor substrate 1 is cleaned using a solution containing a small amount of hydrofluoric acid (hydrofluoric acid: HF), for example, and the entire region near the extreme surface of the insulating film 15 is cleaned. It is more preferable that lift-off is performed to completely remove unnecessary conductive material on the insulating film 15. As a result, when the metal cap film 22 is formed, the conductive material grows on the insulating film 15 (selectivity is broken), or the conductive material grows on the metal contaminants on the insulating film 15. Even when GaN grows, it becomes possible to etch and remove these unnecessary conductor materials and metal contaminants on the insulating film 15.
次に、 図 1 0に示されるように、 配線 2 0が埋め込まれた絶縁膜 1 5上に （す なわち、絶縁膜 1 5および金属キャップ膜 2 2上に)、絶縁膜（パリア絶縁膜） 2 3を形成する。 図 1 0は、 図 8に続く半導体装置の製造工程中における要部断面 図であり、 図 1の絶縁膜 1 1より下の構造に対応する部分は図示を省略している 。 絶縁膜 2 3は、 例えば炭窒化シリコン （S i C N) 膜などからなり、 銅配線の パリア絶縁膜として機能する。 従って、 絶縁膜 2 3は、 配線 2 0の主導体膜 1 9 中の銅が、 絶縁膜 2 4中などに拡散するのを抑制または防止する。 絶縁膜 2 3の 他の材料として、 例えば窒化シリコン （S i xN y) 膜、 炭化シリコン （S i C) 膜、 酸窒化シリコン （S i O N) 膜または酸炭ィ匕シリコン （S i O C) 膜を用い ても良い。 Next, as shown in FIG. 10, on the insulating film 15 in which the wiring 20 is embedded (that is, on the insulating film 15 and the metal cap film 22), the insulating film (the Palia insulating film) is formed. To form 23. FIG. 10 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 8, and a portion corresponding to a structure below the insulating film 11 in FIG. 1 is omitted. The insulating film 23 is made of, for example, a silicon carbonitride (SiCN) film and functions as a barrier insulating film for copper wiring. Therefore, the insulating film 23 suppresses or prevents copper in the main conductor film 19 of the wiring 20 from diffusing into the insulating film 24 or the like. Insulation film 2 3 Other materials, for example, using a silicon nitride (S i x N y) film, a silicon carbide (S i C) film, a silicon oxynitride (S i ON) film or Sansumyi匕silicon (S i OC) film Is also good.
本実施の形態とは異なり、 窪み 2 1を形成せずに金属キヤップ膜 2 2の上面の 高さ位置と絶縁膜 1 5の高さ位置とが異なっている （金属キャップ膜 2 2の上面 の高さ位置が絶縁膜 1 5上面の高さ位置よりも高い） 場合は、 金属キャップ膜 2 2の上面と絶縁膜 1 5の上面との間に段差が生じ、 絶縁膜 2 3を形成した際に、 絶縁膜 2 3にも下地の段差を反映して段差が生じてしまう。 図 1 1は、 窪み 2 1 を形成せずに金属キャップ膜 2 2の上面の高さ位置と絶縁膜 1 5の高さ位置とが 異なっている場合に絶縁膜 2 3を形成した状態を示す要部断面図であり、 本実施 の形態の図 1 0に対応する。 この場合、 図 1 1に示されるように、 配線 2 0の上 面端部 （金属キャップ膜 2 2の端部） 近傍領域において絶縁膜 2 3の力パレージ (coverage) またはステップ力パレージが悪くなる。 絶縁膜 （キャップ絶縁膜） 2 3のステップ力パレージが悪いと、 配線 2 0の端部での銅 （C u ) のバリア性 が劣化して隣り合う配線間のリーク電流レベルが増カロし、 絶縁破壌耐性が低下す る （T D D B寿命が短くなる） 可能性がある。  Unlike the present embodiment, the height position of the upper surface of the metal cap film 22 and the height position of the insulating film 15 are different without forming the depression 21 (the upper surface of the metal cap film 22). If the height position is higher than the height position of the upper surface of the insulating film 15), a step occurs between the upper surface of the metal cap film 22 and the upper surface of the insulating film 15, and when the insulating film 23 is formed. In addition, a step occurs in the insulating film 23 reflecting the step of the base. FIG. 11 shows a state in which the insulating film 23 is formed when the height position of the upper surface of the metal cap film 22 and the height position of the insulating film 15 are different without forming the depression 21. It is a principal part sectional view, and corresponds to FIG. 10 of this Embodiment. In this case, as shown in FIG. 11, in the region near the upper end of the wiring 20 (the end of the metal cap film 22), the force coverage or the step force rage of the insulating film 23 deteriorates. . If the step strength of the insulating film (cap insulating film) 23 is poor, the barrier property of copper (Cu) at the end of the wiring 20 is deteriorated, and the leakage current level between adjacent wirings increases, There is a possibility that insulation rupture resistance may be reduced (TDDB life may be shortened).
このため、 本実施の形態のように、 金属キヤップ膜 2 2の形成前に窪み 2 1を 形成し、 この窪み 2 1の深さ を金属キャップ膜 2 2の膜厚 W とほぼ同じにす ることが好ましい。 これにより、 金属キャップ膜 2 2の上面と絶縁膜 1 5の上面 とを略平面 （略同一平面） にすることができる。 従って、 図 1 0に示されるよう に、 絶縁膜 2 3に段差が生じるのを防止し、 配線 2 0の上端部 （金属キャップ膜 2 2の端部） 近傍領域における絶縁膜 2 3の力パレージを向上することができ、 隣り合う配線間の絶縁破壌耐性を向上することができる。 また、 窪み 2 1の深さ を深くしすぎると、 配線 2 0の銅 ( C u ) 成分が減少して配線 2 0の抵抗値 が増加する恐れがある力 窪み 2 1の深さ D を金属キャップ膜 2 2の膜厚 と ほぼ同じにすることで、 配線 2 0の銅 ( C u ) 成分の減少を抑制し、 配線 2 0の 抵抗増加を抑制または防止することができる。 また、 上記のように金属キャップ 膜 2 2の膜厚は比較的薄いが、 絶縁膜 1 5および金属キャップ膜 2 2上に銅のパ リァ性を有する絶縁膜 2 3を形成しているので、 この絶縁膜 2 3により配線 2 0 に対するバリァ性を十分に確保することができ、 隣り合う配線 2 0間のリーク電 流レベルを低下し、 絶縁破壌耐性を向上 （T D D B寿命を長く） することができ る。 Therefore, as in the present embodiment, the depression 21 is formed before the formation of the metal cap film 22, and the depth of the depression 21 is made substantially the same as the thickness W of the metal cap film 22. Is preferred. Thereby, the upper surface of the metal cap film 22 and the upper surface of the insulating film 15 can be made substantially flat (substantially the same plane). Therefore, as shown in FIG. 10, a step is prevented from being formed in the insulating film 23, and a force paradigm of the insulating film 23 in a region near the upper end of the wiring 20 (end of the metal cap film 22) is prevented. And the resistance to rupture of insulation between adjacent wirings can be improved. If the depth of the depression 21 is too large, the copper (Cu) component of the wiring 20 may decrease and the resistance value of the wiring 20 may increase. By making the thickness substantially equal to the thickness of the cap film 22, a decrease in the copper (Cu) component of the wiring 20 can be suppressed, and an increase in resistance of the wiring 20 can be suppressed or prevented. Further, as described above, the thickness of the metal cap film 22 is relatively small, but since the insulating film 23 having copper parity is formed on the insulating film 15 and the metal cap film 22, Wiring 20 by this insulating film 23 In this case, sufficient barrier properties can be ensured, the leakage current level between the adjacent wirings 20 can be reduced, and the insulation breakdown resistance can be improved (the TDDB life can be increased).
図 1 2〜図 1 8は、 図 1◦に続く半導体装置の製造工程中における要部断面図 を示している。 なお、 理解を簡単にするために、 図 1 2〜図 1 8においても、 図 1の絶縁膜 1 1より下の構造に対応する部分は図示を省略している。  FIGS. 12 to 18 are cross-sectional views of essential parts of the semiconductor device during the manufacturing process following FIG. In addition, for simplicity of understanding, also in FIGS. 12 to 18, parts corresponding to the structure below the insulating film 11 in FIG. 1 are not shown.
絶縁膜 2 3の形成後、 図 1 2に示されるように、 絶縁膜 2 3上に絶縁膜 （層間 絶縁膜） 2 4、 絶縁膜 （エッチングストッパ膜） 2 5および絶縁膜 （層間絶縁膜 ) 2 6を形成する。 絶縁膜 2 4は絶縁膜 1 5と同様の材料 （低誘電率材料） によ り形成することができ、 絶縁膜 2 5は絶縁膜 1 4または絶縁膜 2 3と同様の材料 により形成することができ、 絶縁膜 2 6は絶縁膜 1 5と同様の材料 （低誘電率材 料） により形成することができる。  After the formation of the insulating film 23, as shown in FIG. 12, the insulating film (interlayer insulating film) 24, the insulating film (etching stopper film) 25, and the insulating film (interlayer insulating film) are formed on the insulating film 23. Form 2 6 The insulating film 24 can be formed of the same material (low dielectric constant material) as the insulating film 15, and the insulating film 25 can be formed of the same material as the insulating film 14 or the insulating film 23. The insulating film 26 can be formed of the same material (low dielectric constant material) as the insulating film 15.
次に、 図 1 3に示されるように、 フォトリソグラフィ法などを用いて絶縁膜 2 3〜2 6をドライエッチング （選択的に除去） することなどによって、 配線開口 部すなわち、 配線 2 0に達するスルーホールまたはビア （開口部） 3 0および配 線溝 （開口部） 3 1を形成する。 このとき、 ビア 3 0の底部では、 金属キャップ 膜 2 2の全部または一部が除去 （エッチング） されており、 主導体膜 1 9の上面 が露出される。 配線溝 3 1は絶縁膜 2 5， 2 6を選択的に除去することにより形 成されており、 ビア 3 0は、 配線溝 3 1の底部で、 絶縁膜 2 3， 2 4および金属 キャップ膜 2 2の一部を選択的に除去することにより形成されている。 このため 、 ビア 3 0は、 配線溝 3 1の底部から絶縁膜 2 3， 2 4と金属キャップ膜 2 2の 一部を貫通して主導体膜 1 9に到達し、 ビア 3 0の底部で主導体膜 1 9が露出す る。  Next, as shown in FIG. 13, the insulating films 23 to 26 are dry-etched (selectively removed) by using a photolithography method or the like to reach the wiring opening, that is, the wiring 20. A through hole or via (opening) 30 and a wiring groove (opening) 31 are formed. At this time, all or part of the metal cap film 22 has been removed (etched) at the bottom of the via 30, exposing the upper surface of the main conductor film 19. The wiring groove 31 is formed by selectively removing the insulating films 25 and 26, and the via 30 is formed at the bottom of the wiring groove 31 by the insulating films 23 and 24 and the metal cap film. It is formed by selectively removing a part of 22. For this reason, the via 30 penetrates from the bottom of the wiring groove 31 through the insulating films 23 and 24 and a part of the metal cap film 22 to reach the main conductor film 19, and is formed at the bottom of the via 30. The main conductor film 19 is exposed.
上記のように金属キャップ膜 2 2の膜厚は比較的薄いので、 本実施の形態とは 異なり、 もしビア 3 0の底部で金属キヤップ膜 2 2が残存するようにビア 3 0形 成のドライエッチングを行うと、 エッチング不足によりビア 3 0底部で金属キヤ ップ膜 2 2上の絶縁膜 2 3の一部が残存してビア 2 0が配線 2 0に到達しない可 能性が生じる。 これは、 上層配線 （後述する配線 3 5 ) と下層配線 （配線 2 0 ) との間の電気的接続の信頼性を低下させる。 本実施の形態では、 ビア 3 0の底部 で金属キャップ膜 2 2も除去し、 ビア 3 0の底部で主導体膜 1 9が露出するよう に、 ビア 3 0形成のドライエッチングを行う。 すなわち、 ビア 3 0形成の際に、 すなわち主導体膜 1 9が露出するまでオーバーエッチングを行い、 ビア 3 0が配 線溝 3 1の底部から絶縁膜 2 3， 2 4と金属キャップ膜 2 2とを貫通して主導体 膜 1 9に到達するようにする。 このため、 エッチング不足 （ビア 3 0底部での絶 縁膜 2 3の残存） は生じにくく、 ビア 3 0を配線 2 0に確実に到達させることが できる。 従って、 上層配泉 （後述する配線 3 5 ) と下層配 ,镰 （配線 2 0 ) との間 の電気的接続の信頼性を向上することができる。 Since the thickness of the metal cap film 22 is relatively small as described above, unlike the present embodiment, if the metal cap film 22 is formed so that the metal cap film 22 remains at the bottom of the via 30, the dry formation of the via 30 is performed. When the etching is performed, there is a possibility that a portion of the insulating film 23 on the metal cap film 22 remains at the bottom of the via 30 due to insufficient etching, and the via 20 does not reach the wiring 20. This lowers the reliability of the electrical connection between the upper wiring (wiring 35 described later) and the lower wiring (wiring 20). In the present embodiment, the bottom of via 30 Then, the metal cap film 22 is also removed, and the dry etching for forming the via 30 is performed so that the main conductor film 19 is exposed at the bottom of the via 30. That is, over-etching is performed when the via 30 is formed, that is, until the main conductor film 19 is exposed, and the via 30 is formed from the bottom of the wiring groove 31 by the insulating films 23 and 24 and the metal cap film 22. To reach the main conductor film 19. For this reason, insufficient etching (the insulating film 23 remains at the bottom of the via 30) is unlikely to occur, and the via 30 can reliably reach the wiring 20. Therefore, the reliability of the electrical connection between the upper layer distribution (wiring 35 described later) and the lower layer distribution 镰 (wiring 20) can be improved.
次に、 必要に応じて、 ビア 3 0の底部および側壁のェッチング残渣物を取り除 く洗浄処理と、 還元性ガスを含む雰囲気中でのァニール処理を行う。 これにより 、 ビア 3 0の底部および側壁のエッチング残渣物を除去して清浄化し、 ビア 3 0 の底部で露出する配線 2 0 (主導体膜 1 9 ) の表面に形成された酸化銅を除去 ( 還元） して配線 2 0 (主導体膜 1 9 ) の露出面を清浄化 (クリーニング) するこ とができる。  Next, if necessary, a cleaning process for removing etching residues on the bottom and side walls of the via 30 and an annealing process in an atmosphere containing a reducing gas are performed. As a result, the etching residue on the bottom and side walls of the via 30 is removed and cleaned, and the copper oxide formed on the surface of the wiring 20 (main conductor film 19) exposed at the bottom of the via 30 is removed ( Thus, the exposed surface of the wiring 20 (main conductor film 19) can be cleaned (cleaned).
次に、 図 1 4に示されるように、 ビア 3 0の底部で露出する主導体膜 1 9を塞 ぐために、 ビア 3 0底部で露出する配線 2 0 (主導体膜 1 9 ) 上に第 2の金属キ ヤップ膜として金属キャップ膜 （第 2キャップ導体膜） 3 2を選択成長または優 先成長させる。 これにより、 金属キャップ膜 3 2は金属キャップ膜 2 2につなが り、 主導体膜 1 9の上面が金属キャップ膜 2 2および金属キャップ膜 3 2によつ て覆われることになる。 金属キャップ膜 3 2は、 金属キャップ膜 2 2と同様の材 料により形成することができ、 例えばタングステン (W) 膜またはタングステン 合金膜 （あるいはタングステンを主成分とする導体膜） などからなる。 また、 金 属キャップ膜 3 2は、 金属キャップ膜 2 2と同様の手法により形成することがで きる。 例えば選択タングステン C V D法によって金属キャップ膜 3 2を形成する ことができる。 この場合、 例えば六フッ化タングステン (WF 6 ) および水素 ( H 2) ガスを用いた C V D法により、 ビア 3 0底部で露出した配線 2 0 (主導体 膜 1 9 ) 上にタングステン膜を選択的に堆積することにより、 金属キャップ膜 3 2を形成することができる。 また、 無電解めつき法によって、 C o WP、 C o W Bまたは C o Wなどからなる金属キャップ膜 3 2をビア 3 0底部で露出した配線 20 (主導体膜 1 9) 上に選択的に形成することもできる。 金属キャップ膜 32 の材料としては、 タングステン (W)、 タングステン合金 (W合金、 Wを主成分と する合金)、 コノルト （C o)、 コバルト合金 （C o合金、 C oを主成分とする合 金)、 ニッケル（N i ) またはニッケル合金 (N i合金、 N iを主成分とする合金 ) などを用いることができ、 例えば、 Wを材料 （主成分） とする" W, WN, WN Cまたはコバルトを材料 （主成分） とする Co， C o P, C oW, C oWP, C oWB, Co S nP, C oMo Pまたは N iを材料 （主成分） とする N i , N i W, N i Pなどを用いることができる。 Next, as shown in FIG. 14, a second conductive layer 19 on the bottom of the via 30 (the main conductive layer 19) is covered with the second conductive layer 19 to cover the main conductive layer 19 exposed at the bottom of the via 30. A metal cap film (second cap conductor film) 32 is selectively grown or preferentially grown as a metal cap film. As a result, the metal cap film 32 is connected to the metal cap film 22, and the upper surface of the main conductor film 19 is covered with the metal cap film 22 and the metal cap film 32. The metal cap film 32 can be formed of the same material as the metal cap film 22 and is made of, for example, a tungsten (W) film or a tungsten alloy film (or a conductor film containing tungsten as a main component). The metal cap film 32 can be formed by the same method as the metal cap film 22. For example, the metal cap film 32 can be formed by a selective tungsten CVD method. In this case, for example, a tungsten film is selectively formed on the wiring 20 (main conductor film 19) exposed at the bottom of the via 30 by a CVD method using tungsten hexafluoride (WF 6 ) and hydrogen (H 2 ) gas. The metal cap film 32 can be formed. The metal cap film 32 made of Co WP, Co WB, or Co W is exposed at the bottom of the via 30 by the electroless plating method. 20 (main conductor film 19) can also be selectively formed. Examples of the material of the metal cap film 32 include tungsten (W), tungsten alloy (W alloy, alloy containing W as a main component), conort (Co), and cobalt alloy (Co alloy, containing Co as a main component). Gold), nickel (Ni) or a nickel alloy (Ni alloy, Ni-based alloy) can be used. For example, W is a material (main component). "W, WN, WNC Alternatively, Co, CoP, CoW, CoWP, CoWB, CoSnP, CoMoP or Ni using cobalt as a material (main component) and Ni, NiW, NiP or the like can be used.
金属キャップ膜 32の膜厚 （堆積厚み） W2は、 2〜20 nmの範囲内である ことが好ましい。 金属キャップ膜 32の膜厚 W2が 20 nmよりも厚いと、 W ( タングステン） 膜の比抵抗は Cu (銅） 膜よりも大きいため W (タングステン） 成分の増カ卩によって抵抗が増加する、 あるいは W (タングステン) 膜 （金属キヤ ップ膜 32) の表面凹凸の増大によって導電性パリア膜 33の被覆率の低下を招 く恐れがある。 また、 金属キャップ膜 22の膜厚 W が 2 nmよりも薄いと、 金 属キャップ膜 22を形成したことにより得られる効果、 すなわち後述するように 配線のエレクトロマイグレーションゃストレスマイグレーション特性を向上し、 埋込銅配線の信頼性および埋込銅配線を有する半導体装置の信頼性を向上できる という効果が低下してしまう可能性がある。 Thickness (deposition thickness) W 2 of the metal cap film 32 is preferably in the range of 2 to 20 nm. If the thickness W 2 of the metal cap film 32 is greater than 20 nm, the specific resistance of the W (tungsten) film is larger than that of the Cu (copper) film, so that the resistance is increased by increasing the W (tungsten) component. Alternatively, the coverage of the conductive barrier film 33 may decrease due to an increase in the surface irregularities of the W (tungsten) film (metal cap film 32). When the thickness W of the metal cap film 22 is smaller than 2 nm, the effect obtained by forming the metal cap film 22, that is, as described later, the electromigration of the wiring and the stress migration characteristics are improved and the embedding is improved. There is a possibility that the effect of improving the reliability of the embedded copper wiring and the reliability of the semiconductor device having the embedded copper wiring is reduced.
また、 金属キャップ膜 32を形成する際には、 選択性の破れが多少あっても差 し支えない。 その理由は、 絶縁膜 26上に金属キャップ膜 32の材料 （導体材料 ) が多少堆積したとしても、 後述する配線 35を形成するための CMP工程で絶 縁膜 26上の不要な導体材料を除去できるからである。 このため、 金属キャップ 膜 22の形成前にはフッ化水素 （HF) を含む溶液による洗浄で絶縁膜 1 5上の 金属汚染を除去する処理を行ったが、 金属キャップ膜 32の形成前には、 このフ ッ化水素 （HF) を含む溶液による洗浄で絶縁膜 26上の金属汚染を除去する処 理を省略することも可能である。 これにより、 製造工程数を低減できる。  In forming the metal cap film 32, selectivity may be slightly broken. The reason is that even if the material (conductor material) of the metal cap film 32 is slightly deposited on the insulating film 26, the unnecessary conductor material on the insulating film 26 is removed in the CMP process for forming the wiring 35 described later. Because you can. For this reason, before forming the metal cap film 22, a process of removing metal contamination on the insulating film 15 by cleaning with a solution containing hydrogen fluoride (HF) was performed. However, it is also possible to omit the process of removing metal contamination on the insulating film 26 by cleaning with a solution containing hydrogen fluoride (HF). Thereby, the number of manufacturing steps can be reduced.
また、 金属キャップ膜 22の形成前には、 還元性ガスを含む雰囲気中 （例えば' 水素を含む雰囲気中） でァニール処理することにより、 絶縁膜 1 5表面の未結合 手 （ダングリングボンド） の活性を低下させる処理を行ったが、 この還元性ガス を含む雰囲気中でのァニール処理は、 金属キヤップ膜 3 2の形成前にも行うこと がより好ましい。 このような処理により、 ビア 3 0底部で露出する主導体膜 1 9 表面に形成された酸化銅を還元し、 界面抵抗を下げる効果を得ることができる。 また、 金属キャップ膜 2 2の形成後には、 フッ酸 （フッ化水素酸： H F ) を少 量含む溶液などを用いて半導体基板 1の表面を洗浄して絶縁膜 1 5上の不要な導 体材料を完全に除去する処理を行ったが、 金属キャップ膜 3 2の選択性の破れが 大きな問題とならなければ、 金属キャップ膜 3 2の形成後には、 このフッ酸を含 む溶液による洗浄処理を省略することもできる。 これにより、 製造工程数を低減 できる。 Before the formation of the metal cap film 22, annealing treatment is performed in an atmosphere containing a reducing gas (for example, in an atmosphere containing hydrogen) to reduce dangling bonds on the surface of the insulating film 15. Although the treatment to reduce the activity was performed, this reducing gas It is more preferable to perform the annealing treatment in an atmosphere including the following before the metal cap film 32 is formed. By such a treatment, copper oxide formed on the surface of the main conductor film 19 exposed at the bottom of the via 30 can be reduced, and an effect of reducing interface resistance can be obtained. After the formation of the metal cap film 22, the surface of the semiconductor substrate 1 is washed with a solution containing a small amount of hydrofluoric acid (hydrofluoric acid: HF) to remove unnecessary conductors on the insulating film 15. Although the material was completely removed, if the breakage of the selectivity of the metal cap film 32 was not a major problem, the cleaning treatment with a solution containing hydrofluoric acid was performed after the formation of the metal cap film 32. Can also be omitted. Thereby, the number of manufacturing steps can be reduced.
金属キャップ膜 3 2の形成後、 図 1 5に示されるように、 半導体基板 1の主面 上の全面 （すなわちビア 3◦の底部および側壁上と配線溝 3 1の底部および側壁 上とを含む絶縁膜 2 6上） に、 例えば厚さ 5 0 n m程度の比較的薄い導電性パリ ァ膜 （パリア導体膜） 3 3を形成する。 従って、 ビア 3 0の底部では、 金属キヤ ップ膜 3 2上に導電性パリア膜 3 3が形成されることになる。 導電性パリア膜 3 3は、 導電性パリア膜 1 8と同様の手法により形成することができ、 スパッタリ ング法、 C V D法または原子層デポジション（A L D： Atomic Layer Deposition) 法などを用いて形成することができる。 導電性パリア膜 3 3は、 導電性パリァ膜 1 8と同様、 例えば後述の主導体膜形成用の銅の拡散を抑制または防止する機能 や主導体膜のリフロー時に銅の濡れ性を向上させる機能、 あるいは銅 （銅膜） の 接着性を高める機能などを有している。 導電性パリア膜 3 3の材料としては、 導 電性パリア膜 1 8と同様の材料を用いることができ、例えばチタン（T i )、 タン タル （T a ) またはタングステン （W) などのような高融点金属や、 その合金膜 (例えば窒化チタン (T i N)、望化タンタル (T a N) または窒化タングステン (WN) などのような高融点金属窒化物、 またはそのような高融点金属窒化物に シリコン （S i ) を添加した材料 （例えば T i S i N, T a S i N, W S i N) など） を用いることができる。 また、 導電性パリア膜 3 3としては、 上記材料膜 の単体膜だけでなく積層膜を用いることもできる。  After the formation of the metal cap film 32, as shown in FIG. 15, as shown in FIG. 15, the entire surface of the semiconductor substrate 1 (including the bottom and side walls of the via 3 ° and the bottom and side walls of the wiring groove 31) On the insulating film 26), a relatively thin conductive barrier film (paria conductor film) 33 having a thickness of, for example, about 50 nm is formed. Therefore, at the bottom of the via 30, the conductive barrier film 33 is formed on the metal cap film 32. The conductive barrier film 33 can be formed by a method similar to that of the conductive barrier film 18 and is formed by using a sputtering method, a CVD method, an atomic layer deposition (ALD) method, or the like. be able to. The conductive barrier film 33, like the conductive barrier film 18, has, for example, a function of suppressing or preventing the diffusion of copper for forming a main conductor film described later and a function of improving the wettability of copper during reflow of the main conductor film. Or, it has a function to enhance the adhesiveness of copper (copper film). As the material of the conductive barrier film 33, the same material as that of the conductive barrier film 18 can be used, for example, such as titanium (T i), tantalum (T a), or tungsten (W). Refractory metal or its alloy film (for example, refractory metal nitride such as titanium nitride (T iN), tantalum peroxide (T aN) or tungsten nitride (WN), or such refractory metal nitride A material obtained by adding silicon (Si) to an object (for example, TiSiN, TaSiN, WSiN) can be used. Further, as the conductive barrier film 33, not only a single film of the above-mentioned material film but also a laminated film can be used.
また、 導電性パリア膜 3 3形成前の前処理として、 一般的なダマシン配線では アルゴン （A r ) イオンによる物理的スパッタエッチングを行うことが多いが、 アルゴン (A r ) イオンによる物理的スパッタエッチングを行うとビア 3 0底部 の金属キャップ膜 3 2が除去される可能性があるので、 本実施の形態では、 導電 性パリア膜 3 3形成前の前処理として、 還元性ガスを含む雰囲気 （例えば水素雰 囲気） 中における反応性プラズマ処理を行うことがより好ましい。 これにより、 ビア 3 0底部の金属キャップ膜 3 2が除去されるのを防止するとともに、 金属キ ヤップ膜 3 2の表面を還元処理することができ、 金属キャップ膜 3 2上を含むビ ァ 3◦および配線溝 3 1の底面および側壁上に導電性パリア膜 3 3を的確に形成 することができる。 Also, as a pre-treatment before the formation of the conductive barrier film 33, physical damping wiring is generally subjected to physical sputter etching using argon (Ar) ions. Since the metal cap film 32 at the bottom of the via 30 may be removed by performing physical sputter etching using argon (Ar) ions, in the present embodiment, before the conductive barrier film 33 is formed, As the treatment, it is more preferable to carry out a reactive plasma treatment in an atmosphere containing a reducing gas (for example, a hydrogen atmosphere). This prevents the metal cap film 32 at the bottom of the via 30 from being removed, and at the same time, reduces the surface of the metal cap film 32 so that the via 3 including on the metal cap film 32 can be reduced. The conductive barrier film 33 can be accurately formed on the bottom surface and the side wall of the wiring groove 31.
次に、 図 1 6に示されるように、 導電性パリア膜 3 3上に （すなわち半導体基 板 1上に)、相対的に厚い銅からなる主導体膜（銅膜） 3 4を形成する。主導体膜 3 4は、主導体膜 1 9と同様の手法により形成することができ、例えば C V D法、 スパッタリング法またはめつき法などを用いて形成することができる。 また、 主 導体膜 3 4は、 主導体膜 1 9と同様の材料により形成することができ、 銅を主成 分とする導体膜、例えば銅または銅合金 ( C uを主成分とし、例えば M g， A g， P d， T i， T a , A l， N b， Z rまたは Z nなどを含む） により形成するこ とができる。 また、 導電性パリア膜 3 3上に、 相対的に薄い銅 （または銅合金） などからなるシード膜をスパッタリング法または C V D法などによって形成し、 その後、 シード膜上に相対的に厚い銅 （または銅合金） などからなる主導体膜 3 4をめつき法 （電解めつき法） などによって形成することもできる。 このシード 膜は、 主導体膜 3 4と導電性パリア膜 3 3の密着性を向上させるよう機能するこ とができる。その後、例えば 4 7 5 °C程度の非酸ィ匕性雰囲気（例えば水素雰囲気） 中において半導体基板 1に対して熱処理を施すことにより主導体膜 3 4をリフロ 一させ、 銅をビア 3 0および配線溝 3 1の内部に隙間なく埋め込む。  Next, as shown in FIG. 16, a main conductor film (copper film) 34 made of relatively thick copper is formed on the conductive barrier film 33 (that is, on the semiconductor substrate 1). The main conductor film 34 can be formed by a method similar to that of the main conductor film 19, and can be formed by using, for example, a CVD method, a sputtering method, or a plating method. The main conductor film 34 can be formed of the same material as the main conductor film 19, and can be a conductor film containing copper as a main component, for example, copper or a copper alloy (containing Cu as a main component, for example, M g, Ag, Pd, Ti, Ta, Al, Nb, Zr, or Zn). Also, a relatively thin seed film made of copper (or copper alloy) is formed on the conductive barrier film 33 by a sputtering method or a CVD method, and then, a relatively thick copper (or copper alloy) is formed on the seed film. The main conductor film 34 made of copper alloy or the like may be formed by a plating method (electrolytic plating method). This seed film can function to improve the adhesion between the main conductor film 34 and the conductive barrier film 33. Thereafter, the main conductor film 34 is reflowed by subjecting the semiconductor substrate 1 to a heat treatment in a non-oxidizing atmosphere (for example, a hydrogen atmosphere) at about 475 ° C. It is embedded in the wiring groove 31 without any gap.
次に、 図 1 7に示されるように、 主導体膜 3 4および導電性パリア膜 3 3を例 えば CMP法によって、 絶縁膜 2 6の上面が露出するまで研磨する。 絶縁膜 2 6 上の （すなわちビア 3 0および配線溝 3 1の外部の） 不要な導電性パリア膜 3 3 および主導体膜 3 4を除去し、 配線溝 3 1およびビア 3 0内に導電性パリア膜 3 3および主導体膜 3 4を残すことにより、 図 1 7に示されるように、 相対的に薄 い導電性パリア膜 3 3と相対的に厚い主導体膜 3 4とからなる配線 (第 2層配線） 3 5を形成する（配線溝 3 1およびビア 3 0内に埋込む)。形成された配線 3 5の 配線部 （配線溝 3 1に埋込まれた導電性パリア膜 3 3および主導体膜 3 4 ) は、 配線 3 5のビア部 （ビア 3 0に埋込まれた導電性パリア膜 3 3および主導体膜 3 4 ) を介して配線 2 0と電気的に接続されている。 また、 選択性の破れによって 絶縁膜 2 6上に金属キャップ膜 3 2の材料が堆積した場合は、 この CMP工程で 主導体膜 3 4および導電性パリア膜 3 3と一緒に除去することができる。 また、 CMPの代わりにエッチング （電解エッチングなど） により、 不要な導電性パリ ァ膜 3 3および主導体膜 3 4を除去することもできる。 Next, as shown in FIG. 17, the main conductor film 34 and the conductive barrier film 33 are polished by, eg, CMP until the upper surface of the insulating film 26 is exposed. Unnecessary conductive barrier film 33 and main conductor film 34 on insulating film 26 (ie, outside of via 30 and wiring groove 31) are removed, and conductive film in wiring groove 31 and via 30 is removed. By leaving the Paria film 33 and the main conductor film 34, as shown in FIG. 17, a wiring composed of a relatively thin conductive barrier film 33 and a relatively thick main conductor film 34 ( 2nd layer wiring) 35 is formed (buried in the wiring groove 31 and the via 30). The wiring portion of the formed wiring 35 (the conductive barrier film 33 and the main conductor film 34 buried in the wiring groove 31) is a via portion of the wiring 35 (the conductive film buried in the via 30). It is electrically connected to the wiring 20 via the conductive barrier film 33 and the main conductor film 34). Further, when the material of the metal cap film 32 is deposited on the insulating film 26 due to the breakage of the selectivity, it can be removed together with the main conductor film 34 and the conductive barrier film 33 in this CMP step. . Unnecessary conductive barrier film 33 and main conductor film 34 can also be removed by etching (such as electrolytic etching) instead of CMP.
その後、 図 7、 図 8、 図 1 0および図 1 2〜1 7の工程を繰り返して、 更に上 層配線を形成することができる。 例えば、 図 1 8に示されるように、 配線 3 5に 対して窪み 2 1と同様の窪みを形成した後、 配線 3 5上に第 1の金属キャップ膜 として金属キヤップ膜 4 2を金属キヤップ膜 2 2と同様の材料および手法により 形成し、 その後、 配線 3 5が埋め込まれた絶縁膜 2 6上に、 上記絶縁膜 2 3〜2 6を形成した工程と同様の工程および材料によって、 絶縁膜 （パリア絶縁膜） 4 3、 絶縁膜 （層間絶縁膜） 4 4、 絶縁膜 （エッチングストッパ膜） 4 5および絶 縁膜 （層間絶縁膜） 4 6を形成する。 それから、 フォトリソグラフィ法などを用 いて絶縁膜 4 3〜4 6をドライエッチングすることなどによって、 ビア 3 0およ び配線溝 3 1と同様にして、 配線 3 5に達し金属キヤップ膜 4 2を貫通して配線 3 5の主導体膜 3 4を露出するビア （開口部） 5 0と配線溝 （開口部） 5 1とを 形成し、 ビア 5 0底部で露出する配線 3 5 (主導体膜 3 4 ) 上に第 2の金属キヤ ップ膜として金属キャップ膜 5 2を金属キャップ膜 3 2と同様の材料および手法 により形成する。 その後、 半導体基板 1上 （ビア 5 0および配線溝 5 1の底部お よび側壁を含む絶縁膜 4 6上） に、 導電性パリア膜 （パリア導体膜） 5 3を導電 性パリア膜 1 8， 3 3と同様の材料および手法により形成し、 導電性パリァ膜 5 3上にビア 5 0および配線溝 5 1を埋めるように主導体膜 5 4を主導体膜 1 9， 3 4と同様の材料および手法により形成し、 CMP法により絶縁膜 4 6上の不要 な主導体膜 5 4および導電性パリア膜 5 3を除去してビア 5 0および配線溝 5 1 を埋めかつ配線 3 5と電気的に接続された配線 （第 3層配線） 5 5を形成する。 更に同様にして、 上層配線 （第 4層配線） を形成することができるが、 ここでは その図示および説明は省略する。 Thereafter, the steps of FIG. 7, FIG. 8, FIG. 10, and FIGS. 12 to 17 can be repeated to form a further upper layer wiring. For example, as shown in FIG. 18, after forming a depression similar to the depression 21 on the wiring 35, a metal cap film 42 as a first metal cap film is formed on the wiring 35 as a first metal cap film. 22 and then formed on the insulating film 26 in which the wiring 35 is embedded by the same process and material as the process of forming the insulating films 23 to 26. (Paria insulating film) 43, insulating film (interlayer insulating film) 44, insulating film (etching stopper film) 45, and insulating film (interlayer insulating film) 46 are formed. Then, the insulating films 43 to 46 are dry-etched using a photolithography method or the like, so that the metal cap film 42 reaches the wirings 35 in the same manner as the vias 30 and the wiring grooves 31. A via (opening) 50 and a wiring groove (opening) 51 are formed to penetrate and expose the main conductor film 34 of the wiring 35, and the wiring 35 (main conductor film) exposed at the bottom of the via 50 is formed. 34) A metal cap film 52 is formed thereon as a second metal cap film using the same material and method as the metal cap film 32. Then, on the semiconductor substrate 1 (on the insulating film 46 including the bottom of the via 50 and the wiring groove 51 and the side wall), a conductive barrier film (paria conductor film) 53 is formed on the conductive barrier film 18, 3. The main conductor film 54 is formed by the same material and method as that of the main conductor film 53 so as to fill the via 50 and the wiring groove 51 on the conductive PAR film 53. Then, the unnecessary main conductor film 54 and conductive barrier film 53 on the insulating film 46 are removed by the CMP method to fill the via 50 and the wiring groove 51 and electrically connect to the wiring 35. The connected wiring (third layer wiring) 55 is formed. In the same manner, an upper layer wiring (fourth layer wiring) can be formed. Its illustration and description are omitted.
次に、 本実施の形態の効果について説明する。  Next, effects of the present embodiment will be described.
図 1 9は、 比較例の半導体装置の要部断面図であり、 配線 2 0， 3 5近傍領域 の部分拡大図である。図 1 9の構造は、本実施の形態の配線 2 0 , 3 5において、 金属キャップ膜 2 2 , 3 2， 4 2， 5 2の形成を省略したものにほぼ対応する。 一般に埋込銅配線は、 絶縁膜にビアや配線溝となるパターンを形成し、 銅 （C u ) の拡散防止膜である導電性パリア膜と主配線部分である銅の主導体膜をビア や配線溝に埋込み、 不要な部分を研磨 ( CMP ) で除去して配,镍を形成するダマ シン法を採用している。 このため、 その加工方法上、 図 1 9に示されるように、 銅の主導体膜 1 9の底面および側面は導電性パリア膜 1 8で被覆されるが、 主導 体膜 1 9の上面は銅の拡散防止性能の高い絶縁膜 2 3で覆われる構造となるのが 一般的である。  FIG. 19 is a cross-sectional view of a main part of the semiconductor device of the comparative example, and is a partially enlarged view of a region near the wirings 20 and 35. The structure of FIG. 19 substantially corresponds to the case where the formation of the metal cap films 22, 32, 42, 52 is omitted in the wirings 20, 35 of the present embodiment. In general, buried copper wiring is formed by forming vias and wiring grooves in the insulating film and forming a conductive barrier film that is a copper (Cu) diffusion prevention film and a copper main conductor film that is the main wiring part. The damascene method is adopted, which is embedded in the wiring groove, and unnecessary portions are removed by polishing (CMP) to form a distribution. Therefore, due to the processing method, as shown in FIG. 19, the bottom and side surfaces of the copper main conductor film 19 are covered with the conductive barrier film 18, but the upper surface of the main conductor film 19 is made of copper. Generally, the structure is covered with an insulating film 23 having high diffusion prevention performance.
銅 （C u ) 原子のマイグレーションは、 結晶内部の拡散よりも表面拡散が支配 的であるが、 図 1 9に示されるような埋込銅配線構造においては、 配線 2 0上部 の絶縁膜 2 3で覆われた面の接着性が他の面よりも低いため、 絶縁膜 2 3と銅配 線の主導体膜 1 9との界面が、 銅 （ C u ) 原子のマイグレーションパスとなり得 る。 配線 3 5についても同様である。  The migration of copper (Cu) atoms is dominated by surface diffusion rather than diffusion inside the crystal. However, in the buried copper wiring structure as shown in FIG. 19, the insulating film 23 over the wiring 20 Since the adhesiveness of the surface covered with is lower than that of the other surface, the interface between the insulating film 23 and the main conductor film 19 of the copper wiring can serve as a migration path for copper (Cu) atoms. The same applies to the wiring 35.
また、 ストレスマイグレーションによつて銅配線のビア部 （配,線 3 5のビア 3 0に埋め込まれた部分）の抵抗が上昇する現象（S I V： Stress-Induced Voiding) が生じる。 ストレスマイグレーションによる不良現象としては、 ビア 3 0内部の 銅 （C u ) が上部の配線部に吸い上げられてボイドが発生するモードと、 ビア 3 0と下層銅配線としての配線 2 0との界面にボイドが発生するモードがある。 前 者は、 導電性パリア膜としてのタンタル （T a ) の採用や、 ビア形状の改善、 あ るレヽは導電性パリァ膜ゃ銅のシー—ド膜のカバレージの改善などによつて対策する ことができる。  In addition, a phenomenon (SIV: Stress-Induced Voiding) occurs in which the resistance of the via portion of the copper wiring (the portion embedded in the via 30 of the wiring 35) increases due to the stress migration. The failure phenomena due to stress migration include the mode in which copper (Cu) inside via 30 is sucked up by the upper wiring and voids are generated, and the interface between via 30 and wiring 20 as the lower copper wiring. There is a mode in which voids occur. For the former, the use of tantalum (T a) as the conductive barrier film, improvement of the via shape, and, in some cases, the improvement of the coverage of the conductive barrier film and the copper seed film should be taken. Can be.
ビア底に生じるボイドの形態としては、 熱負荷温度 2 0 0 °C近傍で生じるケー ス (低温ストレスマイグレーション) が顕著であり、 不良率の下層配!！ （図 1 9 では配線 2 0 ) 幅依存性が大きく、 配線幅が大きい程ビア部の劣ィ匕が進行する。 この現象は、 銅配線内部に内在する空隙 （Vacancy) 力 絶縁膜 （パリア絶縁膜） と銅配線の応力差を駆動力として銅の結晶粒界を拡散し、 ビア底に集まってボイ ドを形成するためと考えられる。 ビア下部周辺が最も応力勾配が大きく、 配線幅 が大きい程、 散する空隙の量も多いため、 不良率が高くなる。 応力勾配が発生 する理由は、 ビアは銅配線上の絶縁膜 （パリア絶縁膜） によってビアの直径を圧 縮する方向の力を受けるが、 ビア底の銅配線 （銅の主導体膜） は、 この反作用に よってビアを膨張させようとするので、 ビア底部分と下層の配線部分との間に大 きな応力差が発生するためである。 空隙の拡散は、 相対的には銅 （C u ) が逆方 向に拡散していることを意味しており、 銅 （C u ) の拡散パス （拡散経路） を抑 制する （なくす） ことが、 ビア底のポイドの発生およびそれに起因した不良を防 止するために有効であると考えられる。 As a form of voids generated at the via bottom, a case (low-temperature stress migration) generated near a thermal load temperature of 200 ° C is remarkable, and the failure rate is lower! (In FIG. 19, the wiring 20) The width dependency is large, and the larger the wiring width, the worse the via portion becomes. This phenomenon is caused by the void force inside the copper wiring (Vacancy). It is thought that the difference in stress between the copper wiring and the copper wiring is used as a driving force to diffuse copper grain boundaries and collect at the bottom of the via to form a void. The stress gradient is greatest around the bottom of the via and the larger the interconnect width, the greater the amount of scattered voids, resulting in a higher failure rate. The reason for the stress gradient is that the via is subjected to a force in the direction of reducing the diameter of the via by the insulating film (paria insulating film) on the copper wiring, but the copper wiring (copper main conductor film) at the bottom of the via is This is because the reaction tends to expand the via, so that a large stress difference is generated between the bottom portion of the via and the underlying wiring portion. The diffusion of the void means that copper (Cu) is relatively diffused in the opposite direction, and suppresses (eliminates) the copper (Cu) diffusion path. Is considered to be effective in preventing the occurrence of voids in the via bottom and the resulting defects.
このように、 エレクトロマイグレーションゃ低温ストレスマイグレーションの 抑制に対して、 銅 （C u ) 原子の拡散現象を抑制することが有効である。 これを 実現する手段として、 銅配線の上面に選択的に金属キャップ膜を成長させて、 銅 配線の上面を金属キャップ膜で被覆することが考えられる。 図 2 0は、 銅配線の 上面を金属キャップで被覆した半導体装置の要部断面図であり、 配線 2 0， 3 5 近傍領域の部分拡大図である。 図 1 9の構造に、 更に金属キャップ膜 2 2 , 4 2 を形成したものに対応する。  Thus, it is effective to suppress the diffusion phenomenon of copper (Cu) atoms in order to suppress the electromigration ゃ low-temperature stress migration. To realize this, it is conceivable to selectively grow a metal cap film on the upper surface of the copper wiring and cover the upper surface of the copper wiring with the metal cap film. FIG. 20 is a cross-sectional view of a main part of a semiconductor device in which the upper surface of a copper wiring is covered with a metal cap, and is a partially enlarged view of a region near the wirings 20 and 35. This corresponds to a structure in which metal cap films 22 and 42 are further formed on the structure of FIG.
しかしながら、 本発明者の実験によれば、 金属キャップ膜 2 2の膜厚を厚くす るほど、 金属キャップ膜 2 2の選択性が低下または劣化することが分かった。 す なわち、 金属キャップ膜 2 2の選択成長の際の選択性は完全ではなく、 部分的に 破れてしまい、 配線 2 0を埋め込んだ絶縁膜 1 5の表面にも金属キャップ膜 2 2 を構成する金属材料が成長してしまう可能性がある。 金属キャップ膜 4 2につい ても同様である。 選択性が破れる原因としては、 絶縁膜表面の金属汚染により、 そこ （金属汚染物） を基点として金属膜 （金属キャップ膜を構成する金属材料） が成長することによるものと考えられる。 金属キャップ膜を構成する金属材料の 絶縁膜上への成長 （選択性の破れ） は、 隣り合う同層配線間の絶縁破壊耐性を低 下させ、 半導体装置の信頼性を低下させる可能性がある。  However, according to experiments performed by the present inventors, it was found that as the thickness of the metal cap film 22 was increased, the selectivity of the metal cap film 22 was reduced or deteriorated. In other words, the selectivity of the selective growth of the metal cap film 22 is not perfect, but is partially broken, and the metal cap film 22 is also formed on the surface of the insulating film 15 in which the wiring 20 is embedded. Metal material may grow. The same applies to the metal cap film 42. It is considered that the selectivity is broken because metal contamination on the surface of the insulating film causes the growth of the metal film (the metal material constituting the metal cap film) based on the metal contamination. The growth of the metal material that forms the metal cap film on the insulating film (breaking of selectivity) may reduce the dielectric breakdown resistance between adjacent wirings on the same layer and may reduce the reliability of semiconductor devices. .
半導体装置は微細化する傾向にあり、 配線間のスペースは小さくなってきてい る。 金属キャップ膜の選択成長の際の上記のような選択性の破れは、 隣り合う配 線間の絶縁破壊耐性を低下させる可能性があるので、 半導体装置の微細化に対し て不利である。このため、金属キャップ膜 2 2はあまり厚くすることができない。 また、 配線抵抗を増加させないためにも、 金属キャップ膜はあまり厚くすること ができない。 本発明者の検討によれば、 上記のように金属キャップ膜 2 2の膜厚 は 2 0 n m以下であることが好ましい。 金属キャップ膜 4 2についても同様であ る。 しかしながら、 金属キャップ膜 2 2の膜厚を薄くした場合、 次のような問題 が生じる。 すなわち、 配線 2 0上にビア 3 0を形成 （開孔） する際に、 金属キヤ ップ膜 2 2上でェツチングストップできずに、 配線 2 0上に形成した金属キヤッ プ膜 2 2までエッチング除去されてしまう点である。 Semiconductor devices tend to be miniaturized, and the space between wirings is becoming smaller. The above-mentioned loss of selectivity during the selective growth of metal cap film This is disadvantageous for miniaturization of a semiconductor device, since the dielectric breakdown resistance between wires may be reduced. For this reason, the metal cap film 22 cannot be made too thick. Also, the metal cap film cannot be made too thick in order not to increase the wiring resistance. According to the study of the present inventors, as described above, the thickness of the metal cap film 22 is preferably 20 nm or less. The same applies to the metal cap film 42. However, when the thickness of the metal cap film 22 is reduced, the following problem occurs. That is, when the via 30 is formed (opened) on the wiring 20, the etching stop cannot be performed on the metal cap film 22, and the metal cap film 22 formed on the wiring 20 cannot be stopped. The point is that it is removed by etching.
もし、 ビア 3 0底部で金属キャップ膜 2 2が残存するようにビア 3 0形成のド ライエッチングを行うと、 エッチング不足によりビア 3 0底部で金属キャップ膜 2 2上の絶縁膜 2 3の一部が残存してビア 3 0が配線 2 0に到達しない可能性が 生じる。 これは、 上層配線である配線 3 5と下層配線である配線 2 0との間の電 気的接続の信頼性を低下させる。 これを防 、でビア 3 0底部で配線 2 0を確実に 露出しょうとすると、 上記のように配線 2 0上にビア 3 0を形成 （開孔） する際 に、 金属キャップ膜 2 2上でエッチングストップできずに、 配線 2 0上に形成し た金属キャップ膜 2 2まで除去され、 図 2 0に示されるように、 金属キャップ膜 2 2の下の銅の主導体膜 1 9が露出し、 ビア 3 0底部では主導体膜 1 9上に金属 キャップ膜が無い状態になってしまう。 銅配線のボリューム （長さ、 Ψ畐、 深さ） が大きい場合には、 内在する空隙の総量も大きくなつてしまうため、 金属キヤッ プ膜の無い場所 （ビア 3 0底部） 力 唯一のウィークポイント、 すなわち、 導電 性パリア膜 1 8および金属キャップ膜 2 2で被覆されていない唯一の部分であり 銅の拡散パス （拡散経路） となる部分になってしまう。 また、 ビア 3 0底部で露 出する銅の主導体膜 1 9上に上層配線である配線 3 5用の導電性パリア膜 3 3を 形成したとしても、 主導体膜 1 9と導電性パリア膜 3 3との接着性 （密着性） は 比較的低いため、 上記のように主導体膜 1 9の金属キヤップ膜 2 2で被覆されて いないビア 3 0底部の部分が銅の拡散パス （拡散経路） となってしまう。  If dry etching for forming the via 30 is performed so that the metal cap film 22 remains at the bottom of the via 30, if the insulating film 23 on the metal cap film 22 is formed at the bottom of the via 30 due to insufficient etching. There is a possibility that the via 30 may not reach the wiring 20 due to the remaining part. This lowers the reliability of the electrical connection between the wiring 35 as the upper wiring and the wiring 20 as the lower wiring. In order to prevent this, and to surely expose the wiring 20 at the bottom of the via 30, when forming the via 30 on the wiring 20 (opening) as described above, Without being able to stop etching, the metal cap film 22 formed on the wiring 20 was removed, and as shown in FIG. 20, the copper main conductor film 19 under the metal cap film 22 was exposed. At the bottom of the via 30, there is no metal cap film on the main conductor film 19. If the volume (length, depth, depth) of the copper wiring is large, the total amount of internal voids will also increase, so a place without a metal cap film (the bottom of the via 30) is the only weak point. That is, it is the only part that is not covered with the conductive barrier film 18 and the metal cap film 22 and becomes a part that becomes a copper diffusion path (diffusion path). Further, even if a conductive barrier film 33 for the wiring 35 as an upper layer wiring is formed on the copper main conductive film 19 exposed at the bottom of the via 30, the main conductive film 19 and the conductive Since the adhesion to 33 is relatively low, the bottom of the via 30 that is not covered with the metal cap film 22 of the main conductor film 19 as described above has a copper diffusion path (diffusion path). ).
図 2 1は、 本実施の形態の半導体装置の要部断面図であり、 配線 2 0 , 3 5近 傍領域の部分拡大図である。 本実施の形態では、 金属キャップ膜 2 2， 3 2 , 4 2 , 5 2を形成している (なお、 図 2 1では金属キャップ膜 5 2は図示を省略し ている）。 FIG. 21 is a cross-sectional view of a main part of the semiconductor device of the present embodiment, and is a partially enlarged view of a region near wirings 20 and 35. In the present embodiment, the metal cap films 22, 32, 4 2 and 52 (the metal cap film 52 is not shown in FIG. 21).
本実施の形態では、 上記のように、 配線 2 0上にビア 3 0を形成 （開孔） する 際にビア 3 0底部で金属キャップ膜 2 2を除去するが、 ビア 3 0底部で露出した 配線 2 0 (主導体膜 1 9 ) 上に金属キャップ膜 3 2を付け直すことにより、 接着 性のよい材料 （導電性パリア膜 1 8および金属キャップ膜 2 2， 3 2 ) で配線 2 0の表面 （上面、 底面および側面） を完全に被覆する。 このため、 配線 2 0の鲖 の主導体膜 1 9が露出した部分 （ウィークポイント、 銅の拡散経路） を無くし、 空隙がビア 3 0底部周辺に集中することを防止することができる。 配線 3 5につ いても同様である。 このため、 電気的、 熱的または機械的ストレスによる不良 （ 例えば配線抵抗が増大する現象など） を抑制または防止することができる。 従つ て、 形成された配線のエレクトロマイグレーションやストレスマイグレーション 特性を向上し、 埋込銅配線の信頼性および埋込銅配線を有する半導体装置の信頼 性を向上できる。  In the present embodiment, as described above, when forming (opening) the via 30 on the wiring 20, the metal cap film 22 is removed at the bottom of the via 30, but is exposed at the bottom of the via 30. By re-attaching the metal cap film 32 on the wiring 20 (main conductor film 19), the wiring 20 can be formed with a material having good adhesion (conductive barrier film 18 and metal cap films 22 and 32). Completely cover the surface (top, bottom and side). Therefore, a portion (weak point, copper diffusion path) where the main conductor film 19 is exposed on the side of the wiring 20 is eliminated, and it is possible to prevent the void from being concentrated around the bottom of the via 30. The same applies to wiring 35. Therefore, defects due to electrical, thermal, or mechanical stress (for example, a phenomenon in which wiring resistance increases) can be suppressed or prevented. Accordingly, the electromigration and stress migration characteristics of the formed wiring can be improved, and the reliability of the buried copper wiring and the semiconductor device having the buried copper wiring can be improved.
また、 配線 2 0上に金属キヤップ膜 2 2を比較的薄く形成するので、 金属キヤ ップ膜 2 2の選択成長性を向上して隣り合う配線間の絶縁破壊耐性を向上するこ とができ、 またビア 3 0底部で金属キャップ膜 2 2を除去するように配線 2 0上 にビア 3 0を形成 (開孔） するので、 ビア 3 0の底部で配線 2 0を確実に露出さ せることができ、 上層配線と下層配線との間の電気的接続の信頼性を向上させる ことができる。  Further, since the metal cap film 22 is formed relatively thin on the wiring 20, the selective growth of the metal cap film 22 can be improved, and the dielectric breakdown resistance between adjacent wirings can be improved. In addition, since the via 30 is formed (opened) on the wiring 20 so as to remove the metal cap film 22 at the bottom of the via 30, the wiring 20 is surely exposed at the bottom of the via 30. Thus, the reliability of the electrical connection between the upper wiring and the lower wiring can be improved.
また、 多層配線構造を構成するいずれの埋込銅配線についても、 本実施の形態 を適用することができるが、 多層配線構造のうち、 任意の配線層、 例えばストレ スマイグレーションによる劣ィ匕が生じやすい構造の配線層についてだけ、 本実施 の形態を適用することもできる。 ストレスマイグレーションに起因した不良が生 じゃすいのは、 比較的幅広の配線部に比較的小さな径のビア部が接続された構造 の配線層である。 そのような配線構造においては、 高温放置による抵抗上昇のよ うなストレスマイグレーションによる劣化が生じやすい。 そのようなストレスマ ィグレーションによる劣ィ匕が生じやすい構造の配線層は、 多層配線構造のうち比 較的下層側の配線層であるので、 例えば下層側の銅配線 （例えば配線 2 0、 3 5 ) で本実施の形態を適用し、 銅配線 （配線 2 0、 3 5 ) 上に第 1の金属： 膜 （金属キャップ膜 2 2， 4 2 ) を形成し、 その銅配線に接続するビア （ビア 3 0 , 5 0 ) 形成時にビア底部で第 1の金属キャップ膜を除去し、 ビア底部で露出 した銅配線上に第 2の金属キャップ膜 （金属キャップ膜 3 2， 5 2 ) を形成する ことができる。 In addition, the present embodiment can be applied to any embedded copper wiring constituting the multilayer wiring structure. However, in the multilayer wiring structure, any wiring layer, for example, inferiority due to stress migration occurs. The present embodiment can be applied only to a wiring layer having an easy structure. Defects due to stress migration are likely to occur in wiring layers with a structure in which relatively wide wiring parts are connected to via parts having relatively small diameters. In such a wiring structure, deterioration due to stress migration, such as an increase in resistance due to high temperature storage, is likely to occur. Since the wiring layer having a structure in which inferiority due to such stress migration is likely to occur is a relatively lower wiring layer in the multilayer wiring structure, for example, a lower copper wiring (for example, wiring 20 or 3 5 ), A first metal film (metal cap film 22, 42) is formed on the copper wiring (wiring 20, 35), and a via () connected to the copper wiring is formed. When forming the vias 30 and 50), the first metal cap film is removed at the bottom of the via and a second metal cap film (metal cap films 32 and 52) is formed on the copper wiring exposed at the bottom of the via be able to.
(実施の形態 2 )  (Embodiment 2)
図 2 2および図 2 3は、 本発明の他の実施の形態である半導体装置の製造工程 中の要部断面図である。 図 1 2までの製造工程は上記実施の形態 1とほぼ同様で あるので、ここではその説明は省略し、図 1 2に続く製造工程について説明する。 なお、 図 2 2および図 2 3においても、 図 1の絶縁膜 1 1より下の構造に対応す る部分は図示を省略している。  FIGS. 22 and 23 are cross-sectional views of essential parts during a manufacturing process of a semiconductor device according to another embodiment of the present invention. Since the manufacturing steps up to FIG. 12 are almost the same as those in the first embodiment, the description is omitted here, and the manufacturing steps following FIG. 12 will be described. In FIGS. 22 and 23, the portions corresponding to the structure below the insulating film 11 in FIG. 1 are not shown.
上記実施の形態 1と同様にして図 1 2の構造が得られた後、 図 2 2に示される ように、 フォトリソグラフィ法などを用いて絶縁膜 2 3〜2 6をドライエツチン グすることなどによって、 配線開口部すなわち、 配線 2 0に達するスルーホール またはビア （開口部） 3 0および配線溝 （開口部） 3 1を形成する。  After the structure of FIG. 12 is obtained in the same manner as in the first embodiment, as shown in FIG. 22, the insulating films 23 to 26 are dry-etched by using a photolithography method or the like. Then, a wiring opening, that is, a through hole or via (opening) 30 reaching the wiring 20 and a wiring groove (opening) 31 are formed.
例えばフォトレジストパターン形成工程での露光のフォトマスクの位置合わせ のずれなどのために、 図 2 2に示されるように、 ビア 3 0が配線 2 0のパターン 力 らずれる、 いわゆる目外れが発生する場合がある。 半導体装置の設計では、 マ 一ジンが少ないぎりぎりの設計を行ったり、 あるいは、 半導体装置の配線パター ンの設計上目外れを避けられない設計、 目外れを含む設計、 または目外れを許容 した設計とする場合もある。 このような目外れを防止するためには、 配線パター ンの幅を広くする必要があるが、 これは半導体装置の大型化を招く。 また、 ビア の径を小さくして目外れを防止することも考えられるが、 これはビアのァスぺク ト比の更なる増大を招き、 ビアを埋める導電性パリア膜および銅の主導体膜の形 成を困難にしてしまう。 このため、 高密度な配線パターンを有する半導体装置に おいては、 このような目外れが生じ得る。 従って、 半導体装置には目外れが発生 したビアと目外れが生じていないビアとが混在することになる。  For example, as shown in FIG. 22, the via 30 shifts in the pattern of the wiring 20, that is, a so-called gap occurs due to misalignment of the exposure photomask in the photoresist pattern forming process. There are cases. In the design of semiconductor devices, marginal design is used, or the design of the wiring pattern of the semiconductor device cannot be avoided. In some cases, To prevent such misalignment, it is necessary to increase the width of the wiring pattern, but this leads to an increase in the size of the semiconductor device. It is also conceivable to reduce the diameter of the via to prevent unsightlyness. However, this causes a further increase in the aspect ratio of the via, and a conductive barrier film and a copper main conductive film that fill the via. This makes it difficult to form For this reason, such a gap may occur in a semiconductor device having a high-density wiring pattern. Therefore, in the semiconductor device, the vias in which the opening has occurred and the vias in which the opening has not occurred are mixed.
配線 2 0を露出するために形成したビア 3 0のうち、 図 2 2に示されるビア 3 0 aで目外れが発生している。 目外れが発生したビア 3 0 a内では、 主導体膜 1 9の上面と導電性バリア膜 1 8の端部とが露出する。 すなわち、 目外れが発生し たビア 3 0 aの底部では主導体膜 1 9だけでなく導電性パリア膜 1 8の一部も露 出することになる。 Of the vias 30 formed to expose the wiring 20, the vias 30a shown in FIG. In the via 30 a where the opening occurred, the main conductor film 1 9 and the end of the conductive barrier film 18 are exposed. That is, not only the main conductor film 19 but also a part of the conductive barrier film 18 is exposed at the bottom of the via 30a where the opening has occurred.
次に、 図 2 3に示されるように、 ビア 3 0の底部で露出する配線 2 0上に金属 キャップ膜 （導電性キャップ膜） 3 2を選択成長または優先成長させる。 金属キ ヤップ膜 3 2は、 例えばタングステン （W) 膜またはタングステン合金膜 （ある いはタングステンを主成分とする導体膜）などからなる。金属キヤップ膜 2 2は、 選択タングステン C V D法などによって形成することができる。 例えば、 六フッ 化タングステン （WF 6) および水素 （H 2) ガスを用いた C V D法により、 ビア 3 0底部で露出した配線 2 0の上面上にタングステン膜を選択的に堆積すること により、 金属キャップ膜 3 2を形成することができる。 また、 無電解めつき法に よって、 C o WP、 C o WBまたは C o Wなどからなる金属キャップ膜 3 2をビ 了 3 0底部で露出した配線 2 0の上面上に選択的に形成することもできる。 図 2 4は、 ビア 3 0に目外れが生じ得る場合の導電性パリア膜 1 8の材料と金 属キャップ膜 3 2の形成方法の関係を示す説明図 （表） である。 Next, as shown in FIG. 23, a metal cap film (conductive cap film) 32 is selectively grown or preferentially grown on the wiring 20 exposed at the bottom of the via 30. The metal cap film 32 is made of, for example, a tungsten (W) film or a tungsten alloy film (or a conductor film containing tungsten as a main component). The metal cap film 22 can be formed by a selective tungsten CVD method or the like. For example, by selectively depositing a tungsten film on the upper surface of the wiring 20 exposed at the bottom of the via 30 by a CVD method using tungsten hexafluoride (WF 6 ) and hydrogen (H 2 ) gas, The cap film 32 can be formed. In addition, a metal cap film 32 made of Co WP, Co WB, or Co W is selectively formed on the upper surface of the wiring 20 exposed at the bottom of the via 30 by an electroless plating method. You can also. FIG. 24 is an explanatory diagram (table) showing the relationship between the material of the conductive barrier film 18 and the method of forming the metal cap film 32 in the case where the via 30 may be missed.
上記のように、 本実施の形態では、 ビア 3 0のうち、 ビア 3◦ aでは目外れが 生じているので、 目外れが発生したビア 3 0 aの底部では主導体膜 1 9だけでな く導電性パリア膜 1 8の一部も露出している。 このため、 もし導電性パリア膜 1 8が高融点金属膜 （例えばチタン （T i ) 膜、 タンタル (T a ) 膜、 タンダステ ン （W) 膜などの純金属膜） を含んでいた場合、 金属キャップ膜 3 2の形成法と して選択タングステン C V D法を用いると、 ビア 3 0 aの底部で露出する導電性 パリア膜 1 8の端部上でタングステン （金属キャップ膜 3 2 ) が異常成長してし まう。 これは、 高融点金属 （純金属） による還元作用によって六フッ化タンダス テン （WF 6) ガスがそこで優先的に還元され、 タングステンが優先的に成長す る作用によるものと考えられる。 こめタングステンの異常成長は、 導電性パリア 膜 3 3や導電性パリア膜 3 3上に形成する銅のシード膜の力パレージ （ステップ 力パレージ） を低下させるので、 ビア 3 0 a内部でボイドを発生させる可能性が ある。 このため、 ビア 3 0に目外れが発生し得るようなレイアウトルールにおい ては、 金属キャップ膜 3 2の形成法として選択タングステン C V D法を用いる場 合は、 導電性パリア膜 1 8が高融点金属膜 （純金属膜） を含んでいなければより 好ましい。 この場合、 導電性パリア膜 1 8として、 例えば窒化チタン （T i N)、 窒ィ匕タンタル （T a N) または窒化タングステン （WN) などのような高融点金 属窒化物、 またはそのような高融点金属窒化物にシリコン （S i ) を添加した材 料を用いることができる。 As described above, in the present embodiment, among the vias 30, out-of-via occurs in the via 3 ◦a, so that only the main conductor film 19 is present at the bottom of the via 30 a in which the out-of-via occurs. In addition, part of the conductive barrier film 18 is also exposed. Therefore, if the conductive barrier film 18 includes a high melting point metal film (for example, a pure metal film such as a titanium (T i) film, a tantalum (T a) film, and a tundast (W) film), When the selective tungsten CVD method is used to form the cap film 32, tungsten (metal cap film 32) abnormally grows on the end of the conductive barrier film 18 exposed at the bottom of the via 30a. I will. This is considered to be due to the effect that the tungsten hexafluoride (WF 6 ) gas is preferentially reduced there by the reducing action of the refractory metal (pure metal) and the tungsten grows preferentially. Anomalous growth of rice tungsten lowers the force paradigm of the conductive barrier film 33 and the copper seed film formed on the conductive barrier film 33, so voids are generated inside the via 30a. There is a possibility that it will be. For this reason, in a layout rule that may cause the via 30 to be out of place, the selective tungsten CVD method is used as the method for forming the metal cap film 32. In this case, it is more preferable that the conductive barrier film 18 does not include a refractory metal film (pure metal film). In this case, as the conductive barrier film 18, for example, a high melting point metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), or the like. A material obtained by adding silicon (Si) to a high melting point metal nitride can be used.
導電性パリア膜 1 8が高融点金属膜を含んでいる場合、 すなわち導電性パリァ 膜 1 8として高融点金属の単体膜または高融点金属膜と高融点金属合金膜 （例え ば高融点金属窒化物膜） との積層膜を用いた場合は、 ビア 3 0形成のレイァゥト ルールの目外れ規制を行ってビア 3 0に目外れが生じないようにするか、 あるい はビア 3 0の目外れを許容して金属キャップ膜 3 2を無電解めつき法により形成 する。 目外れが発生したビア 3 0 aにおいて導電性パリア膜 1 8が露出していた としても、 金属キャップ膜 3 2を無電解めつき法で形成することで、 導電性パリ ァ膜 1 8が高融点金属膜 （純金属膜） を含んでいるかどうかにかかわらず、 タン ダステン （金属キャップ膜 3 2 ) の異常成長を防止することができる。  When the conductive barrier film 18 includes a high melting point metal film, that is, a single film of a high melting point metal or a high melting point metal film and a high melting point metal alloy film (for example, a high melting point metal nitride) In the case of using a laminated film with a via), the layout rule for the formation of via 30 should be controlled so as not to cause the via 30 to be out of alignment, or the via 30 should be prevented from being out of alignment. The metal cap film 32 is formed by an electroless plating method, while allowing. Even if the conductive barrier film 18 is exposed in the via 30 a where the opening has occurred, the conductive barrier film 18 can be formed in a high quality by forming the metal cap film 32 by the electroless plating method. Irrespective of whether a melting point metal film (pure metal film) is included or not, abnormal growth of tungsten (metal cap film 32) can be prevented.
従って、 ビア 3 0に目外れが生じ得るレイアウトルールにおいては、 図 2 4に 示されるように、 導電性パリア膜 1 8が高融点金属膜 （純金属膜） を含む場合は 金属キャップ膜 3 2を無電解めつき法で形成し、 導電性パリア膜 1 8が高融点金 属膜 （純金属膜） を含まない場合は金属キャップ膜 3 2を選択タングステン C V D法または無電解めつき法で形成する。 また、 多層配線構造を有する半導体装置 においては、 比較的下層の配線層では、 配線間隔が比較的狭く目外れが生じやす いので、図 2 4に示されるような金属キャップ膜 3 2の成膜法を適用すればよい。 これにより、 埋込銅配線を有する半導体装置の信頼性をより向上することができ る。  Therefore, according to the layout rule in which the via 30 can be missed, as shown in FIG. 24, when the conductive barrier film 18 includes a refractory metal film (pure metal film), the metal cap film 32 Is formed by an electroless plating method. If the conductive barrier film 18 does not include a high melting point metal film (pure metal film), a metal cap film 32 is selected. A tungsten CVD method or an electroless plating method is used. I do. Further, in a semiconductor device having a multilayer wiring structure, since a relatively lower wiring layer has a relatively narrow wiring interval and is likely to be out of shape, a metal cap film 32 as shown in FIG. 24 is formed. The law may be applied. Thereby, the reliability of the semiconductor device having the embedded copper wiring can be further improved.
図 2 5は、 ビア 3 0に目外れが生じない場合の導電性パリア膜 1 8の材料と金 属キャップ膜 3 2の形成方法の関係を示す説明図 （表） である。 ビア 3 0に目外 れが生じない場合は、 上記実施の形態 1における図 1 3のように、 ビア 3 0の底 部では主導体膜 1 9が露出し、 導電性パリア膜 1 8は露出しないので、 金属キヤ ップ膜 3 2を選択タングステン C V D法または無電解めつき法のいずれで形成し  FIG. 25 is an explanatory view (table) showing the relationship between the material of the conductive barrier film 18 and the method of forming the metal cap film 32 when the vias 30 do not miss. If the via 30 does not miss, the main conductor film 19 is exposed at the bottom of the via 30 and the conductive barrier film 18 is exposed as shown in FIG. 13 in the first embodiment. Therefore, the metal cap film 32 is selectively formed by either the tungsten CVD method or the electroless plating method.
(金属キャップ膜 3 2 ) の異常成長は生じない。 このた め、 ビア 3 0に目外れが生じないレイアウトルールにおいては、 図 2 5に示され るように、 導電性パリア膜 1 8が高融点金属膜 （純金属膜） を含む場合および含 まない場合のいずれにおいても、 金属キャップ膜 3 2を選択タングステン C V D 法または無電解めつき法で形成することができる。 また、 多層配線構造を有する 半導体装置においては、 比較的上層の配線層では、 配線間隔が比較的広く目外れ が生じにくいので、 図 2 5に示されるような金属キャップ膜 3 2の成膜法を適用 すればよい。 これにより、 埋込鲖配線を有する半導体装置の信頼性をより向上す ることができる。 No abnormal growth of the (metal cap film 32) occurs. others Therefore, in the layout rule in which the via 30 does not become unclear, as shown in FIG. 25, when the conductive barrier film 18 includes or does not include the high melting point metal film (pure metal film). In either case, the metal cap film 32 can be formed by a selective tungsten CVD method or an electroless plating method. Further, in a semiconductor device having a multilayer wiring structure, a relatively high wiring layer has a relatively wide wiring interval and is hard to be out of shape, so that a metal cap film 32 as shown in FIG. 25 is formed. What is necessary is to apply. As a result, the reliability of the semiconductor device having the embedded wiring can be further improved.
図 2 6は、 図 2 3に続く半導体装置の製造工程中における要部断面図を示して いる。 なお、 理解を簡単にするために、 図 2 6においても、 図 1の絶縁膜 1 1よ り下の構造に対応する部分は図示を省略している。  FIG. 26 is a cross-sectional view of a main part of another manufacturing step of the semiconductor device, following the step shown in FIG. In FIG. 26, portions corresponding to the structure below the insulating film 11 in FIG. 1 are not shown for easy understanding.
金属キャップ膜 3 2の形成工程以降の工程については、 上記実施の形態 1とほ ぼ同様である。 すなわち、 図 2 6に示されるように、 半導体基板 1の主面上の全 面 （すなわちビア 3 0 (ビア 3 0 a ) の底部および側壁上と配線溝 3 1の底部お よび側壁上とを含む絶縁膜 2 6上） に導電性パリア膜 3 3および主導体膜 3 4を 形成し、 主導体膜 3 4および導電性パリア膜 3 3を CMP法によって絶縁膜 2 6 の上面が露出するまで研磨して、 配線 3 5を形成する。  The steps after the step of forming the metal cap film 32 are almost the same as those in the first embodiment. That is, as shown in FIG. 26, the entire surface on the main surface of the semiconductor substrate 1 (that is, the bottom and side walls of the via 30 (via 30a) and the bottom and side walls of the wiring groove 31) are A conductive barrier film 33 and a main conductive film 34 are formed on the insulating film 26 including the insulating film 26, and the main conductive film 34 and the conductive barrier film 33 are formed by CMP until the upper surface of the insulating film 26 is exposed. Polishing is performed to form the wiring 35.
本実施の形態では、 上記のように、 ビア 3 0に目外れが生じてビア 3 0底部で 配線 2 0の導電性パリア膜 1 8が露出するかどうかに応じて、 ビア 3 0の底部で 付け直す金属キャップ膜 3 2の成膜方法を選択する。 これにより、 金属キャップ 膜 3 2をより的確に形成することができ、 坦込銅配線を有する半導体装置の信頼 性をより向上することができる。  In this embodiment, as described above, depending on whether or not the via 30 is missed and the conductive barrier film 18 of the wiring 20 is exposed at the bottom of the via 30, Select the method for forming the metal cap film 32 to be reattached. As a result, the metal cap film 32 can be formed more accurately, and the reliability of the semiconductor device having the embedded copper wiring can be further improved.
(実施の形態 3 )  (Embodiment 3)
図 2 7〜図 3 0は、 本発明の他の実施の形態である半導体装置の製造工程中の 要部断面図である。 図 1 7までの製造工程は上記実施の形態 1とほぼ同様である ので、 ここではその説明は省略し、 図 1 7に続く製造工程について説明する。 な お、 図 2 7〜図 3 0においても、 図 1の絶縁膜 1 1より下の構造に対応する部分 は図示を省略している。  27 to 30 are main-portion cross-sectional views of a semiconductor device according to another embodiment of the present invention during the manufacturing steps thereof. Since the manufacturing steps up to FIG. 17 are substantially the same as those in the first embodiment, the description thereof is omitted here, and the manufacturing steps following FIG. 17 will be described. In FIGS. 27 to 30, portions corresponding to the structure below the insulating film 11 in FIG. 1 are not shown.
上記実施の形態 1と同様にして図 1 7の構造が得られた後、 図 2 7に示される ように、 配線 3 5に対して窪み 2 1と同様の窪みを形成した後、 配線 3 5上に金 属キャップ膜 4 2を金属キャップ膜 2 2と同様の材料および手法により形成し、 その後、 配線 3 5が埋め込まれた絶縁膜 2 6上に、 上記絶縁膜 2 3〜2 6を形成 した工程と同様の工程および材料によって、 絶縁膜 （パリア絶縁膜） 4 3、 絶縁 膜 （層間絶縁膜） 4 4、 絶縁膜 （エッチングストッパ膜） 4 5および絶縁膜 （層 間絶縁膜） 4 6を形成する。 それから、 図 2 8に示されるように、 配線開口部と して、 ビア 3 0および配線溝 3 1と同様にして、 配線 3 5に達して配線 3 5の主 導体膜 3 4を露出するビア （開口部） 5 0と配線溝 （開口部） 5 1とを形成する 。 その後、 図 2 9に示されるように、 本実施の形態では、 ビア 5 0から露出する 配線 3 5 (主導体膜 3 4 ) 上に金属キャップ膜を形成せずに （すなわち上記実施 の形態 1における金属キャップ膜 5 2を省略し）、半導体基板 1上（ビア 5 0およ び配線溝 5 1の底部および側壁を含む絶縁膜 4 6上） に導電性パリア膜 5 3を導 電性パリア膜 1 8 , 3 3と同様の材料および手法により形成し、 導電性パリァ膜 5 3上にビア 5 0および配線溝 5 1を埋めるように主導体膜 5 4を主導体膜 1 9 ， 3 4と同様の材料および手法により形成する。 そして、 図 3 0に示されるよう に、 CMP法により絶縁膜 4 6上の不要な主導体膜 5 4および導電性パリア膜 5 3を除去してビア 5 0および配線溝 5 1を埋めかつ配線 3 5と電気的に接続され た配線 （第 3層配線） 5 5を形成する。 After the structure of FIG. 17 is obtained in the same manner as in the first embodiment, the structure is shown in FIG. 27. As described above, after forming a depression similar to the depression 21 in the wiring 35, a metal cap film 42 is formed on the wiring 35 by the same material and method as the metal cap film 22. The insulating film (paria insulating film) 43 and the insulating film (interlayer insulating film) are formed on the insulating film 26 in which the wirings 35 are embedded by the same process and material as the process of forming the insulating films 23 to 26 above. 4) An insulating film (etching stopper film) 45 and an insulating film (interlayer insulating film) 46 are formed. Then, as shown in FIG. 28, the vias reaching the wirings 35 and exposing the main conductor film 34 of the wirings 35 are formed in the same manner as the vias 30 and the wiring grooves 31 as the wiring openings. (Opening) 50 and wiring groove (opening) 51 are formed. Thereafter, as shown in FIG. 29, in the present embodiment, the metal cap film is not formed on the wiring 35 (main conductor film 34) exposed from the via 50 (that is, in the first embodiment described above). And a conductive barrier film 53 on the semiconductor substrate 1 (on the insulating film 46 including the bottoms and side walls of the vias 50 and the wiring grooves 51). The main conductor film 54 is formed by the same material and method as those of the films 18 and 33, and the main conductor film 54 is filled on the conductive barrier film 53 so as to fill the via 50 and the wiring groove 51. It is formed by the same material and method as described above. Then, as shown in FIG. 30, the unnecessary main conductor film 54 and the conductive barrier film 53 on the insulating film 46 are removed by the CMP method to fill the via 50 and the wiring groove 51 and to perform wiring. Wiring (third layer wiring) 55 electrically connected to 35 is formed.
下層配線 （ここでは配線 3 5 ) のボリュームが小さい場合には、 本実施の形態 のように下層配線に接続 （到達） するビア （ここではビア 5 0 ) の底部の金属キ ヤップ膜 （ここでは金属キャップ膜 5 2 ) を省略することもできる。 下層配線の ボリュームが小さい場合というのは、 配線の幅、 深さが概ね主導体膜を構成する 銅 （C u ) の結晶粒径以下である場合を言う。 銅 （C u) の結晶粒径は、 例えば 1 . 5 μ πι程度である。 多層配線構造を有する半導体装置において、 下層配線の ボリュームが小さい場合は、 ストレスマイグレーションに起因した不良が生じに くいので、 本実施の形態のように、 その下層配線に接続 （到達） するビア （ここ ではビア 5 0 ) の底部の金属キャップ膜 （ここでは金属キャップ膜 5 2 ) を省略 することも可能である。 これにより、 製造工程数を低減して半導体装置の製造ェ 程を簡略化でき、 また配線のビア部の抵抗増加を防止することができる。 また、 ビア 5 0の底部での金属キヤップ膜の形成を省略しているので、 導電性 パリア膜 5 3形成前の前処理として、 アルゴン （A r ) イオンによる物理的スパ ッタエッチングや、 あるいは還元性ガスを含む雰囲気 （例えば水素雰囲気） 中に おける反応性プラズマ処理を用いることができる。 When the volume of the lower wiring (the wiring 35 in this case) is small, as in the present embodiment, the metal cap film at the bottom of the via (the via 50 in this case) connected to (attains) the lower wiring as in the present embodiment. The metal cap film 52) may be omitted. When the volume of the lower wiring is small, it means that the width and depth of the wiring are approximately equal to or smaller than the crystal grain size of copper (Cu) constituting the main conductor film. The crystal grain size of copper (Cu) is, for example, about 1.5 μπι. In a semiconductor device having a multilayer wiring structure, when the volume of the lower wiring is small, a failure due to stress migration is unlikely to occur. Therefore, as in the present embodiment, vias connected to (arriving at) the lower wiring (here). In this case, the metal cap film (here, the metal cap film 52) at the bottom of the via 50) can be omitted. As a result, the number of manufacturing steps can be reduced and the manufacturing process of the semiconductor device can be simplified, and the resistance of the via portion of the wiring can be prevented from increasing. In addition, since the formation of the metal cap film at the bottom of the via 50 is omitted, as a pretreatment before the formation of the conductive barrier film 53, physical sputter etching using argon (Ar) ions or reduction Reactive plasma treatment in an atmosphere containing a gas (eg, a hydrogen atmosphere) can be used.
(実施の形態 4 )  (Embodiment 4)
図 3 1〜図 3 4は、 本発明の他の実施の形態である半導体装置の製造工程中の 要部断面図である。 図 1 7までの製造工程は上記実施の形態 1とほぼ同様である ので、 ここではその説明は省略し、 図 1 7に続く製造工程について説明する。 な お、 図 3 1〜図 3 4においても、 図 1の絶縁膜 1 1より下の構造に対応する部分 は図示を省略している。  31 to 34 are main-portion cross-sectional views of a semiconductor device according to another embodiment of the present invention during the manufacturing steps thereof. Since the manufacturing steps up to FIG. 17 are substantially the same as those in the first embodiment, the description thereof is omitted here, and the manufacturing steps following FIG. 17 will be described. In FIG. 31 to FIG. 34, portions corresponding to the structure below the insulating film 11 in FIG. 1 are not shown.
上記実施の形態 1と同様にして図 1 7の構造が得られた後、 図 3 1に示される ように、 配線 3 5が埋め込まれた絶縁膜 2 6上に、 上記絶縁膜 2 3〜 2 6を形成 した工程と同様の工程および材料によって、 絶縁膜 （パリァ絶縁膜） 4 3、 絶縁 膜 （層間絶縁膜） 4 4、 絶縁膜 (エッチングストッパ膜) 4 5および絶縁膜 （層 間絶縁膜） 4 6を形成する。 本実施の形態では、 配線 3 5の形成後、 配線 3 5上 に金属キャップ膜を形成せずに （すなわち上記実施の形態 1における金属キヤッ プ膜 4 2を省略し）、配線 3 5が埋め込まれた絶縁膜 2 6上に絶縁膜 4 3〜 4 6を 形成する。 それから、 図 3 2に示されるように、 配線開口部として、 ビア 3 0お よび配線溝 3 1と同様にして、 配線 3 5に達して配線 3 5の主導体膜 3 4を露出 するビア （開口部） 5 0と配線溝 （開口部） 5 1とを形成する。 その後、 図 3 3 • に示されるように、 本実施の形態では、 ビア 5 0から露出する配線 3 5 (主導体 膜 3 4 ) 上に金属キャップ膜を形成せずに （すなわち上記実施の形態 1における 金属キャップ膜 5 2を省略し）、半導体基板 1上（ビア 5 0および配線溝 5 1の底 部および側壁を含む絶縁膜 4 6上） に導電性パリア膜 5 3を導電性パリア膜 1 8 ， 3 3と同様の材料および手法により形成し、 導電性パリア膜 5 3上にビア 5 0 および配線溝 5 1を埋めるように主導体膜 5 4を主導体膜 1 9， 3 4と同様の材 料および手法により形成する。 そして、 図 3 4に示されるように、 CMP法によ り絶縁膜 4 6上の不要な主導体膜 5 4および導電性パリア膜 5 3を除去してビア 5 0および配線溝 5 1を埋めかつ配線 3 5と電気的に接続された配線 （第 3層配 H) 5 5を形成する。 After the structure of FIG. 17 is obtained in the same manner as in the first embodiment, as shown in FIG. 31, the insulating films 23 to 2 are embedded on the insulating film 26 in which the wirings 35 are embedded. By the same process and material as the process of forming 6, the insulating film (Parier insulating film) 43, the insulating film (interlayer insulating film) 44, the insulating film (etching stopper film) 45, and the insulating film (interlayer insulating film) To form 4 6). In the present embodiment, after the formation of the wiring 35, the wiring 35 is embedded without forming a metal cap film on the wiring 35 (that is, omitting the metal cap film 42 in the first embodiment). The insulating films 43 to 46 are formed on the insulating film 26 thus formed. Then, as shown in FIG. 32, as the wiring opening, the via () that reaches the wiring 35 and exposes the main conductor film 34 of the wiring 35 in the same manner as the via 30 and the wiring groove 31. An opening) 50 and a wiring groove (opening) 51 are formed. Thereafter, as shown in FIG. 33, in the present embodiment, the metal cap film is not formed on the wiring 35 (main conductor film 34) exposed from the via 50 (that is, in the above-described embodiment). 1, the conductive cap film 52 is omitted, and the conductive barrier film 53 is formed on the semiconductor substrate 1 (on the insulating film 46 including the bottom and side walls of the via 50 and the wiring groove 51). The main conductor film 54 is formed by the same material and method as those of 18 and 33, and the main conductor film 54 and the main conductor films 19 and 34 are filled on the conductive barrier film 53 so as to fill the via 50 and the wiring groove 51. It is formed using the same materials and techniques. Then, as shown in FIG. 34, the unnecessary main conductor film 54 and the conductive barrier film 53 on the insulating film 46 are removed by the CMP method to fill the via 50 and the wiring groove 51. And wiring electrically connected to wiring 35 (third layer wiring H) Form 5 5
多層配線構造を有する半導体装置において、 下層配線 （ここでは配線 3 5 ) の ボリュームが小さい場合には、 ストレスマイグレーションに起因した不良が生じ にくいので、 本実施の形態のように、 その下層配線 （ここでは配線 3 5 ) の金属 キャップ膜 （ここでは金属キャップ膜 4 2 ) と、 その下層配線に接続 （到達） す るビア （ここではビア 5 0 ) の底部の金属キャップ膜 （ここでは金属キャップ膜 5 2 ) とを省略することもできる。 これにより、 製造工程数を低減して半導体装 置の製造工程を簡略化でき、 また配線のビア部の抵抗増加を防止することができ る。  In a semiconductor device having a multilayer wiring structure, if the volume of the lower wiring (wiring 35 in this case) is small, defects due to stress migration are less likely to occur. In this case, the metal cap film (here, the metal cap film 42) of the wiring 35) and the metal cap film (here, the metal cap film) at the bottom of the via (here, the via 50) that connects to (or reaches) the underlying wiring 5 2) can also be omitted. As a result, the number of manufacturing steps can be reduced, the manufacturing steps of the semiconductor device can be simplified, and an increase in the resistance of the via portion of the wiring can be prevented.
(実施の形態 5 )  (Embodiment 5)
図 3 5〜図 3 8は、 本発明の他の実施の形態である半導体装置の製造工程中の 要部断面図である。 図 1 7までの製造工程は上記実施の形態 1とほぼ同様である ので、 ここではその説明は省略し、 図 1 7に続く製造工程について説明する。 な お、 図 3 5〜図 3 8においても、 図 1の絶縁膜 1 1より下の構造に対応する部分 は図示を省略している。 なお、 本実施の形態では、 配線 3 5を半導体装置の比較 的上層の配線であると想定して説明する。  35 to 38 are main-portion cross-sectional views of a semiconductor device according to another embodiment of the present invention during the manufacturing steps thereof. Since the manufacturing steps up to FIG. 17 are substantially the same as those in the first embodiment, the description thereof is omitted here, and the manufacturing steps following FIG. 17 will be described. Note that, also in FIGS. 35 to 38, parts corresponding to the structure below the insulating film 11 in FIG. 1 are not shown. Note that, in the present embodiment, the description will be made assuming that the wiring 35 is a wiring in a layer relatively higher than the semiconductor device.
上記実施の形態 1と同様にして図 1 7の構造が得られた後、 図 3 5に示される ように、 配線 3 5に対して窪み 2 1と同様の窪みを形成した後、 配線 3 5上に金 属キャップ膜 4 2を金属キヤップ膜 2 2と同様の材料および手法により形成する 。 それから、 配線 3 5が埋め込まれた絶縁膜 2 6上に、 上記絶縁膜 2 3， 2 4を 形成した工程と同様の工程および材料によって、 絶縁膜 （パリア絶縁膜） 6 3お よび絶縁膜 （層間絶縁膜） 6 4を形成する。  After the structure shown in FIG. 17 is obtained in the same manner as in the first embodiment, as shown in FIG. 35, a recess similar to the recess 21 is formed in the wire 35, and then the wire 35 A metal cap film 42 is formed thereon by the same material and method as the metal cap film 22. Then, on the insulating film 26 in which the wirings 35 are embedded, the insulating film (paria insulating film) 63 and the insulating film ( An interlayer insulating film) 64 is formed.
次に、 フォトリソグラフィ法を用いて絶縁膜 6 3， 6 4をドライエッチングす ることなどによって、 配線 3 5に達するスルーホールまたはビア 6 5を形成する 。 このとき、 ビア 6 5の底部では、 金属キャップ膜 4 2の全部または一部が除去 (エッチング） されており、 主導体膜 3 4の上面が露出される。 これにより、 図 3 5の構造が得られる。  Next, through holes or vias 65 reaching the wirings 35 are formed by, for example, dry etching the insulating films 63 and 64 using a photolithography method. At this time, at the bottom of the via 65, all or a part of the metal cap film 42 has been removed (etched), and the upper surface of the main conductor film 34 is exposed. As a result, the structure shown in FIG. 35 is obtained.
次に、 半導体基板 1の主面上の全面 （すなわちビア 6 5の底部および側壁上を 含む絶縁膜 6 4上） に、 例えばチタン （T i ) 膜および窒化チタン （T i N) 膜 の積層膜からなる導電性パリア膜 6 6を形成する。 導電性パリア膜 66の成膜に は、 スパッタリング法、 CVD法または原子層デポジション （ALD) 法などを 用いることができる。 導電性パリア膜 66の成膜の際には、 チタン （T i ) 膜を 最初に成膜することが好ましい。 ビア 65の形成後で導電性パリア膜 66の形成 前に、 ビア 6 5底部で金属キャップ膜は形成しなくともよい。 これは、 導電性パ リア膜 66の成膜の際に、 最初にチタン （T i ) 膜を成膜するので、 ビア 65底 部で露出する配線 35 (主導体膜 34) 上にチタン （T i ) 膜が形成されること になり、 このチタン （T i) 膜をビア 65底に揷入することによってビア 65底 部での接着強度が向上し、 S I V (Stress-Induced Voiding) が抑制されるため である。 Next, for example, a titanium (Ti) film and a titanium nitride (TiN) film are formed on the entire surface on the main surface of the semiconductor substrate 1 (that is, on the insulating film 64 including the bottom of the via 65 and the side wall). A conductive barrier film 66 made of a laminated film of the above is formed. The conductive barrier film 66 can be formed by a sputtering method, a CVD method, an atomic layer deposition (ALD) method, or the like. When forming the conductive barrier film 66, it is preferable to form a titanium (T i) film first. After the formation of the via 65 and before the formation of the conductive barrier film 66, the metal cap film may not be formed at the bottom of the via 65. This is because, when the conductive barrier film 66 is formed, a titanium (T i) film is formed first, so that the titanium (T i) film is formed on the wiring 35 (main conductor film 34) exposed at the bottom of the via 65. i) A film is formed. By inserting this titanium (T i) film into the bottom of the via 65, the adhesive strength at the bottom of the via 65 is improved, and SIV (Stress-Induced Voiding) is suppressed. That is because.
それから、 CVD法などによってタングステン膜 67を導電性パリア膜 66上 にビア 65を埋めるように形成し、 絶縁膜 64上の （すなわちビア 65外部の） 不要なタングステン膜 67および導電性パリア膜 66を例えば CMP法などによ つて除去することにより、 ビア 65を埋める導電'性パリア膜 66およびタンダス テン膜 67からなるプラグ 68を形成する。 これにより、 図 36の構造が得られ る。  Then, a tungsten film 67 is formed on the conductive barrier film 66 so as to fill the via 65 by a CVD method or the like, and the unnecessary tungsten film 67 and the conductive barrier film 66 on the insulating film 64 (that is, outside the via 65) are formed. For example, by removing by a CMP method or the like, a plug 68 made of a conductive film 66 and a tungsten film 67 filling the via 65 is formed. As a result, the structure shown in FIG. 36 is obtained.
次に、 プラグ 68が埋め込まれた絶縁膜 64上に、 例えばスパッタリング法を 用いて、 チタン （T i) 膜と窒化チタン （T i N) 膜との積層膜からなる導体膜 69 aと、 相対的に厚いアルミニウム （A 1) 単体またはアルミニウム合金など のアルミニウムを主成分とする導体膜 （アルミユウム膜） 69 bと、 チタン （T i ) 膜と窒化チタン （T i N) 膜との積層膜からなる導体膜 69 cとを順に形成 する。 導体膜 69 bの材料として、 銅 （Cu) を例えば 0. 5重量％程度含むァ ルミニゥム合金などを用いることができるが、 アルミニウムが主成分であれば、 Cuやその他の添加物 （S iなど） を任意の割合で含んでいてもよい。 導体膜 6 9 a, 69 cは、 下層側がチタン膜で、 上層側が窒化チタン膜である積層膜であ る。 導体膜 69 a, 69 cはパリァ導体膜として機能することができ、 導体膜 6 9 cはフォトリソグラフイエ程における反射防止膜としても機能することができ る。  Next, on the insulating film 64 in which the plug 68 is embedded, a conductive film 69a composed of a laminated film of a titanium (Ti) film and a titanium nitride (TiN) film is formed by, for example, a sputtering method. Thick aluminum (A1) alone or a conductor film (aluminum film) consisting mainly of aluminum such as aluminum alloy (b) 69b, and a laminated film of a titanium (Ti) film and a titanium nitride (TiN) film And a conductive film 69c formed in this order. As a material of the conductive film 69b, an aluminum alloy containing copper (Cu) at about 0.5% by weight, for example, can be used. If aluminum is the main component, Cu and other additives (Si, etc.) ) May be contained in any ratio. The conductor films 69a and 69c are laminated films in which the lower layer is a titanium film and the upper layer is a titanium nitride film. The conductor films 69a and 69c can function as a parier conductor film, and the conductor film 69c can also function as an anti-reflection film in a photolithographic process.
それから、 フォトリソグラフィ法などを用いて導体膜 69 a、 69 b、 69 c の積層構造 （積層膜） をドライエッチングして所定のパターンに加工し、 配線 ( アルミニゥム配線） 6 9を形成する。 これにより、 図 3 7の構造が得られる。 配 線 6 9は、 プラグ 6 8を介して配線 3 5に電気的に接続されている。 この上層配 線である配線 6 9は、 パッド （P AD) 電極として機能することができる。 Then, using photolithography, etc., the conductive films 69a, 69b, 69c The laminated structure (laminated film) is dry-etched and processed into a predetermined pattern to form wiring (aluminum wiring) 69. As a result, the structure shown in FIG. 37 is obtained. The wiring 69 is electrically connected to the wiring 35 via a plug 68. The wiring 69 serving as this upper wiring can function as a pad (PAD) electrode.
次に、 図 3 8に示されるように、 パッド電極としての配線 6 9の保護層 (Protection Layer) として、 絶縁膜 6 4上に配線 6 9を覆うように、 絶縁膜 7 0を形成する。 絶縁膜 7 0は、 例えば、 酸化シリコン膜 （T E O S酸化膜） 、 窒 化シリコン （ S i N) 膜または S O G (Spin On Glass) 膜などから選択された少 なくとも一種類以上の材料膜を含む単体膜または積層膜で形成されている。  Next, as shown in FIG. 38, an insulating film 70 is formed on the insulating film 64 so as to cover the wiring 69 as a protection layer of the wiring 69 as a pad electrode. The insulating film 70 includes, for example, at least one material film selected from a silicon oxide film (TEOS oxide film), a silicon nitride (SIN) film, a SOG (Spin On Glass) film, and the like. It is formed of a single film or a laminated film.
次に、 フォトリソグラフィ法を用いて絶縁膜 7 0をエッチングすることなどに よって、 絶縁膜 7 0にビア 7 1を形成する。 ビア 7 1の底部ではパッド電極とし ての配,镍 6 9が露出する。 その後、 図示はしないけれども、 ビア 7 1から露出す る配線 6 9に引出し電極を結線し、 半導体装置をパッケージと一体化させること ができる。  Next, a via 71 is formed in the insulating film 70 by, for example, etching the insulating film 70 using a photolithography method. At the bottom of the via 71, the arrangement as a pad electrode, 镍 69, is exposed. Thereafter, although not shown, an extraction electrode is connected to the wiring 69 exposed from the via 71, and the semiconductor device can be integrated with the package.
(実施の形態 6 )  (Embodiment 6)
図 3 9〜図 4 1は、 本発明の他の実施の形態である半導体装置の製造工程中の 要部断面図である。 図 1 7までの製造工程は上記実施の形態 5とほぼ同様である ので、 ここではその説明は省略し、 図 1 7に続く製造工程について説明する。 な お、 図 3 9〜図 4 1においても、 図 1の絶縁膜 1 1より下の構造に対応する部分 は図示を省略している。 なお、 本実施の形態では、 配線 3 5を半導体装置の比較 的上層の配線であると想定して説明する。  FIG. 39 to FIG. 41 are cross-sectional views of main parts during a manufacturing process of a semiconductor device according to another embodiment of the present invention. Since the manufacturing steps up to FIG. 17 are almost the same as those of the fifth embodiment, the description is omitted here, and the manufacturing steps following FIG. 17 will be described. In FIG. 39 to FIG. 41, portions corresponding to the structure below the insulating film 11 in FIG. 1 are not shown. Note that, in the present embodiment, the description will be made assuming that the wiring 35 is a wiring in a layer relatively higher than the semiconductor device.
上記実施の形態 1と同様にして図 1 7の構造が得られた後、 図 3 9に示される ように、 配,櫞 3 5に対して窪み 2 1と同様の窪みを形成した後、 配線 3 5上に金 属キャップ膜 4 2を金属キャップ膜 2 2と同様の材料および手法により形成する 。 それから、 配線 3 5が埋め込まれた絶縁膜 2 6上に、 上記絶縁膜 2 3， 2 4を 形成した工程と同様の工程および材料によって、 絶縁膜 （パリア絶縁膜） 6 3お よび絶縁膜 （層間絶縁膜） 6 4を形成する。  After the structure shown in FIG. 17 is obtained in the same manner as in the first embodiment, as shown in FIG. 39, a depression similar to the depression 21 is formed in the arrangement 35 and the wiring is formed. A metal cap film 42 is formed on 35 using the same material and method as the metal cap film 22. Then, on the insulating film 26 in which the wirings 35 are embedded, the insulating film (paria insulating film) 63 and the insulating film ( An interlayer insulating film) 64 is formed.
次に、 フォトリソグラフィ法を用いて絶,椽膜 6 3， 6 4をドライエッチングす ることなどによって、 配線 3 5に達するスルーホールまたはビア 8 5を形成する o このとき、 ビア 8 5の底部では、 金属キャップ膜 4 2の全部または一部が除去 (エッチング） されており、 主導体膜 3 4の上面が露出される。 Next, through holes or vias 85 reaching the wirings 35 are formed by, for example, dry etching the films 6 3 and 6 4 using photolithography. o At this time, at the bottom of the via 85, all or part of the metal cap film 42 has been removed (etched), and the upper surface of the main conductor film 34 is exposed.
次に、 ビア 8 5が形成された絶縁膜 6 4上に、 上記実施の形態 5の導体膜 6 9 a , 6 9 b , 6 9 cと同様の手法および材料を用いて、 チタン （T i ) 膜と窒ィ匕 チタン （T i N) 膜との積層膜からなる導体膜 8 9 aと、 相対的に厚いアルミ二 ゥム （A 1 ) 単体またはアルミニウム合金などのアルミニウムを主成分とする導 体膜 （アルミニウム膜） 8 9 bと、 チタン （T i ) 膜と窒化チタン （T i N) 膜 との積層膜からなる導体膜 8 9 cとを順に形成する。 この際、 下地の銅の主導体 膜 3 4との接着性 （密着性） を高めるために、 ビア 8 5形成後に最初に形成する 材料膜はチタン （T i ) 膜であることが好ましい。 導体膜 8 9 a , 8 9 cは、 下 層側がチタン膜で、 上層側が窒化チタン膜である積層膜である。 導体膜 8 9 bの 材料として、 銅 （C u ) を例えば 0 . 5重量％程度含むアルミニウム合金を用い ることができるが、 アルミ二ゥムが主成分であれば、 C uやその他の添加物 ( S iなど） を任意の割合で含んでいてもよい。  Next, titanium (Ti) is formed on the insulating film 64 on which the via 85 is formed by using the same method and material as those of the conductive films 69a, 69b, 69c of the fifth embodiment. ) Conductive film 89 a composed of a laminated film of a film and a titanium nitride (TiN) film, and relatively thick aluminum (A 1) alone or mainly containing aluminum such as an aluminum alloy A conductor film (aluminum film) 89b and a conductor film 89c composed of a laminated film of a titanium (Ti) film and a titanium nitride (TiN) film are sequentially formed. At this time, it is preferable that the material film formed first after the formation of the via 85 be a titanium (T i) film in order to enhance the adhesion (adhesion) of the underlying copper to the main conductor film 34. The conductor films 89a and 89c are laminated films in which the lower layer is a titanium film and the upper layer is a titanium nitride film. As a material of the conductor film 89b, an aluminum alloy containing, for example, about 0.5% by weight of copper (Cu) can be used. However, if aluminum is a main component, Cu and other additives are used. An object (such as Si) may be contained in an arbitrary ratio.
次に、 図 4 0に示されるように、 フォトリソグラフィ法などを用いて導体膜 8 9 a , 8 9 b , 8 9 cの積層構造 （積層膜） をドライエッチングして所定のパタ ーンに加工し、 パッド電極層として機能する配線 （アルミニウム配線） 8 9を形 成する。 配線 8 9は、 ビア 8 5に埋め込まれた部分を介して配線 3 5に電気的に 接続されている。  Next, as shown in FIG. 40, the laminated structure (laminated film) of the conductor films 89a, 89b, and 89c is dry-etched using a photolithography method or the like into a predetermined pattern. Process to form wiring (aluminum wiring) 89 that functions as pad electrode layer. The wiring 89 is electrically connected to the wiring 35 via a portion embedded in the via 85.
次に、 図 4 1に示されるように、 パッド電極層としての配線 8 9の保護層 (Protection Layer) として、 絶縁膜 6 4上に配線 8 9を覆うように、 上記実施 の形態 5の絶縁膜 7 0と同様の材料を用いて絶縁膜 9 0を形成する。  Next, as shown in FIG. 41, as a protection layer of the wiring 89 as a pad electrode layer, the insulation of the fifth embodiment is covered on the insulating film 64 so as to cover the wiring 89. An insulating film 90 is formed using the same material as the film 70.
次に、 フォトリソグラフィ法を用いて絶縁膜 9 0をエッチングすることなどに よって、 絶縁膜 9 0にビア （開口部） 9 1を形成する。 ビア 9 1の底部ではパッ ド電極層としての配,櫞 8 9が露出する。 その後、 図示はしないけれども、 ビア 9 1から露出するパッド電極層としての配線 8 9に引出し電極を結線し、 半導体装 置をパッケージと一体ィ匕させることができる。  Next, a via (opening) 91 is formed in the insulating film 90 by, for example, etching the insulating film 90 using a photolithography method. At the bottom of the via 91, the arrangement 89 as a pad electrode layer is exposed. Thereafter, although not shown, a lead electrode is connected to a wiring 89 serving as a pad electrode layer exposed from the via 91, and the semiconductor device can be integrated with the package.
(実施の形態 7 )  (Embodiment 7)
図 4 2は、 本発明の他の実施の形態である半導体装置の要部断面図である。 図 42に示されるように、 本実施の形態の半導体装置は、 多層配線構造を有し ている。 例えば上記実施の形態 1と同様にして、 半導体基板 1 0 1に、 素子分離 領域 1 02、 ゥエル領域 （ p型または n型のゥエル領域） 1 03が形成され、 ザ ート絶縁膜 1 04、 ゲート電極 105およびソース、 ドレインとしての半導体領 域 （n型または p型の半導体領域） 1 08を有する複数の MI SFET (nチヤ ネル型または Pチャネル型の MI SFET) 1 09が形成されている。 そして、 それらの MI SFET 1 09に電気的に接続された第 1層配線 1 1 1、 第 2層配 線 1 1 2、 第 3層配線 1 1 3、 第 4層配線 1 14、 第 5層配線 1 1 5および第 6 層配線 1 1 6が、 半導体基板 1 0 1上に形成された層間絶縁膜としての絶縁膜 1 21、 エッチングストッパ膜としての絶縁膜 1 22、 パリア絶縁膜としての絶縁 膜 1 23および保護膜としての絶縁膜 1 24の積層構造内に形成されている。 プラグ 1 3 1を介して MI SFET 1 09に電気的に接続されている第 1層配 線 1 1 1はダマシン法 （シングルダマシン法） により形成されているが、 本実施 の形態では第 1層配線 1 1 1にはタングステン配線を用いている。 従って、 第 1 層配線 1 1 1は、 絶縁膜 1 2 1， 1 22に形成された配線溝内に窒ィ匕チタンなど のパリア膜とタングステン膜とを形成し、 配線溝外部の不要なタングステン膜お よび窒ィ匕チタン膜を CMP法によって除去することにより形成されている。 タン ダステン配 #泉においては、 銅膜を有していないために銅の拡散現象は生じない。 このため、 タングステン配線からなる第 1層配線 1 1 1の上面には、 金属キヤッ プ膜を形成する必要はない。 FIG. 42 is a cross-sectional view of a main part of a semiconductor device according to another embodiment of the present invention. As shown in FIG. 42, the semiconductor device of the present embodiment has a multilayer wiring structure. For example, in the same manner as in the first embodiment, an element isolation region 102 and a p-type region (p-type or n-type p-type region) 103 are formed in the semiconductor substrate 101, and a third insulating film 104, A plurality of MI SFETs (n-channel or P-channel MI SFETs) 109 having a gate electrode 105 and a semiconductor region (n-type or p-type semiconductor region) 108 as a source and a drain are formed. . Then, the first-layer wiring 111, the second-layer wiring 112, the third-layer wiring 113, the fourth-layer wiring 114, and the fifth-layer wiring electrically connected to those MI SFETs 109 The wiring 1 15 and the sixth-layer wiring 1 16 are formed on the semiconductor substrate 101 by an insulating film 122 as an interlayer insulating film, an insulating film 122 as an etching stopper film, and an insulating film as a paria insulating film. It is formed in a laminated structure of a film 123 and an insulating film 124 as a protective film. The first-layer wiring 111 electrically connected to the MI SFET 109 via the plug 131 is formed by a damascene method (single damascene method). The wiring 111 is a tungsten wiring. Therefore, the first-layer wiring 111 is formed by forming a tungsten film and a barrier film such as titanium nitride in the wiring groove formed in the insulating films 122 and 122, and forming unnecessary tungsten outside the wiring groove. It is formed by removing the film and the titanium nitride film by a CMP method. In the Tungsten hot spring, the copper diffusion phenomenon does not occur because there is no copper film. Therefore, it is not necessary to form a metal cap film on the upper surface of the first layer wiring 111 made of tungsten wiring.
第 2層配線 1 1 2〜第 5層配線 1 1 5はダマシン法 （図 42の例ではデュアル ダマシン法） により形成されている。 従って、 第 2層配線 1 1 2〜第 5層配線 1 1 5のそれぞれは、 絶縁膜に形成された配線開口部 （配線溝およびビア） 内に導 電性パリァ膜と銅の主導体膜とを形成し、 配線開口部外部の不要な主導体膜およ び導電性パリア膜を CM P法によって除去することにより形成されている。 第 2層配線 1 1 2〜第 5層配線 1 1 5のうち、 第 2層配線 1 1 2から第 3層配 線 1 1 3にかけての工程は、 上記実施の形態 1における配線 35から配線 55に かけての工程と同様にして形成されている。 すなわち領域 1 32 aの構造は、 図 1 8に示されるような上記実施の形態 1の配線 35の上面近傍領域の構造と同様 である。 このため、 第 2層配線 1 1 2上には、 金属キャップ膜 4 2に対応する金 属キャップ膜 1 1 2 aが形成され、 更に金属キャップ膜 5 2に対応する金属キヤ ップ膜 1 1 2 b力 第 3層配線 1 1 3形成用のビア底部で露出する第 2層配線 1 1 2の銅の主導体膜上に形成されている。 また、 比較的下層の配線層である第 2 層配線 1 1 2は、 配線間隔が比較的狭いので、 領域 1 3 2 bでは上記実施の形態 2のビア 3 0 aのように目外れが生じている。 このため、 金属キャップ膜 1 1 2 bの成膜法には、上記実施の形態 2の手法（図 2 4 )を適用することが好ましい。 第 3層配線 1 1 3から第 4層配線 1 1 4にかけての工程は、 上記実施の形態 4 における配線 3 5から配線 5 5にかけての工程と同様にして形成されている。 す なわち領域 1 3 3の構造は、 図 3 4に示されるような上記実施の形態 4の配線 3 5の上面近傍領域の構造と同様である。 このため、 第 3層配線 1 1 3上には、 金 属キヤップ膜は形成されていない。 The second-layer wiring 112 to the fifth-layer wiring 115 are formed by a damascene method (in the example of FIG. 42, a dual damascene method). Therefore, each of the second-layer wiring 112 to the fifth-layer wiring 115 has a conductive parier film and a copper main conductor film in wiring openings (wiring grooves and vias) formed in the insulating film. Is formed by removing unnecessary main conductor films and conductive barrier films outside the wiring openings by the CMP method. The steps from the second layer wiring 112 to the third layer wiring 113 of the second layer wiring 112 to the fifth layer wiring 115 are the same as the steps from the wiring 35 to the wiring 55 in the first embodiment. It is formed in the same way as the process up to. That is, the structure of the region 132a is similar to the structure of the region near the upper surface of the wiring 35 of the first embodiment as shown in FIG. It is. For this reason, a metal cap film 112 a corresponding to the metal cap film 42 is formed on the second-layer wiring 112, and a metal cap film 111 corresponding to the metal cap film 52 is further formed. 2 b force is formed on the copper main conductor film of the second layer wiring 112 exposed at the bottom of the via for forming the third layer wiring 113. In addition, since the second-layer wiring 112, which is a relatively lower wiring layer, has a relatively narrow wiring interval, in the region 132b, as in the case of the via 30a according to the second embodiment described above, a gap occurs. ing. Therefore, it is preferable to apply the method of Embodiment 2 (FIG. 24) to the method of forming the metal cap film 112b. The steps from the third layer wiring 113 to the fourth layer wiring 114 are formed in the same manner as the steps from the wiring 35 to the wiring 55 in the fourth embodiment. That is, the structure of the region 133 is the same as the structure of the region near the upper surface of the wiring 35 of the fourth embodiment as shown in FIG. Therefore, no metal cap film is formed on the third layer wiring 113.
第 4層配線 1 1 4から第 5層配線 1 1 5にかけての工程は、 上記実施の形態 1 における配線 3 5から配線 5 5にかけての工程と同様にして形成されている。 す なわち領域 1 3 4の構造は、 図 1 8に示されるような上記実施の形態 1の配線 3 5の上面近傍領域の構造と同様である。 このため、 第 4層配線 1 1 4上には、 金 属キャップ膜 4 2に対応する金属キャップ膜 1 1 4 aが形成され、 更に金属キヤ ップ膜 5 2に対応する金属キャップ膜 1 1 4 b力 第 5層配線 1 1 5形成用のビ ァ底部で露出する第 4層配線 1 1 4の銅の主導体膜上形成されている。 また、 比 較的上層の配線層である第 4層配線 1 1 4は、 配線間隔が比較的広いので、 上記 実施の形態 2のビア 3 0 aのように目外れは生じない。  The steps from the fourth layer wiring 114 to the fifth layer wiring 115 are formed in the same manner as the steps from the wiring 35 to the wiring 55 in the first embodiment. That is, the structure of the region 134 is the same as the structure of the region near the upper surface of the wiring 35 of the first embodiment as shown in FIG. Therefore, a metal cap film 114 a corresponding to the metal cap film 42 is formed on the fourth layer wiring 114, and a metal cap film 111 corresponding to the metal cap film 52 is further formed. 4 b force Fifth layer wiring 111 is formed on the copper main conductor film of fourth layer wiring 114 exposed at the bottom of via. Further, since the fourth-layer wiring 114, which is a relatively upper wiring layer, has a relatively large wiring interval, there is no gap as in the via 30a of the second embodiment.
第 5層配線 1 1 5はプラグ 1 1 6 aを介してアルミニウム配線である第 6層配 線 1 1 6に電気的に接続されている。 第 5層配線 1 1 5、 プラグ 1 1 6 aおよび 第 6層配線 1 1 6は、 上記実施の形態 5の配線 3 5、 プラグ 6 8および配線 6 9 と同様にして形成されている。 すなわち領域 1 3 5の構造は、 図 3 8に示される ような上記実施の形態 5の配線 3 5の上面近傍領域の構造と同様である。 このた め、 第 5層配線 1 1 5上には、 金属キャップ膜 4 2に対応する金属キャップ膜 1 1 5 aが形成されている。  The fifth-layer wiring 115 is electrically connected to a sixth-layer wiring 116 which is an aluminum wiring via a plug 116a. The fifth-layer wiring 1 15, plug 1 16 a and sixth-layer wiring 1 16 are formed in the same manner as the wiring 35, plug 68 and wiring 69 of the fifth embodiment. That is, the structure of the region 135 is the same as the structure of the region near the upper surface of the wiring 35 of the fifth embodiment as shown in FIG. For this reason, a metal cap film 115 a corresponding to the metal cap film 42 is formed on the fifth layer wiring 115.
保護膜としての絶縁膜 1 2 4に形成されたビアから露出した第 6層配線 1 1 6 上には、 引き出し電極 （例えばバンプ電極） 1 4 1が形成されている。 6th layer wiring exposed from via formed in insulating film 1 2 4 as protective film 1 1 6 A lead electrode (for example, a bump electrode) 144 is formed on the top.
このように、 上記実施の形態 1〜 6を適宜組み合わせて半導体装置の多層配線 構造を形成することができる。  As described above, the multilayer wiring structure of the semiconductor device can be formed by appropriately combining the first to sixth embodiments.
以上、 本発明者によってなされた発明をその実施の形態に基づき具体的に説明 したが、 本発明は前記実施の形態に限定されるものではなく、 その要旨を逸脱し ない範囲で種々変更可能であることは言うまでもない。  As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various changes can be made without departing from the gist of the invention. Needless to say, there is.
前記実施の形態では、 M I S F E Tを有する半導体装置について説明したが、 本発明は、 これに限定されるものではなく、 銅を主成分とする主導体膜を含む配 線を有する種々の半導体装置に適用することができる。  In the above embodiment, the semiconductor device having the MISFET has been described. However, the present invention is not limited to this, and is applicable to various semiconductor devices having a wiring including a main conductor film containing copper as a main component. can do.
本願において開示される発明の実施形態のうち、 代表的なものによって得られ る効果を簡単に説明すれば以下のとおりである。  The effects obtained by the typical embodiments of the invention disclosed in the present application will be briefly described as follows.
下層銅配線上にキヤップ導体膜を形成し、 下層銅配線に接続するビア形成時に ビア底部でそのキヤップ導体膜を除去し、 ビア底部の下層銅配線上に再度キャッ プ導体膜を形成したことにより、 埋込銅配線を有する半導体装置の信頼性を向上 させることができる。 産業上の利用可能性 ，  By forming a cap conductor film on the lower copper wiring, removing the cap conductor film at the bottom of the via when forming a via connected to the lower copper wiring, and forming a cap conductor film again on the lower copper wiring at the bottom of the via Thus, the reliability of the semiconductor device having the embedded copper wiring can be improved. Industrial applicability,
本発明の半導体装置は、埋込銅配線を有する半導体装置に適用して有効である。  The semiconductor device of the present invention is effective when applied to a semiconductor device having embedded copper wiring.

Claims

請 求 の 範 囲 The scope of the claims
1 . 半導体基板と、 1. a semiconductor substrate;
前記半導体基板上に形成された第 1絶縁膜と、  A first insulating film formed on the semiconductor substrate,
前記第 1絶縁膜に形成された第 1開口部と、  A first opening formed in the first insulating film,
前記第 1開口部の側壁および底部上に形成された第 1バリァ導体膜と、 前記第 1開口部内を埋めるように前記第 1パリァ導体膜上に形成された銅を主成分とす る第 1導体膜とを有する第 1配線と、  A first barrier conductor film formed on a side wall and a bottom of the first opening, and a first barrier film mainly composed of copper formed on the first barrier conductor film so as to fill the first opening. A first wiring having a conductive film;
前記第 1導体膜上に形成された第 1キヤップ導体膜と、  A first cap conductive film formed on the first conductive film,
前記第 1絶縁膜および前記第 1キャップ導体膜上に形成された第 2絶縁膜と、 前記第 2絶縁膜に形成され、 その底部で前記第 1導体膜を露出する第 2開口部 と、  A second insulating film formed on the first insulating film and the first cap conductive film, and a second opening formed on the second insulating film and exposing the first conductive film at a bottom thereof;
前記第 2開口部の底部で露出する前記第 1導体膜上に形成された第 2キャップ 導体膜と、  A second cap conductive film formed on the first conductive film exposed at the bottom of the second opening;
前記第 2開口部の側壁上と底部の前記第 2キヤップ導体膜上に形成された第 2 パリア導体膜と、  A second barrier conductor film formed on the side wall of the second opening and on the second cap conductor film at the bottom;
前記第 2開口部内を埋めるように前記第 2パリア導体膜上に形成された鲖を主 成分とする第 2導体膜と、  A second conductor film having 鲖 as a main component formed on the second barrier conductor film so as to fill the second opening,
を有することを特徴とする半導体装置。  A semiconductor device comprising:
2 . 請求項 1記載の半導体装置において、 2. The semiconductor device according to claim 1,
前記第 2開口部は、 前記第 1キャップ導体膜を貫通して前記第 1導体膜に到達 していることを特徴とする半導体装置。  The semiconductor device, wherein the second opening penetrates the first cap conductor film and reaches the first conductor film.
3 . 請求項 1記載の半導体装置において、  3. The semiconductor device according to claim 1,
前記第 1キャップ導体膜は、 タングステン、 タングステン合金、 コバルト、 コ パルト合金、二ッケルまたは二ッケル合金からなることを特徴とする半導体装置。 The semiconductor device according to claim 1, wherein the first cap conductor film is made of tungsten, a tungsten alloy, cobalt, a cobalt alloy, nickel, or nickel alloy.
4 . 請求項 1記載の半導体装置において、 4. The semiconductor device according to claim 1,
前記第 2キャップ導体膜は、 タングステン、 タングステン合金、 コバルト、 コ パルト合金、二ッケルまたは二ッケル合金からなることを特徴とする半導体装置。 The semiconductor device, wherein the second cap conductor film is made of tungsten, a tungsten alloy, cobalt, a cobalt alloy, nickel, or a nickel alloy.
5 . 請求項 1記載の半導体装置において、 前記第 1キヤップ導体膜の膜厚は、 2〜 2 0 n mの範囲内であることを特徴と する半導体装置。 5. The semiconductor device according to claim 1, The semiconductor device according to claim 1, wherein a thickness of the first cap conductor film is in a range of 2 to 20 nm.
6 . 請求項 1記載の半導体装置において、  6. The semiconductor device according to claim 1,
前記第 2キャップ導体膜の膜厚は、 2〜2 0 n mの範囲内であることを特徴と する半導体装置。  The semiconductor device according to claim 1, wherein a thickness of the second cap conductor film is in a range of 2 to 20 nm.
7 . 請求項 1記載の半導体装置において、  7. The semiconductor device according to claim 1,
前記第 1導体膜の上面は前記第 1絶縁膜の上面よりも低く、 前記第 1キャップ 導体膜の上面と前記第 1絶縁膜の上面とが略平面であることを特徴とする半導体 A semiconductor, wherein an upper surface of the first conductive film is lower than an upper surface of the first insulating film, and an upper surface of the first cap conductive film and an upper surface of the first insulating film are substantially flat;
8 . 請求項 1記載の半導体装置において、 8. The semiconductor device according to claim 1,
前記第 2絶縁膜は、 前記第 1絶縁膜および前記第 1キヤップ導体膜上に形成さ れたパリァ絶縁膜とその上に形成された層間絶縁膜とを含む複数の絶縁膜からな ることを特徴とする半導体装置。  The second insulating film includes a plurality of insulating films including a first insulating film, a parer insulating film formed on the first cap conductor film, and an interlayer insulating film formed thereon. Characteristic semiconductor device.
9 . 請求項 1記載の半導体装置において、  9. The semiconductor device according to claim 1,
前記第 1および第 2バリア導体膜は、 高融点金属膜または高融点金属合金膜の 単体膜または積層膜からなることを特徴とする半導体装置。  A semiconductor device, wherein the first and second barrier conductor films are formed of a single film or a laminated film of a high melting point metal film or a high melting point metal alloy film.
1 0 . 請求項 1記載の半導体装置において、  10. The semiconductor device according to claim 1,
前記第 2開口部は、 前記第 2絶縁膜に形成された配線溝と、 前記配線溝の底部 から前記第 1キヤップ導体膜を貫通して前記第 1導体膜に到達するビアとを有し、 前記ビアの底部で露出する前記第 1導体膜上に前記第 2キヤップ導体膜が形成 され、  The second opening has a wiring groove formed in the second insulating film, and a via extending from the bottom of the wiring groove to the first conductive film through the first cap conductive film, The second cap conductor film is formed on the first conductor film exposed at the bottom of the via,
前記ビアの底部の前記第 2キャップ導体膜上と前記ビアの側壁および前記配線 溝の底部および側壁上に前記第 2パリァ導体膜が形成され、  The second pariconductor film is formed on the second cap conductor film at the bottom of the via, on the side wall of the via and on the bottom and the side wall of the wiring groove,
前記ビアおよび前記配線溝内を埋めるように前記第 2パリァ導体膜上に前記第 2導体膜が形成されていることを特徴とする半導体装置。  2. The semiconductor device according to claim 1, wherein the second conductor film is formed on the second barrier conductor film so as to fill the via and the wiring groove.
1 1 . 請求項 1記載の半導体装置において、  11. The semiconductor device according to claim 1,
前記半導体基板上の前記第 1絶縁膜より上層に位置し、 第 3開口部を有する第 A third opening located above the first insulating film on the semiconductor substrate and having a third opening;
3絶縁膜と、 3 insulating film,
前記第 3開口部の側壁および底部上に形成された第 3パリア導体膜と、 前記第 3開口部内を埋めるように前記第 3パリァ導体膜上に形成された銅を主成分とす る第 3導体膜とを有する第 2配線と、 A third barrier conductor film formed on a side wall and a bottom of the third opening; (3) a second wiring having a third conductor film containing copper as a main component and formed on the third conductor film so as to fill the opening;
前記第 3導体膜上に形成された第 3キヤップ導体膜と、  A third cap conductor film formed on the third conductor film,
前記第 3絶縁膜および前記第 3キヤップ導体膜上に形成された第 4絶縁膜と、 前記第 4絶縁膜に形成され、 その底部で前記第 3導体膜を露出する第 4開口部 と、  A fourth insulating film formed on the third insulating film and the third cap conductive film, and a fourth opening formed on the fourth insulating film and exposing the third conductive film at a bottom thereof;
前記第 4開口部の側壁および底部上に形成された第 4パリァ導体膜と、 前記第 4開口部内を埋めるように前記第 4パリア導体膜上に形成された銅を主 成分とする第 4導体膜と、  A fourth conductor film formed on the side wall and the bottom of the fourth opening, and a fourth conductor mainly composed of copper formed on the fourth barrier conductor film so as to fill the fourth opening. A membrane,
を前記第 1配線よりも上層の配線層で有することを特徴とする半導体装置。  In a wiring layer above the first wiring.
1 2 . 請求項 1記載の半導体装置において、  12. The semiconductor device according to claim 1,
前記半導体基板上の前記第 1絶縁膜より上層に位置し、 第 3開口部を有する第 3絶縁膜と、  A third insulating film that is located above the first insulating film on the semiconductor substrate and has a third opening;
前記第 3開口部の側壁および底部上に形成された第 3パリァ導体膜と、 前記第 3開口部内を埋めるように前記第 3パリア導体膜上に形成された銅を主成分とす る第 3導体膜とを有する第 2配線と、  A third pariconductor film formed on the side wall and the bottom of the third opening, and a third mainly composed of copper formed on the third pariconductor film so as to fill the third opening. A second wiring having a conductive film;
前記第 3絶縁膜および前記第 3配線上に形成された第 4絶縁膜と、  A fourth insulating film formed on the third insulating film and the third wiring,
前記第 4絶縁膜に形成され、 その底部で前記第 3導体膜を露出する第 4開口部 と、  A fourth opening formed in the fourth insulating film and exposing the third conductive film at a bottom thereof;
前記第 4開口部の側壁および底部上に形成された第 4パリア導体膜と、 前記第 4開口部内を埋めるように前記第 4パリァ導体膜上に形成された銅を主 成分とする第 4導体膜と、  A fourth conductor film formed on the side wall and the bottom of the fourth opening, and a fourth conductor mainly composed of copper formed on the fourth conductor film so as to fill the fourth opening. A membrane,
を前記第 1配線よりも上層の配線層で有することを特徴とする半導体装置。  In a wiring layer above the first wiring.
1 3 . 請求項 1記載の半導体装置において、  13. The semiconductor device according to claim 1,
前記半導体基板上の前記第 1絶縁膜より上層に位置し、 第 3開口部を有する第 3絶縁膜と、  A third insulating film that is located above the first insulating film on the semiconductor substrate and has a third opening;
前記第 3開口部の側壁および底部上に形成された第 3パリァ導体膜と、 前記第 3開口部内を埋めるように前記第 3パリァ導体膜上に形成された銅を主成分とす る第 3導体膜とを有する第 2配線と、 前記第 3導体膜上に形成された第 3キヤップ導体膜と、 A third pariconductor film formed on the side wall and the bottom of the third opening, and a third chiefly composed of copper formed on the third pariconductor film so as to fill the third opening. A second wiring having a conductive film; A third cap conductor film formed on the third conductor film,
前記第 3絶縁膜および前記第 3キヤップ導体膜上に形成された第 4絶縁膜と、 前記第 4絶縁膜に形成され、 その底部で前記第 3導体膜を露出する第 4開口部 と、  A fourth insulating film formed on the third insulating film and the third cap conductive film, and a fourth opening formed on the fourth insulating film and exposing the third conductive film at a bottom thereof;
前記第 4開口部の底部で露出する前記第 3配線に電気的に接続され、 アルミ二 ゥムを主成分とする第 4導体膜を有する第 3配線と、  A third wiring electrically connected to the third wiring exposed at the bottom of the fourth opening, the third wiring having a fourth conductive film mainly composed of aluminum;
を前記第 1配線よりも上層の配線層で有することを特徴とする半導体装置。  In a wiring layer above the first wiring.
1 4 . 半導体基板と、 1 4. The semiconductor substrate,
前記半導体基板上に形成された第 1絶縁膜と、  A first insulating film formed on the semiconductor substrate,
前記第 1絶縁膜に形成された第 1開口部と、  A first opening formed in the first insulating film,
前記第 1開口部の側壁および底部上に形成された第 1パリァ導体膜と、 前記第 1開口部内を埋めるように前記第 1パリァ導体膜上に形成された銅を主成分とす る第 1導体膜とを有する第 1配線と、  A first pariconductor film formed on the side wall and the bottom of the first opening, and a first parallax film mainly composed of copper formed on the first pariconductor film so as to fill the first opening. A first wiring having a conductive film;
前記第 1導体膜上に形成された第 1キヤップ導体膜と、  A first cap conductive film formed on the first conductive film,
前記第 1絶縁膜および前記第 1キヤップ導体膜上に形成された第 2絶縁膜と、 • 前記第 2絶縁膜に形成され、 その底部で前記第 1キャップ導体膜の一部を貫通 して前記第 1導体膜を露出する第 2開口部と、  A second insulating film formed on the first insulating film and the first cap conductive film; and a second insulating film formed on the second insulating film, the bottom portion of which passes through a part of the first cap conductive film. A second opening exposing the first conductive film,
前記第 2開口部の底部で露出する前記第 1導体膜上に形成され前記第 1キヤッ プ導体膜につながる第 2キヤップ導体膜と、  A second cap conductor film formed on the first conductor film exposed at the bottom of the second opening and connected to the first cap conductor film;
前記第 2開口部の側壁上と底部の前記第 2キヤップ導体膜上に形成された第 2 パリア導体膜と、  A second barrier conductor film formed on the side wall of the second opening and on the second cap conductor film at the bottom;
前記第 2開口部内を埋めるように前記第 2パリァ導体膜上に形成された鲖を主 成分とする第 2導体膜と、  A second conductor film having 鲖 as a main component formed on the second parier conductor film so as to fill the second opening;
を有することを特徴とする半導体装置。  A semiconductor device comprising:
1 5 . 請求項 1 4記載の半導体装置において、 15. The semiconductor device according to claim 14,
前記第 1開口部内の前記第 1導体膜の上面は前記第 1絶縁膜の上面よりも低く 形成されていることを特徴とする半導体装置。  A semiconductor device, wherein an upper surface of the first conductor film in the first opening is formed lower than an upper surface of the first insulating film.
1 6 . 請求項 1 4記載の半導体装置において、  16. The semiconductor device according to claim 14, wherein
前記第 2絶縁膜は、 前記第 1絶縁膜および前記第 1キャップ導体膜上に形成さ れたパリア絶縁膜とその上に形成された層間絶縁膜とで形成され、 前記第 2開口 部は前記層間絶縁膜と前記パリァ絶縁膜と前記第 1キャップ導体膜を貫通して前 記第 1導体膜を露出していることを特徴とする半導体装置。 The second insulating film is formed on the first insulating film and the first cap conductor film. The second opening is formed by penetrating the interlayer insulating film, the barrier insulating film, and the first cap conductor film. A semiconductor device having a conductive film exposed.
1 7 . 半導体基板と、  1 7. Semiconductor substrate,
前記半導体基板上に形成された第 1絶縁膜と、  A first insulating film formed on the semiconductor substrate,
前記第 1絶縁膜に形成された第 1開口部と、  A first opening formed in the first insulating film,
前記第 1開口部の側壁および底部上に形成された第 1パリア導体膜と、 前記第 1開口部内を埋めるように前記第 1パリア導体膜上に形成された銅を主成分とす る第 1導体膜とを有する第 1配線と、  A first barrier conductor film formed on a side wall and a bottom of the first opening; and a first principal component containing copper formed on the first barrier conductor film to fill the first opening. A first wiring having a conductive film;
前記第 1導体膜上に形成された第 1キャップ導体膜と、 ■  A first cap conductor film formed on the first conductor film;
前記第 1絶縁膜および前記第 1キヤップ導体膜上に形成されたパリァ絶縁膜と、 前記パリァ絶縁膜上に形成された第 2絶縁膜と、  A parier insulating film formed on the first insulating film and the first cap conductor film; a second insulating film formed on the parier insulating film;
前記第 2絶縁膜の途中の深さまで形成された配線溝部分と、 前記配線溝部分の 底部から前記第 2絶縁膜とパリア絶縁膜と前記第 1キャップ導体膜の一部を貫通 して前記第 1導体膜に到達するビアとカゝらなる第 2開口部と、  A wiring groove portion formed to an intermediate depth of the second insulating film; and a second groove extending through a part of the second insulating film, the barrier insulating film, and the first cap conductor film from the bottom of the wiring groove portion. (1) a via and a second opening reaching the conductive film,
前記ビアの底部で露出する前記第 1導体膜上に形成され前記第 1キヤップ導体 膜につながる第 2キヤップ導体膜と、  A second cap conductor film formed on the first conductor film exposed at the bottom of the via and connected to the first cap conductor film;
前記ビァの底部の前記第 2キヤップ導体膜上と前記ビァの側壁および前記配線 溝部分の底部および側壁上に形成された第 2パリァ導体膜と、  A second parier conductor film formed on the bottom of the via on the second cap conductor film and on the side wall of the via and on the bottom and side wall of the wiring groove portion;
前記ビアおよび前記配線溝部分を埋めるように前記第 2パリァ導体膜上に形成 された銅を主成分とする第 2導体膜と、  A second conductor film containing copper as a main component formed on the second conductor film so as to fill the via and the wiring groove portion;
を有することを特徴とする半導体装置。  A semiconductor device comprising:
1 8 . 請求項 1 7記載の半導体装置において、  18. The semiconductor device according to claim 17,
前記第 1開口部内の前記第 1導体膜の上面は前記第 1絶縁膜の上面よりも低く 形成されていることを特徴とする半導体装置。  A semiconductor device, wherein an upper surface of the first conductor film in the first opening is formed lower than an upper surface of the first insulating film.
1 9 . 請求項 1 7記載の半導体装置において、  19. The semiconductor device according to claim 17,
前記第 1キャップ導体膜は、 タングステン、 タングステン合金、 コバルト、 コ パルト合金、二ッケルまたは二ッケル合金からなることを特徴とする半導体装置。  The semiconductor device, wherein the first cap conductor film is made of tungsten, a tungsten alloy, cobalt, a cobalt alloy, nickel, or a nickel alloy.
2 0 . 請求項 1 7記載の半導体装置において、 前記第 1キヤップ導体膜の膜厚は、 2〜 2 0 n mの範囲内であることを特徴と する半導体装置。 20. The semiconductor device according to claim 17, The semiconductor device according to claim 1, wherein a thickness of the first cap conductor film is in a range of 2 to 20 nm.
PCT/JP2004/012448 2003-10-20 2004-08-24 Semiconductor device WO2005038904A1 (en)

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