TW200515533A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- TW200515533A TW200515533A TW093118203A TW93118203A TW200515533A TW 200515533 A TW200515533 A TW 200515533A TW 093118203 A TW093118203 A TW 093118203A TW 93118203 A TW93118203 A TW 93118203A TW 200515533 A TW200515533 A TW 200515533A
- Authority
- TW
- Taiwan
- Prior art keywords
- film
- wiring
- main conductive
- conductive film
- wiring groove
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76865—Selective removal of parts of the layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
Abstract
The objective of the present invention is to increase the reliability of a semiconductor device with a buried copper wiring. A wiring groove is formed in insulating films (14, 15). A conductive barrier film (18) and a copper main conductive film (19) are formed on the insulating film (15) including the bottom and side wall of the wiring groove. The unnecessary part is removed by a CMP method to form a wiring (20). Besides, a metal cap film (22) composed of tungsten is selectively growth on the main conductive film (19). Insulating films (23 to 26) are formed on the insulting film (15) where the wiring (20) is buried. The via (30) penetrates through the metal cap film (22) so that the main conductive film (19) is exposed to form the via and a wiring groove (31). After a metal cap film (32) composed of tungsten is selectively grown on the main conductive film (19) exposed at the bottom of the via (30) by selective growing, a conductive barrier film (33) and a copper main conductive film (34) are formed on the insulting film (26) including the inner portions of the via (30) and the wiring groove (31). The unnecessary part is removed by a CMP method to form a wiring (35).
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003359673A JP2007042662A (en) | 2003-10-20 | 2003-10-20 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
TW200515533A true TW200515533A (en) | 2005-05-01 |
Family
ID=34463345
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW093118203A TW200515533A (en) | 2003-10-20 | 2004-06-24 | Semiconductor device |
Country Status (3)
Country | Link |
---|---|
JP (1) | JP2007042662A (en) |
TW (1) | TW200515533A (en) |
WO (1) | WO2005038904A1 (en) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
MY171542A (en) * | 2006-08-30 | 2019-10-17 | Lam Res Corp | Processes and integrated systems for engineering a substrate surface for metal deposition |
JP5305599B2 (en) * | 2007-02-19 | 2013-10-02 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
JP2008294211A (en) | 2007-05-24 | 2008-12-04 | Toshiba Corp | Semiconductor device, and manufacturing method thereof |
KR100824637B1 (en) * | 2007-06-26 | 2008-04-25 | 주식회사 동부하이텍 | Nor flash device and method for fabricating the device |
US7777266B2 (en) * | 2007-11-29 | 2010-08-17 | Qimonda Ag | Conductive line comprising a capping layer |
DE102008021568B3 (en) * | 2008-04-30 | 2010-02-04 | Advanced Micro Devices, Inc., Sunnyvale | A method of reducing erosion of a metal cap layer during via formation in semiconductor devices and semiconductor device with a protective material for reducing erosion of the metal cap layer |
JP2010050190A (en) * | 2008-08-20 | 2010-03-04 | Renesas Technology Corp | Method of manufacturing semiconductor device, and semiconductor device |
US8237191B2 (en) * | 2009-08-11 | 2012-08-07 | International Business Machines Corporation | Heterojunction bipolar transistors and methods of manufacture |
KR102047354B1 (en) | 2010-02-26 | 2019-11-21 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device |
US8940635B1 (en) * | 2013-08-30 | 2015-01-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for forming interconnect structure |
SG11201703033RA (en) * | 2014-10-17 | 2017-05-30 | Acm Res Shanghai Inc | Barrier layer removal method and semiconductor structure forming method |
JP2017069313A (en) * | 2015-09-29 | 2017-04-06 | 株式会社日立国際電気 | Method for manufacturing semiconductor device, apparatus for processing substrate, gas-supply system and program |
WO2017113932A1 (en) * | 2015-12-29 | 2017-07-06 | 苏州晶方半导体科技股份有限公司 | Solder pad, semiconductor chip comprising solder pad, and forming method therefor |
CN107564850B (en) * | 2016-07-01 | 2020-07-07 | 中芯国际集成电路制造(北京)有限公司 | Interconnect structure and method of making the same |
KR102582671B1 (en) | 2016-12-22 | 2023-09-25 | 삼성전자주식회사 | Semiconductor devices |
US20230154829A1 (en) * | 2021-11-18 | 2023-05-18 | Qualcomm Incorporated | Recess structure for padless stack via |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11135506A (en) * | 1997-10-31 | 1999-05-21 | Nec Corp | Manufacture of semiconductor device |
US6870263B1 (en) * | 1998-03-31 | 2005-03-22 | Infineon Technologies Ag | Device interconnection |
JP2001319928A (en) * | 2000-05-08 | 2001-11-16 | Hitachi Ltd | Semiconductor integrated circuit device and manufacturing method therefor |
JP2002064138A (en) * | 2000-08-18 | 2002-02-28 | Hitachi Ltd | Semiconductor integrated circuit device and method of manufacturing the same |
JP2003068848A (en) * | 2001-08-29 | 2003-03-07 | Fujitsu Ltd | Semiconductor device and its manufacturing method |
-
2003
- 2003-10-20 JP JP2003359673A patent/JP2007042662A/en active Pending
-
2004
- 2004-06-24 TW TW093118203A patent/TW200515533A/en unknown
- 2004-08-24 WO PCT/JP2004/012448 patent/WO2005038904A1/en not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
WO2005038904A1 (en) | 2005-04-28 |
JP2007042662A (en) | 2007-02-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW200515533A (en) | Semiconductor device | |
TWI268595B (en) | Damascene structure and process at semiconductor substrate level | |
TW377502B (en) | Method of dual damascene | |
TW200605202A (en) | Semiconductor device having copper wiring and its manufacture method | |
SG84587A1 (en) | Semiconductor device and method of formation | |
EP1796176A3 (en) | Field-effect transistor with via electrode and manufacturing method of the same | |
EP1351291A3 (en) | Copper doped transition layer for improving copper interconnection reliability | |
TW200511493A (en) | Method for forming a dielectric barrier in an integrated circuit structure, interconnect structure and semiconductor device and methods for making the same | |
TWI267132B (en) | Semiconductor device and manufacturing method of the same | |
EP1353370A3 (en) | Semiconductor memory capacitor and method for fabricating the same | |
TW200603331A (en) | Method of manufacturing a semiconductor device | |
CN101930965A (en) | The electric network composition and the manufacture method thereof that are used for semiconductor device | |
TW200623324A (en) | Semiconductor device and its manufacturing method | |
TW200707646A (en) | Semiconductor device and a method of manufacturing the same | |
TW200507108A (en) | Semiconductor device and method for manufacturing the same | |
TW200518263A (en) | Method for fabricating copper interconnects | |
TW200524070A (en) | Metal contact structure and method of manufacture | |
SG143975A1 (en) | Method of manufacturing a semiconductor device | |
TW200725802A (en) | Improved interconnect structure and method of fabricating same | |
SG125113A1 (en) | A method to form shallow junction transistors while eliminating shorts due to juction spiking | |
SG128555A1 (en) | Integrated circuit system using dual damascene process | |
TW200620533A (en) | Semiconductor device and fabrication method thereof | |
TW200518265A (en) | Copper damascene structure and semiconductor device including the structure and method of fabricating the same | |
EP1296368A3 (en) | Semiconductor device including porous insulating material and manufacturing method thereof | |
EP1168433A3 (en) | A method of manufacturing a wiring structure in a semiconductor device |