JP2004063980A - Semiconductor device manufacturing method, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the reliability of each embedded wiring including a main conductor film having Cu as its main component. <P>SOLUTION: There are provided a process for forming each wiring groove in an insulation film 25 on a semiconductor substrate, a process for forming a conductive barrier film 27 on the insulation film 25 inclusive of on the bottom surface and the side surfaces of each wiring groove, a process for forming a seed film on the conductive barrier film 27, a process for forming a main conductor film 29 having Cu as its main component on the seed film by a plating method, a process for so performing thereafter a first heat treatment at a temperature not lower than 400 °C as to grow the crystal grains of the main conductor film 29, a process for forming each wiring 40 by removing the unwanted conductive barrier film 27, seed film, and main conductor film 29 which are present on the insulation film 25, and by leaving the conductive barrier film 27, seed film, and main conductor film 29 in each wiring groove. A process for so performing a second heat treatment at a temperature range of 100-250 °C to make the stress included in each wiring 40 relax, by performing the second heat treatment at a lower temperature than the first heat treatment, and a process for forming an insulation film 41 on the insulation film 25 of the wirings 40 being embedded therein follow. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device manufacturing technology and a semiconductor device, and more particularly to a semiconductor device manufacturing technology having a buried interconnect including a main conductor film containing copper as a main component and a technology effective when applied to a semiconductor device.
[0002]
[Prior art]
The elements of the semiconductor device are connected by, for example, a multilayer wiring structure to form a circuit. With the miniaturization, a buried wiring structure has been developed as a wiring structure. The buried wiring structure is, for example, a damascene technology (single-damascene technology and dual-damascene technology) in a wiring opening such as a wiring groove or a hole formed in an insulating film. Is formed by embedding a wiring material.
[0003]
For example, a buried wiring is formed in the groove of the insulating film by depositing a metal film by a plating method so as to fill the groove of the insulating film, and polishing the metal film by a CMP (Chemical Mechanical Polishing) method or the like. You. After depositing the metal film by plating, annealing is performed. Japanese Patent Application Laid-Open No. 2001-160590 describes a technique of annealing at a temperature in the range of 80 to 200 ° C. immediately after depositing a metal film by a plating method.
[0004]
[Problems to be solved by the invention]
According to the study of the present inventor, if an annealing process is performed after forming a metal film containing copper as a main component, the adhesive strength between the wiring groove and the wiring decreases due to a rapid temperature change during annealing. I knew it was afraid. This leads to a decrease in the reliability of the embedded wiring, which causes a reduction in the manufacturing yield of the semiconductor device and an increase in the manufacturing cost.
[0005]
An object of the present invention is to provide a method of manufacturing a semiconductor device and a semiconductor device capable of improving the reliability of a wiring including a main conductor film containing copper as a main component.
[0006]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0007]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0008]
In the method of manufacturing a semiconductor device according to the present invention, a first heat treatment is performed at a temperature of 400 ° C. or more after forming a main conductor film mainly containing copper for forming an embedded wiring, The second heat treatment is performed at this temperature.
[0009]
Further, in the method of manufacturing a semiconductor device according to the present invention, after forming a main conductor film mainly containing copper for forming an embedded wiring, a first heat treatment is performed at a first temperature to reduce the stress of the first conductor film. The second heat treatment is performed at a second temperature lower than the first temperature so as to relax the temperature.
[0010]
Further, in the method of manufacturing a semiconductor device according to the present invention, after forming a main conductor film mainly containing copper for forming an embedded wiring, the first temperature is increased at a first temperature so as to grow crystal grains of the first conductor film. The first heat treatment is performed, and the second heat treatment is performed at a second temperature lower than the first temperature so as to relax the stress of the first conductor film.
[0011]
In addition, the semiconductor device of the present invention is characterized in that the adhesive strength between the copper-based conductor film of the lower wiring and the conductive barrier film of the lower wiring, the copper-based conductor film of the lower wiring and the lower wiring are formed on the lower wiring. Of the lower layer wiring of the conductive film mainly composed of copper and the lower layer wiring of the conductive barrier film of the upper layer wiring. The adhesion between the film and the conductive barrier film of the upper wiring is not minimum.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless it is particularly necessary.
[0013]
(Embodiment 1)
First, the degradation phenomenon of an embedded wiring (embedded copper wiring) having a main conductor film containing copper as a main component, studied by the present inventors, will be described. FIG. 1 is a graph showing a resistance increase rate of a buried copper wiring formed by a conventional technique after a high-temperature storage test (for example, left at 150 ° C. for 100 hours). The horizontal axis of the graph of FIG. 1 corresponds to the rate of increase in the electrical resistance of the embedded copper wiring after the high-temperature storage test (the rate of increase in electrical resistance based on the electrical resistance before the high-temperature storage test). The vertical axis corresponds to cumulative distribution or cumulative probability (Cumulative Probability). FIG. 2 is a cross-sectional view schematically showing a result of a TEM (Transmission Electron Microscope) observation of a cross section of the buried copper wiring having an increased electric resistance after the high-temperature storage test and having a high resistance.
[0014]
As can be seen from FIG. 1, the electrical resistance of the buried copper wiring is increased by leaving it at a high temperature. At this time, as shown in FIG. 2, the upper surface of the wiring (lower buried copper wiring) 1 and the via portion (via buried portion) of the upper wiring (upper buried copper wiring) embedded in the interlayer insulating film 2. 3, a void or void 4 is formed. For this reason, the connection area between the lower wiring and the upper wiring is reduced, and the electrical resistance is increased as shown in FIG. Further, the formation of the voids 4 may cause disconnection between the lower wiring and the upper wiring. This reduces the manufacturing yield of the semiconductor device and increases the manufacturing cost.
[0015]
According to the study of the present inventor, when heat treatment (annealing treatment) is performed after the plating step of forming the main conductor film (copper film) of the buried copper wiring, the tensile deformation due to the elastic deformation (heat shrinkage) at the time of the temperature decrease in the heat treatment. Stress (contraction direction) remains or remains in the buried copper wiring. FIG. 3 is a cross-sectional view for explaining a state in which a buried copper wiring is formed while a stress remains. In FIG. 3, a wiring (buried copper wiring) 6 is formed in the interlayer insulating film 5, and the wiring 6 is connected to a via part (via buried part) 7 of an upper wiring (upper buried copper wiring). When the wiring 6 is formed on the interlayer insulating film 5, as schematically shown in FIG. 3, a tensile stress (contraction direction) as schematically shown by an arrow remains in the completed wiring 6. become. The semiconductor substrate or the semiconductor device on which the wiring 6 in which such stress remains is formed is left in a temperature region where the copper diffusion coefficient becomes relatively high and a tensile stress is generated in the copper wiring (high temperature storage). As a result, the stress in the wiring 6 is relaxed, and a void is generated between the wiring 1 (6) and the bottom of the via portion 3 (7) of the upper wiring, as shown in FIG. Causes an increase in wiring resistance as shown in FIG.
[0016]
FIG. 4 is a graph showing the relationship between the temperature at which the high-temperature storage test was performed and the rate of occurrence of resistance rise in the wiring. The horizontal axis of the graph of FIG. 4 corresponds to the temperature of the high-temperature storage test performed, and the vertical axis of the graph of FIG. Corresponds to the percentage of samples with increased resistance. It can be seen that when the temperature in the high-temperature storage test is 100 ° C. to 250 ° C., a rise in resistance occurs.
[0017]
Therefore, the present inventor has studied to suppress the phenomenon that the resistance of the copper wiring is increased (increased) by such a high temperature storage (test).
[0018]
The manufacturing process of the semiconductor device according to the present embodiment will be described with reference to the drawings. FIG. 5 is a fragmentary cross-sectional view of a semiconductor device according to an embodiment of the present invention, for example, a MISFET (Metal Insulator Semiconductor Effect Transistor) during a manufacturing process.
[0019]
As shown in FIG. 5, an element isolation region 12 is formed on a main surface of a semiconductor substrate (semiconductor wafer) 11 made of, for example, p-type single crystal silicon having a specific resistance of about 1 to 10 Ωcm. The element isolation region 12 is made of silicon oxide or the like, and is formed by, for example, an STI (Shallow Trench Isolation) method or a LOCOS (Local Oxidation of Silicon) method.
[0020]
Next, a p-type well 13 is formed in a region of the semiconductor substrate 11 where an n-channel MISFET is to be formed. The p-type well 13 is formed by, for example, ion-implanting an impurity such as boron (B).
[0021]
Next, a gate insulating film 14 is formed on the surface of the p-type well 13. The gate insulating film 14 is made of, for example, a thin silicon oxide film, and can be formed by, for example, a thermal oxidation method.
[0022]
Next, a gate electrode 15 is formed on the gate insulating film 14 of the p-type well 13. For example, a polycrystalline silicon film is formed on the semiconductor substrate 11, phosphorus (P) or the like is ion-implanted into the polycrystalline silicon film to form a low-resistance n-type semiconductor film, and the polycrystalline silicon film is patterned by dry etching. Thereby, gate electrode 15 made of a polycrystalline silicon film can be formed.
[0023]
Then, impurities such as phosphorus are ion-implanted into regions on both sides of the gate electrode 15 of the p-type well 13 so that n ⁻ A type semiconductor region 16 is formed.
[0024]
Next, a sidewall spacer or sidewall 17 made of, for example, silicon oxide is formed on the sidewall of the gate electrode 15. The sidewall 17 can be formed, for example, by depositing a silicon oxide film on the semiconductor substrate 11 and anisotropically etching the silicon oxide film.
[0025]
After the formation of the side wall 17, n ⁺ The type semiconductor region 18 (source and drain) is formed by ion-implanting an impurity such as phosphorus into regions on both sides of the gate electrode 15 and the sidewall 17 of the p-type well 13. n ⁺ Type semiconductor region 18 has n ⁻ The impurity concentration is higher than that of the type semiconductor region 16.
[0026]
Next, the gate electrode 15 and n ⁺ The surface of the type semiconductor region 18 is exposed, and for example, a cobalt (Co) film is deposited and heat-treated, so that the gate electrode 15 and n ⁺ A silicide film 15a and a silicide film 18a are formed on the surface of the mold semiconductor region 18, respectively. This gives n ⁺ The diffusion resistance of the type semiconductor region 18 and the contact resistance can be reduced. After that, the unreacted cobalt film is removed.
[0027]
In this manner, an n-channel MISFET (Metal Insulator Semiconductor Field Effect Transistor) 19 is formed in the p-type well 13.
[0028]
Next, an insulating film 20 made of silicon nitride or the like and an insulating film 21 made of silicon oxide or the like are sequentially deposited on the semiconductor substrate 11. Then, the insulating film 21 and the insulating film 20 are sequentially dry-etched to obtain n ⁺ A contact hole 22 is formed above the type semiconductor region (source, drain) 18 or the like. At the bottom of the contact hole 22, a part of the main surface of the semiconductor substrate 11, for example, n ⁺ A part of the mold semiconductor region 18 and a part of the gate electrode 15 are exposed.
[0029]
Next, a plug 23 made of tungsten (W) or the like is formed in the contact hole 22. The plug 23 is formed, for example, by forming a titanium nitride film 23a as a barrier film on the insulating film 21 including the inside of the contact hole 22 and then contacting the tungsten film with the titanium nitride film 23a by a CVD (Chemical Vapor Deposition) method or the like. The hole 22 is formed so as to be filled, and the unnecessary tungsten film and the titanium nitride film 23a on the insulating film 21 can be removed by a CMP (Chemical Mechanical Polishing) method or an etch-back method.
[0030]
6 to 9 are cross-sectional views of main parts of the semiconductor device during the manufacturing process following FIG. 6 to 9, parts corresponding to the structure below the insulating film 21 in FIG. 5 are not shown in FIGS.
[0031]
First, as shown in FIG. 6, an insulating film (etching stopper film) 24 is formed on the insulating film 21 in which the plug 23 is embedded. The insulating film 24 is made of, for example, a silicon nitride film or a silicon carbide (SiC) film. When the insulating film 24 is formed by etching a groove or a hole for forming a wiring in an insulating film (interlayer insulating film) 25 in an upper layer, the insulating film 24 may damage the lower layer due to excessive digging or deteriorate processing dimensional accuracy. It is formed in order to avoid doing. That is, the insulating film 24 functions as an etching stopper when the insulating film (interlayer insulating film) 25 is etched. Then, an insulating film (interlayer insulating film) 25 is formed by sequentially depositing a silicon oxide film to which fluorine (F) is added and a silicon oxide film to which fluorine (F) is not added from the lower layer on the insulating film 24. I do. Note that the insulating film 25 may be formed only of a silicon oxide film to which fluorine is not added. Further, by adding fluorine, the dielectric constant of the insulating film 25 can be reduced, so that the overall dielectric constant of the wiring of the semiconductor device can be reduced, and the wiring delay can be improved. Further, the insulating film 25 may be formed of an organic low dielectric constant material.
[0032]
Next, as shown in FIG. 7, a wiring opening, that is, a wiring groove 26 is formed by dry-etching the insulating films 25 and 24 using a photolithography method and an etching method. At this time, the upper surface of the plug 23 is exposed at the bottom of the wiring groove 26.
[0033]
Next, as shown in FIG. 8, a relatively thin conductive film having a thickness of about 50 nm made of a laminated film of, for example, a tantalum (Ta) film and a tantalum nitride (TaN) film is formed over the entire main surface of the substrate 11. A barrier film 27 is formed. The conductive barrier film 27 can be formed by a sputtering method, for example, long distance (long throw) sputtering using a DC magnetron sputtering apparatus. The conductive barrier film 27 has, for example, a function of suppressing or preventing the diffusion of copper for forming a main conductor film described later, a function of improving the wettability of copper when the main conductor film is reflowed, and the like. As a material of the conductive barrier film 27, a high melting point metal nitride such as tungsten nitride (WN) or titanium nitride (TiN), which hardly reacts with copper, may be used instead of tantalum or tantalum nitride. it can. As the material of the conductive barrier film 27, a material obtained by adding silicon (Si) to a high melting point metal nitride, tantalum (Ta), titanium (Ti), tungsten (W), titanium tungsten (T Refractory metals such as TiW) alloys can also be used. Further, as the conductive barrier film 27, not only a single film of the above material films but also a laminated film can be used.
[0034]
Next, a relatively thin seed film 28 made of a copper (Cu) film is formed on the entire surface of the semiconductor substrate 11 on which the conductive barrier film 27 is deposited, for example, by a sputtering method. Here, the seed film 28 is formed to improve the adhesion between the main conductor film 29 and the conductive barrier film 27. Then, as shown in FIG. 9, over the entire surface of the semiconductor substrate 11 on which the seed film 28 is deposited, a relatively thick main conductor film 29 having a thickness of about 800 to 1600 nm and containing copper as a main component is formed by wiring. It is formed so as to fill the groove 26. The main conductor film 29 can be formed using a plating method such as electrolytic plating or electroless plating. The main conductor film 29 can be formed of, for example, copper or a copper alloy (having Cu as a main component and containing, for example, Mg, Ag, Pd, Ti, Ta, Al, Nb, Zr, Zn, or the like).
[0035]
After the formation of the main conductor film 29, the semiconductor substrate 11 (in a non-oxidizing atmosphere such as a reducing atmosphere (for example, hydrogen atmosphere), an inert gas (for example, He gas or Ar gas) atmosphere, a nitrogen gas atmosphere, or a mixed gas atmosphere thereof). The first heat treatment (first annealing treatment) is performed on the main conductor film 29). Thereby, the (copper) crystal grains of the main conductor film 29 grow. The heat treatment temperature of the first heat treatment is preferably 400 ° C. or higher, more preferably 400 ° C. to 450 ° C. In this embodiment mode, hydrogen gas (H ₂ ) A heat treatment at 400 ° C. was performed for about 2 minutes in a 100% reduced pressure atmosphere. Here, by the first heat treatment, the main conductor film 29 and the seed film 28 are integrated and formed with good adhesion to the conductive barrier film 27. That is, when the main conductive film 29 is directly formed on the conductive barrier film 27 by the electrolytic plating method or the electroless plating method, the adhesion between the main conductive film 29 and the conductive barrier film 27 is poor, and the conductive barrier film 27 is easily peeled. However, after the seed film 28 is formed on the conductive barrier film 27, the main conductor film 29 is formed, and the first heat treatment is performed to improve the adhesion between the main conductor film 29 and the conductive barrier film 27. Can be made.
[0036]
FIG. 10 is a cross-sectional view showing a conceptual structure of a heat treatment apparatus (annealing apparatus) used in the present embodiment. The heat treatment apparatus 31 shown in FIG. 10 includes a processing chamber 32, a stage (mounting table) 33 supported by a support unit (not shown) in the processing chamber 32, and on which the semiconductor substrate (semiconductor wafer) 11 is mounted. A gas inlet port 34 is connected to a gas introduction unit (not shown) for introducing a desired gas into the processing chamber 32 at a desired flow rate, and is connected to a gas exhaust unit (not shown) to evacuate the processing chamber 32 to a desired exhaust speed. And a gas exhaust port 35 for exhausting gas. The stage 33 has a built-in heater for heating, and can heat the semiconductor substrate 11 disposed on the stage 33 at a desired temperature. In the present embodiment, for example, hydrogen gas is introduced from the gas introduction port 34, the exhaust speed from the gas exhaust port 35 is adjusted, the inside of the processing chamber 32 is reduced to a predetermined reduced pressure, and heated with a heater to 400 ° C. By arranging the semiconductor substrate 11 on the stage 33 thus completed, the first heat treatment can be performed. In this case, the semiconductor substrate 11 can be arranged on the stage 33 which has been heated in advance. However, the heating by the heater may be started after the semiconductor substrate 11 is arranged on the stage 33.
[0037]
Note that the first heat treatment can also be performed after a CMP step for the main conductor film 29 described later. Alternatively, the main conductor film 29 may be formed by a sputtering method without forming the seed film 28, and then the main conductor film 29 may be reflowed by the first heat treatment so that copper is buried in the wiring groove 26 without gaps. it can.
[0038]
11 to 19 are cross-sectional views of main parts in the manufacturing process of the semiconductor device following FIG. For simplicity of understanding, in FIGS. 11 to 19, similarly to FIGS. 6 to 9, parts corresponding to the structure below the insulating film 21 in FIG. 5 are omitted. In addition, since the main conductor film 29 and the seed film 28 are integrated by the first heat treatment, the seed film 28 is omitted and described as the main conductor film 29 to simplify the following description.
[0039]
As shown in FIG. 11, by removing unnecessary conductive barrier film 27 and main conductor film 29 on insulating film 25 and leaving conductive barrier film 27 and main conductor film 29 in wiring groove 26, wiring (First layer wiring) 40 is formed. At this time, unnecessary removal of the conductive barrier film 27 and the main conductor film 29 is performed by polishing using, for example, a CMP method. The wiring 40 is connected to the n ⁺ It is electrically connected to the type semiconductor region (source, drain) 18 and the gate electrode 15.
[0040]
Next, in a non-oxidizing atmosphere such as a reducing atmosphere (for example, a hydrogen atmosphere), an inert gas (for example, He gas or Ar gas) atmosphere, a nitrogen gas atmosphere, or a mixed gas atmosphere thereof, the semiconductor substrate 11 (the main conductor film 29 or The second heat treatment (second annealing process) is performed on the wiring 40). The second heat treatment is performed at a heat treatment temperature lower than the heat treatment temperature of the first heat treatment. Thereby, the stress remaining in the wiring 40 can be reduced or reduced. Further, the heat treatment temperature of the second heat treatment is more preferably 100 ° C. to 250 ° C. In this embodiment mode, hydrogen gas (H ₂ ) And nitrogen gas (hydrogen gas 1%) in a normal pressure atmosphere at 150 ° C. for about 90 minutes. In addition, by the second heat treatment, copper oxide (CuO, CuO) on the surface of the wiring 40 (main conductor film 29) oxidized by CMP. ₂ ) Can be reduced to copper (Cu). Note that the heat treatment apparatus 31 used in the first heat treatment can be used for the second heat treatment.
[0041]
In the present embodiment, the second heat treatment is performed after the CMP step of the main conductor film 29 or the like, but the second heat treatment may be performed before the CMP step of the main conductor film 29 or the like. In this case, after the CMP process, a reduction treatment of the upper surface of the wiring 40 may be separately performed. Note that the second heat treatment is performed at a lower temperature than the first heat treatment after the first heat treatment and before the upper surface of the wiring 40 is covered with a material film (such as an insulating film 41 described later). Should.
[0042]
Next, as shown in FIG. 12, an insulating film (barrier insulating film) 41 is formed on the insulating film 25 in which the wiring 40 is embedded. Then, as shown in FIG. 13, an insulating film (interlayer insulating film) 42, an insulating film (etching stopper film) 43, and an insulating film (interlayer insulating film) 44 are formed on the insulating film. The insulating film 41 is made of, for example, a silicon carbonitride (SiCN) film and functions as a barrier insulating film for copper wiring. Therefore, the insulating film 41 suppresses or prevents copper in the main conductor film 29 of the wiring 40 from diffusing into the insulating film 42. The insulating film 42 can be formed using a material similar to that of the insulating film 25. The insulating films 43 and 44 can be formed using the same material as the insulating films 24 and 25.
[0043]
Next, as shown in FIG. 14, the insulating films 41 to 44 are dry-etched by using a photolithography method or the like to form a wiring opening, that is, a through-hole or via 45 reaching the wiring 40 and a wiring. A groove 46 is formed. At this time, the upper surface of the wiring 40 is exposed at the bottom of the via 45.
[0044]
Next, a process of removing the copper oxide formed on the surface of the wiring 40 (lower-layer copper wiring) exposed at the bottom of the via 45 and cleaning the exposed upper surface of the wiring 40 is performed. This can be performed by, for example, an etching process using argon (Ar) plasma.
[0045]
Next, as shown in FIG. 15, a relatively thin conductive film having a thickness of about 50 nm made of a laminated film of, for example, a tantalum (Ta) film and a tantalum nitride (TaN) film is formed over the entire main surface of the semiconductor substrate 11. The conductive barrier film 47 is formed using a sputtering method or the like. The conductive barrier film 47 has a function similar to that of the conductive barrier film 27, for example, a function of suppressing or preventing the diffusion of copper, and can be formed of the same material as the conductive barrier film 27.
[0046]
Next, a relatively thin seed film 48 made of a copper (Cu) film is formed on the entire surface of the semiconductor substrate 11 on which the conductive barrier film 47 is deposited. Then, as shown in FIG. 16, over the entire surface of the semiconductor substrate 11 on which the seed film 48 has been deposited, a relatively thick main conductor film 49 containing copper as a main component, for example, having a thickness of about 800 to 1600 nm, is formed. 45 and the wiring groove 46 are formed. The main conductor film 49 can be formed by using a plating method such as electrolytic plating or electroless plating, for example, and can be formed of, for example, copper or a copper alloy like the main conductor film 29.
[0047]
After the formation of the main conductor film 49, the semiconductor substrate 11 (in a non-oxidizing atmosphere such as a reducing atmosphere (for example, hydrogen atmosphere), an inert gas (for example, He gas or Ar gas) atmosphere, a nitrogen gas atmosphere, or a mixed gas atmosphere thereof). The first heat treatment (first annealing treatment) is performed on the main conductor film 49). Thereby, the (copper) crystal grains of the main conductor film 49 grow. The heat treatment temperature of the first heat treatment is preferably 400 ° C. or higher, more preferably 400 ° C. to 450 ° C. In this embodiment mode, hydrogen gas (H ₂ ) A heat treatment at 400 ° C. was performed for about 2 minutes in a 100% reduced pressure atmosphere. Here, by the first heat treatment, the main conductor film 29 and the seed film 28 are integrated and formed with good adhesion to the conductive barrier film 27. The first heat treatment for the main conductor film 49 can be performed using the heat treatment device 31 in the same manner as the first heat treatment for the main conductor film 29. Note that the first heat treatment can also be performed after a CMP process for the main conductor film 49 described below. Further, the main conductor film 49 is formed by a sputtering method without forming the seed film 48, and then the main conductor film 49 is reflowed by the first heat treatment, so that copper is left inside the via 45 and the wiring groove 46 without any gap. Can be embedded.
[0048]
Next, as shown in FIG. 17, unnecessary conductive barrier film 47 and main conductive film 49 on insulating film 44 are removed, and conductive barrier film 47 and main conductive film 49 are formed in via 45 and wiring groove 46. Are left, a wiring (second-layer wiring) 50 is formed. At this time, the unnecessary portions of the conductive barrier film 47 and the main conductor film 49 are removed by polishing using, for example, a CMP method. The wiring 50 is electrically connected to the wiring 40 via the conductive barrier film 47 and the main conductor film 49 (that is, the via portion of the wiring 50) embedded in the via 45. Here, since the seed film 48 is integrated with the main conductor film 49 by the above-described first heat treatment, the seed film 48 is omitted and described as the main conductor film 49 to simplify the description. .
[0049]
Next, in a non-oxidizing atmosphere such as a reducing atmosphere (for example, a hydrogen atmosphere), an inert gas (for example, He gas or Ar gas) atmosphere, a nitrogen gas atmosphere, or a mixed gas atmosphere thereof, the semiconductor substrate 11 (the main conductor film 49 or A second heat treatment (second annealing process) is performed on the wiring 50). The second heat treatment is performed at a heat treatment temperature lower than the heat treatment temperature of the first heat treatment. Thereby, the stress remaining in the wiring 50 can be reduced or reduced. Further, the heat treatment temperature of the second heat treatment is more preferably 100 ° C. to 250 ° C. In this embodiment mode, hydrogen gas (H ₂ ) And nitrogen gas (hydrogen gas 1%) in a normal pressure atmosphere at 150 ° C. for about 90 minutes. Further, by the second heat treatment, copper oxide (CuO, CuO) on the surface of the wiring 50 (main conductor film 49) oxidized by CMP. ₂ ) Can be reduced to copper (Cu). The second heat treatment for the wiring 50 can be performed using the heat treatment apparatus 31 in the same manner as the second heat treatment for the wiring 40.
[0050]
In the present embodiment, the second heat treatment is performed after the CMP step of the main conductor film 49 or the like, but the second heat treatment may be performed before the CMP step of the main conductor film 49 or the like. In this case, after the CMP process, a reduction treatment of the upper surface of the wiring 50 may be separately performed. Note that the second heat treatment is performed at a lower temperature than the first heat treatment after the first heat treatment and before the upper surface of the wiring 50 is covered with a material film (such as an insulating film 51 described later). Should.
[0051]
Next, as shown in FIG. 18, an insulating film (barrier insulating film) 51 made of the same material as the insulating film 41 and having the same function is formed on the insulating film 44 in which the wiring 50 is embedded. Then, as shown in FIG. 19, an insulating film (interlayer insulating film) 52, an insulating film (etching stopper film) 53, and an insulating film ( An interlayer insulating film) 54 is formed. Then, similarly to the via 45 and the wiring groove 46, a via and a wiring groove reaching the wiring 50 are formed, and the wiring (third layer wiring) 55 that fills the via and the wiring groove and is electrically connected to the wiring 50. Is formed by a process similar to the process of forming the wiring 50. Then, an insulating film (barrier insulating film) 56 made of the same material as the insulating film 51 is formed on the insulating film 54 in which the wiring 55 is embedded.
[0052]
Further, if necessary, the same manufacturing process can be repeated to form an upper layer wiring after the fourth layer wiring, but illustration and description thereof are omitted here. Alternatively, an aluminum wiring made of a laminated film such as a titanium film, an aluminum (Al) alloy film, and a titanium nitride film may be formed as an upper wiring, and the aluminum wiring may be used as a bonding pad. The wiring (first layer wiring) 40 is a wiring made of tungsten, an aluminum alloy, or the like, and the wiring (second layer wiring) 50 is a copper wiring (single damascene wiring) formed in the same manner as the wiring 40 described above. The (third layer wiring) 55 may be a copper wiring (dual damascene wiring) formed in the same manner as the wiring 50 described above.
[0053]
FIG. 20 is a graph showing the rate of increase in resistance of the embedded copper wiring formed according to the present embodiment after the high-temperature storage test. The horizontal axis of the graph of FIG. 20 corresponds to the increase rate of the electrical resistance of the wiring after the high-temperature storage test (the increase rate of the electrical resistance based on the electrical resistance before the high-temperature storage test), and the vertical axis of the graph of FIG. Corresponds to the distribution or cumulative probability (Cumulative Probability). The high-temperature storage test performed was a storage test at 150 ° C. for 100 hours, and the rate of increase (increase) in resistance was calculated by comparing the electrical resistance of the wiring before and after the storage test. The graph of FIG. 20 shows the case where the first heat treatment (annealing) is performed at 400 ° C. for 2 minutes and the second heat treatment (annealing) is performed at 150 ° C. for 90 minutes as in the present embodiment (black circles in the graph). Not only), but also in the case of a comparative example in which both the first heat treatment and the second heat treatment were performed at 300 ° C. (the heat treatment time was 2 minutes) (shown by white circles in the graph). It has become.
[0054]
As can be seen from the graph of FIG. 20, by performing the heat treatment under the conditions as in the present embodiment, an increase in the resistance of the wiring after high-temperature storage (test) is suppressed.
[0055]
As described above, in the present embodiment, the first heat treatment is performed after forming the main conductor films (main conductor films 29 and 49) for forming the embedded copper wirings (wirings 40, 50 and 55). . The crystal grains of the main conductor film are relatively small immediately after being formed, but grow by the first heat treatment. For this reason, the grain size (grain size) of the crystal grains of the main conductor film (copper film) after the first heat treatment increases as the temperature of the first heat treatment increases. Since the stress of the buried copper wiring is generated via the grain boundary of the main conductor film, the stress relaxation in the wiring can be suppressed by increasing the grain size and reducing the grain boundary. For this reason, by performing the first heat treatment at a relatively high temperature to make the crystal grain size of the main conductor film relatively large, it is possible to prevent defects due to stress migration of the embedded copper wiring. Therefore, the heat treatment temperature of the first heat treatment is preferably 400 ° C. or more, and more preferably 400 ° C. to 450 ° C. However, if the heat treatment temperature of the first heat treatment is too high, there is a possibility that an adverse effect may be exerted on an interlayer insulating film and the like. The first heat treatment is performed in a non-oxidizing atmosphere such as a reducing atmosphere (eg, a hydrogen atmosphere), an inert gas (eg, a He gas or an Ar gas) atmosphere, a nitrogen gas atmosphere, or a mixed gas atmosphere thereof, that is, a reducing atmosphere. Alternatively, the reaction is preferably performed under an inert atmosphere at normal pressure (atmospheric pressure) or reduced pressure.
[0056]
When the temperature is lowered after the first heat treatment, the main conductor film thermally contracts, and a tensile stress (contraction direction) is generated in the main conductor film. When a material film (the insulating films 41 and 42 and the insulating films 51 and 52) covering the upper surface of the wiring is formed while the tensile stress remains or remains, the wiring is fixed with the remaining stress. When the residual stress of the wiring is relaxed later, the heat shrinkage component becomes a void, causing an open failure at the bottom of the via portion of the buried copper wiring, thereby increasing the wiring resistance. In this embodiment, the second heat treatment is performed after the first heat treatment and before the formation of the material films (barrier insulating films 41 and 51) covering the upper surface of the wiring, whereby the wiring (main conductor film) is formed. The stress remaining therein can be reduced or reduced. After that, by forming a barrier insulating film, an interlayer insulating film, and the like on the wiring, the wiring is fixed with little residual or residual stress. For this reason, a void does not occur at the bottom of the via portion of the buried copper wiring later to cause an open failure. Thereby, as shown in the graph of FIG. 20, it is possible to suppress an increase in the resistance of the wiring after being left at a high temperature. Therefore, the reliability of the wiring can be further improved, and the reliability of the semiconductor device can be further improved. Further, the production yield of the semiconductor device can be improved, and the production cost can be reduced.
[0057]
The second heat treatment is performed at a temperature lower than the first heat treatment temperature. However, if the second heat treatment is performed in a temperature range in which the copper diffusion coefficient increases to some extent and a tensile stress occurs in the wiring, the second heat treatment is performed during the second heat treatment. This is more preferable because the residual stress in the wiring is easily reduced. Therefore, the heat treatment temperature of the second heat treatment is more preferably 100 ° C to 250 ° C. As shown in the graph of FIG. 4, this temperature region corresponds to a temperature region where resistance rise is likely to occur when the semiconductor substrate or the semiconductor device on which the embedded copper wiring is formed is left at a high temperature.
[0058]
In the case of FIG. 4, the stress in the wiring was relaxed during the high-temperature storage test, voids were generated between the wirings, and the resistance of the wiring increased. However, in the present embodiment, before covering the upper surface of the wiring, the heat is applied to the wiring in such a temperature region (a temperature region where the stress is easily relaxed, that is, 100 ° C. to 250 ° C.) (second heat treatment). Of the wiring, the upper surface of the wiring is covered with the stress reduced or reduced, and the wiring is fixed. Therefore, in the state of the finished product, stress is hardly alleviated in the wiring even when the high-temperature storage test is performed, and no void is generated between the wirings. As a result, defects due to stress migration of the buried copper wiring can be prevented, that is, the stress migration characteristics can be improved. Resistance rise due to the high-temperature storage test is also suppressed.
[0059]
The second heat treatment is performed in a non-oxidizing atmosphere such as a reducing atmosphere (for example, a hydrogen atmosphere), an inert gas (for example, He gas or Ar gas) atmosphere, a nitrogen gas atmosphere, or a mixed gas atmosphere thereof, that is, a reducing atmosphere. Alternatively, the reaction is preferably performed under an inert atmosphere at normal pressure (atmospheric pressure) or reduced pressure. When the heat treatment temperature of the second heat treatment is 100 ° C. or more, the surface of the wiring can be reduced while the stress remaining in the wiring is reduced, so that the number of manufacturing steps of the semiconductor device can be reduced. Note that when the heat treatment temperature of the second heat treatment is low and the reduction of the wiring surface is insufficient, a surface treatment (for example, removal of copper oxide with an acid) is performed separately from the second heat treatment to clean the surface of the wiring. It should just be. At this time, it should be noted that a process that is higher than the heat treatment temperature in the first heat treatment is not performed. Therefore, in this embodiment, the heat treatment temperature in the first heat treatment is used until a material film (for example, a barrier insulating film) is formed over the insulating film in which the wiring is buried and the upper surface of the wiring is covered. The processing to reach the above temperature is not performed.
[0060]
Further, in this embodiment mode, the first heat treatment and the second heat treatment are performed in different steps; however, the first heat treatment and the second heat treatment can be continuously performed in the same step. In this case, for example, the semiconductor substrate 11 is heat-treated at 400 ° C. for about 2 minutes in a mixed gas atmosphere of hydrogen gas and nitrogen gas (first heat treatment), and then the temperature of the semiconductor substrate 11 is reduced to 150 ° C. Then, the temperature is maintained at 150 ° C. for about 90 minutes (second heat treatment), and then the temperature of the semiconductor substrate 11 is lowered to room temperature. As described above, by continuously performing the first heat treatment and the second heat treatment in the same step, the residual stress of the main conductor film is relaxed without including another step therebetween, and the conductive barrier film and Is obtained, so that the reliability of the semiconductor device can be further improved.
[0061]
According to the study of the present inventors, in a wiring structure in which the diameter (diameter) of the via 45 is, for example, 0.3 μm or less, and the width of the wiring groove 26 or 46 is, for example, 1 μm or more, it is necessary to leave it at a high temperature. Resistance rises easily. Even in a wiring structure having such dimensions, by performing a heat treatment (a first heat treatment and a second heat treatment) as in the manufacturing method of the present embodiment, it is possible to suppress an increase in electrical resistance of the wiring due to high temperature storage. Can be.
[0062]
(Embodiment 2)
In the first embodiment, the conductive barrier films of the buried copper wiring, for example, the conductive barrier films 27 and 47 are formed by using a DC magnetron sputtering method or the like. In the present embodiment, the conductive barrier films of the buried copper wiring (the conductive barrier films 27 and 47) are formed by a bias sputtering method using an ionized metal. The bias sputtering method is a method of forming a film on the semiconductor substrate (semiconductor wafer) 11 by sputtering while applying a bias voltage to the semiconductor substrate (semiconductor wafer) 11 with a high-frequency power supply or the like. In the present embodiment, the bias power applied to the semiconductor substrate 11 is, for example, 1 W / cm in the step of forming the tantalum films of the conductive barrier films 27 and 47. ² (Applied power per unit area of the semiconductor substrate) or more, for example, 0.9 W / cm in the step of forming the tantalum nitride films of the conductive barrier films 27 and 47. ² (Applied power per unit area of the semiconductor substrate) or more, and the discharge pressure was 0.1 Pa or less, respectively. The film forming gas is an argon gas in the step of forming the tantalum films of the conductive barrier films 27 and 47, and a mixed gas of argon and nitrogen in the step of forming the tantalum nitride films of the conductive barrier films 27 and 47. there were. As the material of the conductive barrier films 27 and 47, other than the laminated film of the tantalum film and the tantalum nitride film, the materials exemplified in the first embodiment can be used. Other manufacturing steps and structures are almost the same as those in the first embodiment, and thus detailed description is omitted here.
[0063]
FIG. 21 is a cross-sectional view of a main part schematically showing a result of observing, with a TEM, a state in which a conductive barrier film 47 is formed on the inner wall (bottom and side walls) of the via 45 by using the bias sputtering method. FIG. 22 is a diagram schematically showing a result of observing a state in which the conductive barrier film 47 is formed on the inner wall of the via 35 by using a DC magnetron sputtering method, here, a long distance (long throw) sputtering method, using a TEM. It is a fragmentary sectional view.
[0064]
As can be seen from FIG. 22, the conductive barrier film 47 is formed asymmetrically at the bottom of the via 45 even when using the long-distance sputtering method in which the coverage of the formed film is relatively good, and the corner at the bottom of the via 45 is formed. In the vicinity, there may be a region where the conductive barrier film 47 is not formed. Further, the conductive barrier film 47 is not easily formed on the side wall of the via 45. However, as can be seen from FIG. 21, the conductive barrier film 47 is formed on the bottom and the side wall of the via 45 by forming the conductive barrier film 47 using the bias sputtering method as in the present embodiment. can do. The conductive barrier film 47 is also formed symmetrically or uniformly at the bottom of the via 45. The conductive barrier film 47 is also formed near the corner at the bottom of the via 45, and there is no region where the conductive barrier film 47 is not formed and the underlying material film is exposed. For this reason, the coverage of the conductive barrier film 47 can be improved or improved by using the bias sputtering method.
[0065]
Further, when the insulating film 42 and the insulating film 41 are dry-etched to form the via 45, the insulating film 41 is side-etched and the side wall of the via 45 is undercut by selection of etching conditions or the like. Sometimes. FIG. 23 is a cross-sectional view of a main part showing a state where the insulating film 41 is side-etched and the side wall of the via 45 is undercut. As shown in FIG. 23, when the insulating film 41 is side-etched, the diameter of the opening of the insulating film 41 becomes larger than the diameter of the opening of the insulating film 42, and at the bottom end of the via 45, A recessed region 41 a is formed in which the sidewall of the insulating film 41 is recessed in the direction parallel to the main surface of the semiconductor substrate 11 more than the sidewall of the insulating film 42. If the conductive barrier film 47 is not buried in such a recessed region 41a when forming the conductive barrier film 47, voids may be formed and the reliability of the wiring 50 may be adversely affected.
[0066]
FIG. 24 is a cross-sectional view of a principal part showing a state in which a conductive barrier film 47 is formed on a via having an undercut structure as shown in FIG. 23 by using a bias sputtering method. By forming the conductive barrier film 47 by using the bias sputtering method as in the present embodiment, as shown in FIG. 24, even if the recessed region 41a is generated at the bottom end of the via 45, Then, the recessed region 41a can be filled with the conductive barrier film 47, and no void occurs. Thereby, the reliability of the wiring 50 can be further improved.
[0067]
FIG. 25 is a graph showing the results of conducting a peel strength test of the conductive barrier film. In the graph of FIG. 25, the conductive barrier film is formed by using DC magnetron sputtering, here long-distance sputtering, and by using bias sputtering as in this embodiment. The measurement results of the peel strength (arbitrary unit) of the conductive barrier film are shown. In the peel strength test, a conductive barrier film, here a laminated film of a tantalum film and a tantalum nitride film, is formed on a test semiconductor substrate (wafer) by the above two types of film forming methods, and the formed conductive barrier film is formed. The peel strength of the film was measured. As shown in FIG. 25, the peel strength of the conductive barrier film can be increased by using the bias sputtering method. Thereby, the adhesive force or the adhesive force between the conductive barrier film and the base material film (the wiring 40 and the insulating films 41 to 44) can be improved.
[0068]
FIG. 26 is a graph showing the rate of increase in resistance of a buried copper wiring after a high-temperature storage test when a conductive barrier film is formed using a bias sputtering method as in the present embodiment. The horizontal axis of the graph of FIG. 26 corresponds to the rate of increase in the electrical resistance of the wiring after the high-temperature storage test (the rate of increase in electrical resistance based on the electrical resistance before the high-temperature storage), and the vertical axis of the graph of FIG. Corresponds to the distribution or cumulative probability (Cumulative Probability). The high-temperature storage test performed was a storage test at 150 ° C. for 100 hours, and the rate of increase (increase) in resistance was calculated by comparing the electrical resistance of the wiring before and after the storage test. The graph of FIG. 26 shows not only the case where the conductive barrier film of the wiring is formed by the bias sputtering method as shown in this embodiment (shown by a black circle in the graph), but also the conductive barrier film of the wiring. Is also graphed using DC magnetron sputtering (without applying a bias voltage to the semiconductor substrate) (indicated by white circles in the graph). Note that in both cases, the first heat treatment is performed at 400 ° C. and the second heat treatment is performed at 150 ° C.
[0069]
As can be seen from the graph of FIG. 26, by forming the conductive barrier film of the buried copper wiring by using the bias sputtering method as in the present embodiment, the increase in the resistance of the wiring after the high-temperature storage test is further suppressed. be able to. Therefore, in the present embodiment, the same effects as those of the first embodiment are obtained, and furthermore, the conductive barrier film of the buried copper wiring is formed by using the bias sputtering method. As a result, it is possible to more accurately prevent the failure due to the stress migration of the embedded copper wiring. Further, the reliability of the wiring can be further improved, and the reliability of the semiconductor device can be further improved. Further, the production yield of the semiconductor device can be improved, and the production cost can be reduced.
[0070]
Further, in the present embodiment, the conductive barrier film of the buried copper wiring is formed by using the bias sputtering method, but the main conductor films of the buried copper wiring (the main conductive films 29 and 49) are formed. Films (seed films 28 and 48) can be formed by bias sputtering. Thereby, the seed films 28 and 48 can be formed accurately on the conductive barrier film, and the main conductor film of the buried copper wiring can be formed more accurately.
[0071]
In this embodiment, the conductive barrier film of the buried copper wiring is formed by using the bias sputtering method. However, the conductive barrier film is formed by using the conductive barrier film formed by the bias sputtering method and the CVD method. It may be composed of a laminated film obtained by laminating a conductive barrier film formed by a method.
[0072]
The conductive barrier film formed by the bias sputtering method is made of, for example, a high melting point metal such as Ta (tantalum) or a high melting point metal nitride such as TaN (tantalum nitride), and is formed by a CVD method. Is made of a material obtained by adding silicon (Si) to a refractory metal nitride, for example, a TiSiN (titanium silicon nitride) film. Since the conductive barrier film formed by the CVD method has a higher covering property than the bias sputtering method, by forming a laminated film, the thickness of the entire conductive barrier film can be reduced without impairing the barrier property. A conductive barrier film can be formed in a suitable connection hole. Further, since the resistance of the entire conductive barrier film can be reduced, the delay due to the wiring resistance can be improved.
[0073]
As a material of the conductive barrier film formed by such a bias sputtering method, instead of tantalum or tantalum nitride, a high melting point metal such as tungsten nitride (WN) or titanium nitride (TiN) which hardly reacts with copper is used. Nitride can also be used. In addition, as a material of the conductive barrier film formed by the CVD method, a material obtained by adding silicon (Si) to another refractory metal nitride, a tantalum (Ta) hardly reacting with copper, Refractory metals or refractory metal nitrides such as titanium (Ti), tungsten (W), and titanium tungsten (TiW) alloys can also be used.
[0074]
(Embodiment 3)
In the first embodiment, after forming the via 45 and the wiring groove 46 and before forming the conductive barrier film 47, the oxidation formed on the surface of the wiring 40 (lower copper wiring) exposed at the bottom of the via 45. An etching process using Ar plasma is performed to remove copper, a conductive barrier film 47 is formed on the cleaned wiring 40, and a wiring 50 (upper copper wiring) is formed.
[0075]
In the present embodiment, in order to clean copper oxide formed on the surface of the wiring 40 exposed at the bottom of the via 45, hydrogen (H ₂ ) A reduction treatment by a reducing plasma treatment such as a plasma treatment is performed. For example, the semiconductor substrate 11 is placed in a processing chamber of a plasma CVD apparatus, and hydrogen gas (H ₂ ), And applying a plasma power supply to the semiconductor substrate 11 (particularly, the exposed surface of the wiring 40 at the bottom of the via 45). By such a reducing plasma treatment, on the surface of the wiring 40 at the bottom of the via 45, the copper oxide (CuO, CuO ₂ ) Is reduced to copper (Cu). In addition, instead of the hydrogen plasma treatment, the surface of the wiring 40 at the bottom of the via 45 can be reduced by annealing in a reducing atmosphere such as hydrogen (in a containing atmosphere). Therefore, in this embodiment, the exposed surface of the wiring 40 is subjected to a reduction treatment for oxygen in an atmosphere containing hydrogen.
[0076]
In this embodiment mode, hydrogen (H ₂ 2) Since the copper oxide formed on the surface of the wiring 40 exposed at the bottom of the via 45 by plasma processing or the like is reduced, the wiring 40 is not etched. Other manufacturing steps and structures are almost the same as those in the first embodiment, and thus detailed description is omitted here.
[0077]
The details of the main part in the present embodiment will be described with reference to FIGS. In FIG. 28, the seed film 48 is included in the main conductor film 49 as in the first embodiment, and is not shown.
[0078]
FIG. 27 is a cross-sectional view of a main part showing a state where the wiring 40 is etched (digged) in order to clean the surface of the wiring 40 exposed from the via 45. FIG. 28 is a cross-sectional view of a main part showing a state where the barrier insulating film 47 and the main conductor film 49 are embedded in the via having the structure shown in FIG.
[0079]
As shown in FIGS. 27 and 28, when the wiring 40 is etched by argon plasma or the like in order to clean the surface of the wiring 40 exposed from the via 45, the upper surface of the wiring 40 has an etching depth W. ₁ Only the etching causes a depression and a step. However, when the reduction process is performed by the reducing plasma process such as the hydrogen plasma process as in the present embodiment, the wiring 40 is hardly etched and the etching depth W ₁ Can be made substantially zero.
[0080]
FIG. 29 shows a depth (amount) W obtained by etching (digging) the wiring 40 at the bottom of the via 45. ₁ 6 is a graph showing a result obtained by performing a simulation calculation on the relationship between a stress difference generated in a formed wiring 40 (a difference between a maximum value and a minimum value of the stress in the wiring 40). FIG. 29 shows a case where the wiring 40 is not etched (the etching depth W ₁ = 0 nm) and 50 nm by etching with argon plasma or the like (etching depth W ₁ = 50 nm).
[0081]
As can be seen from FIG. 29, when the wiring 40 exposed from the via 45 is etched, the stress difference in the wiring 40 increases. If the stress difference in the wiring 40 is large or the stress gradient is large, the movement of copper in the wiring 40 is promoted, and defects due to stress migration are likely to occur. This may reduce the reliability of the embedded copper wiring. By reducing the wiring 40 exposed at the bottom of the via 45 by hydrogen plasma processing or the like as in the present embodiment, the depth (amount) of the etched (digged) wiring 40 is made substantially zero. Therefore, the stress difference in the wiring 40 can be reduced. As a result, the occurrence of defects due to stress migration can be more accurately prevented, and the reliability of the embedded copper wiring can be further improved.
[0082]
FIG. 30 is a graph showing the rate of increase in resistance of a buried copper wiring after a high-temperature storage test when hydrogen plasma processing is performed after the formation of vias and wiring grooves to reduce the lower copper wiring, as in the present embodiment. It is. The horizontal axis of the graph of FIG. 30 corresponds to the increase rate of the electrical resistance of the wiring after the high-temperature storage test (the increase rate of the electrical resistance based on the electrical resistance before the high-temperature storage test), and the vertical axis of the graph of FIG. Corresponds to the distribution or cumulative probability (Cumulative Probability). The high-temperature storage test performed was a storage test at 150 ° C. for 100 hours, and the rate of increase (increase) in resistance was calculated by comparing the electrical resistance of the wiring before and after the storage test. The graph of FIG. 30 shows the case where the lower copper wiring exposed at the bottom of the via is subjected to reduction treatment with hydrogen plasma as in the present embodiment, and then the conductive barrier film is formed to form the upper copper wiring (graph In addition to the case where the lower copper wiring exposed at the bottom of the via is etched using argon (Ar) plasma and then a conductive barrier film is formed to form the upper copper wiring (indicated by black circles in the drawing), (Indicated by a white circle in the graph). The etching amount (depth) of the lower copper wiring by argon plasma is about 3 nm in terms of a silicon oxide film (corresponding to several tens of nm in terms of CuO). Note that in both cases, the first heat treatment is performed at 400 ° C. and the second heat treatment is performed at 150 ° C.
[0083]
As can be seen from the graph of FIG. 30, under the conditions as in the present embodiment, the lower copper wiring exposed at the bottom of the via is cleaned to further suppress the increase in resistance of the wiring after the high-temperature storage test. Can be. Therefore, in the present embodiment, the same effect as in the first embodiment is obtained, and furthermore, the surface of the wiring exposed at the bottom of the via is subjected to a reducing plasma treatment such as a hydrogen plasma treatment or a reduction treatment by hydrogen annealing. By doing so, it is possible to more properly prevent defects due to stress migration of the embedded copper wiring as compared to the first embodiment. Further, the reliability of the wiring can be further improved, and the reliability of the semiconductor device can be further improved. Further, the production yield of the semiconductor device can be improved, and the production cost can be reduced.
[0084]
(Embodiment 4)
FIG. 31 is a fragmentary cross-sectional view of a semiconductor device according to another embodiment of the present invention during the manufacturing process thereof, which corresponds to the process step of FIG. In FIG. 31, the seed films 28 and 48 are included in the main conductor films 29 and 49 as in the first embodiment, and are not shown.
[0085]
In the first embodiment, the upper surfaces of the wirings 40 and 50 are covered with the insulating films 41 and 51 as barrier insulating films. In the present embodiment, instead of the barrier insulating films (insulating films 41 and 51), metal cap films 61 and 62 as conductive barrier films for suppressing or preventing copper diffusion on the upper surfaces of the wirings 40 and 50. To form
[0086]
The metal cap films 61 and 62 can be formed by, for example, a selective tungsten CVD method. For example, as shown in FIG. 11, after forming the wiring 40 embedded in the wiring groove 26, tungsten hexafluoride (WF) ₆ ) And hydrogen (H ₂ A) A metal cap film 61 is formed by selectively depositing a tungsten film on the upper surface of the wiring 40 exposed from the insulating film 25 by a CVD method using a gas. After that, the insulating film 42 is formed without forming the insulating film (barrier insulating film) 41. The metal cap film 62 can be formed in the same manner as the metal cap film 61. As another material of the metal cap films 61 and 62, another refractory metal or refractory metal nitride that functions as a barrier film, for example, titanium nitride (TiN) or tantalum nitride (TaN) can be used. Other manufacturing steps and structures are almost the same as those in the first embodiment, and thus detailed description is omitted here.
[0087]
In the present embodiment, the periphery (upper surface, side surface, and bottom surface) of a portion (main conductor film 29) mainly containing copper of wiring 40 is a metal film or a metal nitride film (conductive barrier film) as a conductive barrier film. It is surrounded by the film 27 and the metal cap film 61). Similarly, the periphery (upper surface, side surface, and bottom surface) of a portion (main conductor film 49) of which the main component is copper of the wiring 50 is a metal film or a metal nitride film (conductive barrier film 47 and conductive barrier film 47) as a conductive barrier film. It is surrounded by the metal cap film 62). In the present embodiment, the same effects as those of the first embodiment are obtained, and furthermore, the entire periphery of the portion of the copper wiring containing copper as a main component is surrounded by a metal film or a metal nitride film. As compared with the case where the upper surfaces of the body film 29 and the main conductor film 49 are in contact with the insulating film (barrier insulating film) (the first embodiment), the failure due to the stress migration of the wiring 40 and the wiring 50 is more accurately performed. (The stress migration characteristics can be further improved). Therefore, the reliability of the wiring can be further improved, and the reliability of the semiconductor device can be further improved. Further, the production yield of the semiconductor device can be improved, and the production cost can be reduced.
[0088]
(Embodiment 5)
32 and 33 are main-portion cross-sectional views of a semiconductor device in another embodiment of the present invention during the manufacturing process thereof, which correspond to the process steps subsequent to FIG. In FIG. 33, the seed films 28 and 48 are included in the main conductor films 29 and 49, as in the first embodiment, and are not shown.
[0089]
In the first embodiment, after the main conductor film 49 is formed, the first heat treatment is performed, and thereafter, the unnecessary conductive barrier film 47 and the unnecessary main conductor film 49 are removed by the CMP method. In this embodiment, as shown in FIG. 32, after a main conductor film 49 is formed, tantalum (Ta), tungsten (W), titanium (Ti), ruthenium (Ru), or the like is formed on main conductor film 49. A metal film 71 is formed. As the metal film 71, a metal nitride film such as tungsten nitride, titanium nitride, or tantalum nitride can be used. Then, a first heat treatment similar to that of the first embodiment is performed. Then, as shown in FIG. 33, the metal film 71 and the unnecessary conductive barrier film 47 and the main conductive film 49 are removed by using the CMP method or the like, and the conductive barrier film is formed in the via 45 and the wiring groove 46. The wiring 50 is formed by leaving the 47 and the main conductor film 49. In the CMP process, the metal film 71 is completely removed. Then, a second heat treatment similar to that of the first embodiment is performed. Note that the wiring 40 can be formed in a similar manner.
[0090]
In the present embodiment, the same effect as in the first embodiment is obtained, and further, a first heat treatment is performed in a state where the main conductor film 49 is covered with the metal film 71, so that the main conductor film 49 is formed. The effect that the crystallinity in the crystal grains can be further improved as compared with the first embodiment. For this reason, it is possible to more appropriately prevent the failure of the wiring 50 due to the stress migration. Further, the reliability of the wiring can be further improved, and the reliability of the semiconductor device can be further improved. Further, the production yield of the semiconductor device can be improved, and the production cost can be reduced.
[0091]
(Embodiment 6)
FIG. 34 is a fragmentary cross-sectional view of a semiconductor device according to another embodiment of the present invention, which corresponds to part of FIG. In FIG. 34, the seed films 28 and 48 are included in the main conductor films 29 and 49 as in the first embodiment, and are not shown.
[0092]
In the present embodiment, the occurrence of disconnection of the copper wiring is suppressed or prevented by adjusting the peel strength or adhesion (adhesion) at the interface of the copper wiring.
[0093]
Focusing on the wiring 40, the copper portion of the wiring 40 or the main conductor film 29 (including the seed film 28) forms an interface F with the insulating film (barrier insulating film) 41. ₁ , Interface F with conductive barrier film 27 ₂ And interface F with conductive barrier film 47 ₃ have. In the present embodiment, the interface F ₁ Adhesion N ₁ (Adhesion force between copper portion of wiring 40 or main conductive film 29 and insulating film 41), interface F ₂ Adhesion N ₂ (Adhesion force between copper portion of wiring 40 or main conductive film 29 and conductive barrier film 27), and interface F ₃ Adhesion N ₃ (Adhesion force between copper portion of wiring 40 or main conductor film 29 and conductive barrier film 47) ₃ Is not minimized (MINIMUM [N ₁ , N ₂ , N ₃ ] ≠ N ₃ ). Further, the interface F ₃ Adhesion N ₃ Is the interface F ₁ Adhesion N ₁ If larger (N ₃ > N ₁ ) Is more preferred. In such a structure, for example, as in Embodiment 2, the conductive barrier film 47 is formed by bias sputtering, and the interface F ₃ Adhesion N ₃ Can be realized by improving Adhesion force N at each interface by other methods ₁ , N ₂ And N ₃ May be adjusted.
[0094]
In the present embodiment, the adhesion N ₁ , N ₂ And N ₃ Of which is the adhesion N ₃ Is not minimal. For this reason, even if the stress is relaxed and a void is formed at the interface of the wiring 40, the weakest adhesion force is not at the bottom of the via 45, so that separation does not occur at the bottom of the via 45, and No disconnection occurs between the wirings 50. Also, the interface F ₃ Adhesion N ₃ Is the interface F ₁ Adhesion N ₁ If it is larger (N ₃ > N ₁ In particular, even if the peeling is likely to occur near the bottom of the via 45, the peeling occurs not at the bottom of the via 45 but at the interface between the copper portion of the wiring 40 or the interface between the main conductor film 29 and the insulating film (barrier insulating film) 41. Can be further expanded. Therefore, the reliability of the wiring can be further improved, and the reliability of the semiconductor device can be further improved. Further, the production yield of the semiconductor device can be improved, and the production cost can be reduced.
[0095]
As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and can be variously modified without departing from the gist thereof. Needless to say.
[0096]
In the above embodiment, a semiconductor device having a MISFET has been described. However, the present invention is not limited to this, and is applied to various semiconductor devices having a wiring including a main conductor film containing copper as a main component. be able to.
[0097]
Although the invention made by the inventor has been specifically described based on the embodiments, among the embodiments disclosed in the present application, the effects obtained by typical ones will be briefly described as follows. is there.
[0098]
After forming a main conductor film containing copper as a main component for forming an embedded wiring, a first heat treatment is performed at a first temperature, and a second heat treatment is performed at a second temperature lower than the first temperature. By relaxing the stress of the film, the reliability of the wiring can be improved. Further, the reliability of the semiconductor device can be improved.
[0099]
By forming the conductive barrier film of the buried copper wiring by using the bias sputtering method, it is possible to further suppress an increase in the resistance of the wiring after the high-temperature storage test. Therefore, the failure due to the stress migration of the embedded copper wiring can be more accurately prevented. Also, by forming a seed film between the main conductor film and the conductive barrier film by using the bias sputtering method, the seed film can be formed accurately on the conductive barrier film, and the main conductor film of the buried copper wiring can be formed more efficiently. It can be formed precisely.
[0100]
Hydrogen (H) is applied to the surface of the wiring exposed at the bottom of the via. ₂ ) By performing a reducing plasma treatment such as a plasma treatment or a reduction treatment by hydrogen annealing, copper oxide formed on the surface of the wiring can be cleaned, and the resistance of the wiring after a high-temperature storage test increases. It can be more suppressed.
[0101]
By forming a metal cap film as a conductive barrier film that suppresses or prevents the diffusion of copper on the top surface of the wiring instead of the barrier insulation film, compared to the case where the top surface of the main conductor film is in contact with the barrier insulation film As a result, defects due to stress migration of the wiring can be more accurately prevented.
[0102]
By performing the first heat treatment in a state where the main conductor film is covered with the metal film, crystallinity in the crystal grains of the main conductor film can be improved, and defects due to stress migration of the wiring can be more accurately prevented.
[0103]
Adhesion between the copper-based conductor film of the lower wiring and the conductive barrier film of the lower wiring, adhesion between the copper-based conductor film of the lower wiring and the barrier insulating film on the lower wiring Of the force and the adhesive force between the conductive film mainly composed of copper of the lower wiring and the conductive barrier film of the upper wiring, the conductive film mainly composed of copper of the lower wiring and the conductive barrier film of the upper wiring By preventing the adhesive force between the lower wiring and the upper wiring from being disconnected, disconnection between the lower wiring and the upper wiring can be prevented.
[0104]
【The invention's effect】
The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.
[0105]
The reliability of wiring including a main conductor film containing copper as a main component can be improved. Further, the reliability of the semiconductor device can be improved.
[Brief description of the drawings]
FIG. 1 is a graph showing a resistance increase rate of a buried copper wiring manufactured by a conventional technique after a high-temperature storage test.
FIG. 2 is a cross-sectional view schematically showing a result of TEM observation of a cross section of a copper wiring having high resistance.
FIG. 3 is a cross-sectional view for explaining a state where a copper wiring is formed while a stress remains.
FIG. 4 is a graph showing the relationship between the temperature at which a high-temperature storage test was performed and the rate of occurrence of resistance rise in wiring.
FIG. 5 is a fragmentary cross-sectional view of the semiconductor device according to the embodiment of the invention during a manufacturing step;
FIG. 6 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 5;
FIG. 7 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 6;
8 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 7;
9 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 8;
FIG. 10 is a cross-sectional view showing a conceptual structure of a heat treatment apparatus used in a manufacturing process of a semiconductor device according to an embodiment of the present invention.
11 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 9;
12 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 11;
13 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 12;
14 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 13;
15 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 14;
16 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 15;
17 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 16;
18 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 17;
19 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 18;
FIG. 20 is a graph showing a resistance increase rate of a buried copper wiring formed according to a manufacturing process of a semiconductor device according to an embodiment of the present invention after a high-temperature storage test.
FIG. 21 is a cross-sectional view of a principal part schematically showing a result of observing, by TEM, a state in which a conductive barrier film is formed by using a bias sputtering method.
FIG. 22 is a cross-sectional view of a principal part schematically showing a result of observing, with a TEM, a state in which a conductive barrier film has been formed by using a DC magnetron sputtering method.
FIG. 23 is an essential part cross-sectional view showing a state where the side wall of the via is undercut.
FIG. 24 is an essential part cross-sectional view showing a state in which a conductive barrier film is formed on a via having an undercut structure by using a bias sputtering method.
FIG. 25 is a graph showing the results of conducting a peel strength test of a conductive barrier film.
FIG. 26 is a graph showing a resistance increase rate of a buried copper wiring after a high-temperature storage test when a conductive barrier film is formed by a bias sputtering method.
FIG. 27 is a fragmentary cross-sectional view showing a state in which the wiring is etched to clean the surface of the wiring exposed from the via.
28 is a fragmentary cross-sectional view showing a state where a barrier insulating film and a main conductor film are embedded in the structure of FIG. 27;
FIG. 29 shows a depth W etched to clean the lower wiring exposed at the bottom of the via; ₁ 9 is a graph showing a result obtained by performing a simulation calculation on a relationship between a stress difference in a lower wiring and a lower wiring.
FIG. 30 is a graph showing a rate of increase in resistance of a buried copper wiring after a high-temperature storage test when a hydrogen plasma treatment is performed to reduce a lower copper wiring.
FIG. 31 is an essential part cross sectional view of the semiconductor device of another embodiment of the present invention during a manufacturing step;
FIG. 32 is an essential part cross sectional view of the semiconductor device of another embodiment of the present invention during a manufacturing step;
FIG. 33 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 32;
FIG. 34 is a fragmentary cross-sectional view of a semiconductor device according to another embodiment of the present invention;
[Explanation of symbols]
1 Copper wiring
2 Interlayer insulating film
3 Via section of upper layer copper wiring (via embedded section)
4 void
5 Interlayer insulating film
6 Wiring
7 Via section
11 Semiconductor substrate
12 Device isolation area
13 p-type well
14 Gate insulating film
15 Gate electrode
15a Silicide film
16 n ⁻ Semiconductor region
17 Sidewall
18 n ⁺ Semiconductor region
18a silicide film
19 n-channel MISFET
20 Insulating film
21 Insulating film
22 Contact hole
23 plug
23a Titanium nitride film
24 Insulating film
25 Insulating film
26 Wiring groove
27 Conductive barrier film
28 Seed film
29 Main conductor film
31 Heat treatment equipment
32 processing room
33 stage (mounting table)
34 Gas inlet
35 Gas outlet
40 Wiring
41 Insulating film
41a Retreat area
42 insulating film
43 insulating film
44 Insulating film
45 Via
46 Wiring groove
47 Conductive barrier film
48 Seed film
49 Main conductor film
50 Wiring
51 Insulating film
52 insulating film
53 insulating film
54 Insulating film
55 wiring
56 Insulating film
61 Metal cap film
62 Metal cap film
71 Metal film

Claims (22)

A method for manufacturing a semiconductor device, comprising:
(A) forming a first insulating film on a semiconductor substrate;
(B) forming a wiring opening in the first insulating film;
(C) forming a first conductive film containing copper as a main component so as to fill the wiring opening;
(D) a step of performing a first heat treatment at a temperature of 400 ° C. or higher after the step (c);
(E) a step of performing a second heat treatment at a temperature in the range of 100 to 250 ° C. after the step (d). A method for manufacturing a semiconductor device, comprising:
(A) forming a first insulating film on a semiconductor substrate;
(B) forming a wiring opening in the first insulating film;
(C) forming a first conductive film containing copper as a main component so as to fill the wiring opening;
(D) performing a first heat treatment at a first temperature after the step (c);
(E) a step of, after the step (d), performing a second heat treatment at a second temperature lower than the first temperature so as to relax the stress of the first conductor film. A method for manufacturing a semiconductor device, comprising:
(A) forming a first insulating film on a semiconductor substrate;
(B) forming a wiring opening in the first insulating film;
(C) forming a first conductive film containing copper as a main component so as to fill the wiring opening;
(D) after the step (c), performing a first heat treatment at a first temperature so as to grow crystal grains of the first conductor film;
(E) a step of, after the step (d), performing a second heat treatment at a second temperature lower than the first temperature so as to relax the stress of the first conductor film. The method of manufacturing a semiconductor device according to claim 1,
A method for manufacturing a semiconductor device, wherein a tensile stress is generated in the first conductive film by the first heat treatment. The method of manufacturing a semiconductor device according to claim 4,
A method of manufacturing a semiconductor device, wherein a tensile stress of the first conductor film generated by the first heat treatment is reduced by the second heat treatment. The method of manufacturing a semiconductor device according to claim 2,
The method of manufacturing a semiconductor device, wherein the first temperature is a temperature of 400 ° C. or more, and the second temperature is a temperature in a range of 100 to 250 ° C. The method of manufacturing a semiconductor device according to claim 2,
The method according to claim 1, wherein the first temperature is in a range of 400 to 450C. The method of manufacturing a semiconductor device according to claim 1,
In the step (d), the first heat treatment is performed in an inert atmosphere or a reducing atmosphere.
In the method (e), the second heat treatment is performed in an inert atmosphere or a reducing atmosphere. The method for manufacturing a semiconductor device according to claim 1,
After the step (c) and before the step (d), a step of removing the other first conductive film so as to leave the first conductive film embedded in the wiring opening is provided. A method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device according to claim 1,
After the step (d) and before the step (e), there is a step of removing the other first conductive film so as to leave the first conductive film embedded in the wiring opening. A method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, comprising: after the step (e), removing the other first conductive film so as to leave the first conductive film embedded in the wiring opening. The method of manufacturing a semiconductor device according to claim 9,
A step of forming a second insulating film on the first insulating film so as to cover the first conductive film remaining in the wiring opening after the step (e). Production method. The method of manufacturing a semiconductor device according to claim 9,
After the step (e), a step of selectively forming a third conductive film having a function of suppressing or preventing copper diffusion on the first conductive film left in the wiring opening is provided. Manufacturing method of a semiconductor device. The method of manufacturing a semiconductor device according to claim 1,
After the step (b) and before the step (c), a second conductive film having a function of suppressing or preventing copper diffusion is formed on the first insulating film including the bottom surface and the side wall of the wiring opening. Having a step of
In the method (c), the first conductive film is formed on the second conductive film so as to fill the wiring opening. The method for manufacturing a semiconductor device according to claim 14,
The method of manufacturing a semiconductor device, wherein the second conductive film is formed by a bias sputtering method. The method for manufacturing a semiconductor device according to claim 14,
The second conductive film is formed of a laminated film in which a second conductive barrier film formed by a CVD (Chemical Vapor Deposition) method is stacked on a first conductive barrier film formed by a bias sputtering method. A method for manufacturing a semiconductor device, comprising: The method for manufacturing a semiconductor device according to claim 1,
Forming a film made of tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride or ruthenium on the first conductor film after the step (c) and before the step (d). A method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device according to any one of claims 1 to 17,
In the step (c), the first conductive film is formed by a plating method. The method of manufacturing a semiconductor device according to claim 1,
The step (a) comprises:
(A1) forming a first wiring including a main conductor film containing copper as a main component on the semiconductor substrate;
(A2) forming the first insulating film on the first wiring;
Has,
The step (b) comprises:
(B1) forming the wiring opening exposing at least a part of the first wiring in the first insulating film;
(B2) performing a reduction treatment on oxygen in an atmosphere containing hydrogen on the first wiring surface exposed from the wiring opening;
A method for manufacturing a semiconductor device, comprising: The method for manufacturing a semiconductor device according to claim 1, wherein
The method of manufacturing a semiconductor device, wherein the steps (d) and (e) are performed continuously. Semiconductor substrate,
A first insulating film formed on the semiconductor substrate,
A first wiring opening formed in the first insulating film;
A first conductive film formed on the bottom and side surfaces of the first wiring opening and having a function of suppressing or preventing diffusion of copper, and a second conductive film formed on the first conductive film and containing copper as a main component A first wiring embedded in the first wiring opening,
A second insulating film formed on the first insulating film and the first wiring and having a function of suppressing or preventing copper diffusion;
A third insulating film formed on the second insulating film,
A second wiring opening formed in the third insulating film and exposing at least a part of an upper surface of the first wiring from a bottom surface thereof;
A third conductive film formed on the bottom and side surfaces of the second wiring opening and having a function of suppressing or preventing diffusion of copper, and a fourth conductive film formed on the third conductive film and containing copper as a main component A second wiring embedded in the second wiring opening,
With
The adhesion between the first conductor film and the second conductor film, the adhesion between the second conductor film and the second insulation film, and the adhesion between the second conductor film and the third conductor film. A semiconductor device, wherein the adhesion between the second conductor film and the third conductor film is not the minimum among the adhesion between them. The semiconductor device according to claim 21,
A semiconductor device, wherein the adhesion between the second conductor film and the third conductor film is larger than the adhesion between the second conductor film and the second insulating film.

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