JP2002043577A - Thin film semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To activate the impurity injected into the LDD region immediately under a gate electrode without having any effect on a channel area in a thin film semiconductor device. SOLUTION: The gate electrode 7 is constituted of a transparent conductive film 5 having low absorption coefficient and reflectivity against the light energy 8 projected at the time of activating the impurity and an opaque conductive film 6 having high absorption coefficient and reflectivity against the energy 8, with the film 5 being formed on the gate insulating film 4 side. In addition, a lightly doped area 10 is formed in a polycrystalline semiconductor film 3 immediately below the region of the transparent conductive film 5 which does not projectively underlie the opaque conductive film 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film semiconductor device and a method of manufacturing the same, and more particularly, to GOLD (G
ate Overlapped Lightly dop
The present invention relates to a thin film semiconductor device characterized by a laminated film structure of a gate electrode in an ed drain (Train) type TFT and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, liquid crystal display devices have been small, light,
Because of its low power consumption, it is used for OA terminals, projectors, etc., or for small liquid crystal televisions, etc., because of its portability. An active matrix type liquid crystal display device provided with an active element for switching is used.

In such an active matrix type liquid crystal display device, by operating each pixel in the display section with an active element such as a TFT, crosstalk during non-selection as in a simple matrix type liquid crystal display device is completely eliminated. And excellent display characteristics can be exhibited.

Among them, an active matrix type liquid crystal display device using a TFT has a high driving capability as a control element, and therefore, a liquid crystal display device with a built-in driver incorporating a data driver, a gate bus line, and the like, a high resolution and high definition liquid crystal display device. Although applied to display devices, polycrystalline silicon is particularly suitable for high-speed operation because it has a higher mobility than amorphous silicon, and it is possible to form peripheral circuits at the same time. TFT using polycrystalline silicon for active matrix type liquid crystal display
Is used.

Here, referring to FIGS. 5 and 6, a conventional T
An FT manufacturing process will be described. First, as shown in FIG. 5A, an amorphous silicon film 33 having a thickness of, for example, 50 nm is formed on a glass substrate 31 by using a PCVD method (plasma CVD method) via an SiO ₂ film 32 serving as a base insulating film. Deposit.

Referring to FIG. 5B, the amorphous silicon film 33 is irradiated with a laser beam 34 by using an excimer laser and laser-annealed to form polycrystalline silicon having sufficient crystallinity to form a channel layer. The film 35 is converted.

Referring to FIG. 5C, the polycrystalline silicon film 35 is formed into a predetermined shape polycrystalline silicon pattern 36 by performing dry etching using a predetermined shape resist pattern (not shown) as a mask. Again, the SiO _{2 is formed} by the PCVD method.
A film is deposited to form a gate oxide film 37, and then a Mo film 38 and A
1 films 39 are sequentially deposited.

Next, referring to FIG. 6D, phosphoric acid,
H consisting of nitric acid and acetic acid _ThreePO_FourU with a system etchant
The Al film 39 is etched by wet etching.
After touching, CF_Four+ O_TwoUsing F-based gas consisting of
Mo film 38 by dry etching
Etch. Note that the wet etching process
From the end of the resist pattern 40
Excessive etching so as to recede about 0.6 to 1.0 μm
I do.

Referring to FIG. 6E, the exposed portion of the gate oxide film 37 is removed by dry etching using the Mo film 38 as a mask.
^{A +} type source / drain region 43 is formed. in this case,
Since the Mo film 38 is thin, the region into which the P ions 41 have been implanted through the Mo film 38 is n ⁻ type LDD (Lightly).
(Doped Drain) area 42.

Next, as shown in FIG. 6 (f), the implanted impurity is activated by irradiating the polycrystalline silicon pattern 36 into which the impurity has been implanted with laser light 44 using an excimer laser and performing laser annealing.

Although not shown, the entire surface is made of SiO _2.
A film and a SiN film are sequentially deposited to form an interlayer insulating film. Next, after forming an n-type source / drain region 43 and a contact hole for a gate electrode, a T
i, Al and Ti are sequentially deposited and patterned to form Ti
By forming a source / drain electrode and a gate lead electrode (both not shown) having a / Al / Ti structure, T
The basic configuration of the FT is obtained.

In a so-called GOLD type TFT in which such an n ⁻ type LDD region 42 is covered with a gate electrode, o
At the time of ff, the n ⁻ -type LDD region 42 functions as a resistance region, so that a low leakage current can be realized. At the time of the on-time, the n ⁻ -type LDD region 42 is effectively affected by the gate voltage and has a low resistance channel. Since it acts as a region, the mobility does not decrease.

[0013]

However, in a conventional GOLD type TFT using a low-temperature polycrystalline silicon film,
Although it is necessary to perform annealing to activate the implanted impurities as described above, in the n ⁻ -type LDD region 42 immediately below the Mo film 38 constituting the gate electrode, the Mo film 38 emits the laser light 44. There is a problem that the light cannot be sufficiently activated due to reflection, and the resistance is too high to suppress the mobility.

On the other hand, in thermal annealing, since a glass substrate is used, the upper limit temperature is limited, and it is difficult to sufficiently activate impurities.

When the laser light is irradiated from the back surface of the glass substrate 31, the impurities injected into the n ⁻ -type LDD region 42 can be activated. However, the laser light also irradiates the channel region. Therefore, there is a problem that the crystallinity of the polycrystalline silicon pattern 36 optimized in the step of FIG. 2B is adversely affected.

Therefore, an object of the present invention is to activate an impurity implanted in an LDD region immediately below a gate electrode without affecting a channel region.

[0017]

Here, means for solving the problems in the present invention will be described with reference to FIG. (1) The present invention relates to a thin-film semiconductor device in which at least a polycrystalline semiconductor film 3, a gate insulating film 4, and a gate electrode 7 are sequentially stacked on an insulating substrate 1, the gate electrode 7 is replaced with the gate insulating film 4 A transparent conductive film 5 having a small absorptance and reflectance for light energy 8 irradiated when activating impurities in order from the side, and a narrower width than the transparent conductive film 5 and a larger absorptivity and reflectance for the light energy 8 The low-impurity-concentration region 10 is formed in the polycrystalline semiconductor film 3 immediately below a region of the transparent conductive film 5 that does not overlap with the opaque conductive film 6.

By adopting such a gate electrode 7 configuration, the impurities implanted in the polycrystalline semiconductor film 3 immediately below the opaque conductive film 6 of the transparent conductive film 5 that does not overlap with the opaque conductive film 6 are sufficiently activated to reduce the impurity. Impurity concentration region 10, ie, LD
The region can be a D region, and a decrease in mobility in the low impurity concentration region 10 can be suppressed.

Further, in the present invention, in the above (1), it is preferable that a transparent insulating substrate is used as the insulating substrate 1 and a polycrystalline silicon film is provided as the polycrystalline semiconductor film 3 via the base insulating film 2.

As described above, the polycrystalline semiconductor film 3 is preferably a polycrystalline silicon film capable of obtaining a polycrystalline film having excellent characteristics, and prevents diffusion of impurities from a transparent insulating substrate such as a glass substrate. For this purpose, it is preferable to interpose the base insulating film 2.

(2) Further, according to the present invention, in the above (1), the opaque conductive film 6 is made of Al, Mo, Ti, Cr, Mo.
/ Al, Ti / Al, or Cr / Al, and the transparent conductive film 5 is made of ITO, In ₂ O ₃ , SnO ₂ ,
It is characterized by being one of ZnO and CdO.

As described above, as the opaque conductive film 6 constituting the upper part of the gate electrode 7, Al, Mo, Ti, Cr, Mo / Al, Ti
/ Al or Cr / Al is preferable, and the transparent conductive film 5 constituting the lower part of the gate electrode 7 can transmit light energy 8 irradiated for activating impurities, and ITO, In with excellent conductivity
Any of ₂ O ₃ , SnO ₂ , ZnO and CdO is suitable.

(3) The present invention provides a method of manufacturing a thin film semiconductor device in which at least a polycrystalline semiconductor film 3, a gate insulating film 4, and a gate electrode 7 are sequentially laminated on an insulating substrate 1, A transparent conductive film 5 having a small absorptance and reflectivity for light energy 8 applied when activating the impurities injected into the source / drain regions 9 in order from the gate insulating film 4 side; An opaque conductive film 6 which is narrow and has a large absorptance and reflectivity with respect to the light energy 8, and is irradiated with the light energy 8 via the transparent conductive film 5, immediately below a region which does not overlap the opaque conductive film 6 in a projected manner. The impurity implanted into the polycrystalline semiconductor film 3 is activated to form a low impurity concentration region 10.

As described above, by irradiating the light energy 8 through the transparent conductive film 5 to activate the impurities implanted in the polycrystalline semiconductor film 3 immediately below the region which does not projectively overlap the opaque conductive film 6, , Does not adversely affect the previously optimized channel region.

Further, the present invention can be applied to the case (3) in which a film crystallized by irradiating an amorphous semiconductor film with light energy 8 is used as the polycrystalline semiconductor film 3. desirable.

As described above, since the impurity activation step does not adversely affect the channel region, it is necessary to optimize the crystallinity of the polycrystalline semiconductor film 3 by light irradiation in advance to a degree suitable for the channel region. Can be.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A manufacturing process of a TFT according to an embodiment of the present invention will be described with reference to FIGS. FIGS. 2 (a) see First, the thickness of the TFT substrate is, for example, on the glass substrate 11 of 1.1mm transparent, the thickness of the base insulating film by a PCVD method, for example, 100 nm SiO ₂ Membrane 1
2, and an amorphous silicon film 13 having a thickness of, for example, 50 nm is sequentially deposited.

Next, as shown in FIG. 2B, a laser beam 14 is irradiated by using a XeCl excimer laser.
The amorphous silicon film 13 is crystallized by scanning and laser annealing while overlapping with each other to convert the amorphous silicon film 13 into a polycrystalline silicon film 15 having suitable crystallinity for the channel region.

Next, as shown in FIG. 2C, the polycrystalline silicon film 15 is subjected to dry etching to form an island-like polycrystalline silicon pattern 16.
After that, again using the PCVD method,
For example, a 120 nm SiO ₂ film is deposited to form a gate oxide film 17, and then a 30 nm thick ITO film 1 serving as a gate electrode is formed by sputtering.
An Mo film 19 of 8 and 30 nm and an Al film 20 of 300 nm are sequentially deposited. In this case, A
When the 1 film 20 is directly provided, a battery effect occurs due to the electronegativity, so the Mo film 19 is interposed.

Next, referring to FIG. 3D, using the resist pattern 21 as a mask, the Al film 20 and the Mo film 19 are subjected to wet etching using an H ₃ PO ₄ type etchant composed of phosphoric acid, nitric acid and acetic acid. Are sequentially etched. In this case, the Al film 20 and the Mo film 19 are over-etched so as to recede from the end of the resist pattern 21 by about 0.6 μm.

Next, referring to FIG. 3E, using the resist pattern 21 as a mask, TCP
(Transformer Coupled Plas
ma) method, that is, an ICP characterized by the shape of the upper coil.
(Inductive Coupled Plasm
a) Using a plasma etching method using an apparatus, HB
r at a flow rate of 300 sccm, a pressure of 7 mTorr, a substrate temperature of 40 ° C., a bias voltage of 600 W at 4 MHz, and a voltage of 3 at 13.56 MHz.
By applying a top power of kW, the ITO film 18
Is etched. The top power is power applied to generate plasma from above.

Next, referring to FIG. 3F, the exposed portion of the gate oxide film 17 is removed by performing dry etching using CHF ₃ as an etching gas using the ITO film 18 as a mask.
By implanting P ions 22 into the polycrystalline silicon pattern 16 using the 0 / Mo film 19 as a mask, n
⁺ -Type source / drain regions 24 are formed and
1 film 20 / ITO film 1 that does not projectively overlap with Mo film 19
The n ⁻ -type LDD region 23 is formed immediately below the region 8.

Next, referring to FIG. 4G, the implanted P is activated again by using a XeCl excimer laser to perform scanning and laser annealing while overlapping the laser beam 25. In this laser annealing step, the n ⁻ -type LDD region 23 is irradiated with the laser light 25 via the ITO film 18, so that the P injected into the n ⁻ -type LDD region 23 is also sufficiently activated.

Next, as shown in FIG. 4H, the entire surface is made of SiO _{2 serving as} an etching stopper layer.
After sequentially depositing the film 26 and the SiN film 26 which is a main part of the interlayer insulating film, contact holes for the n ⁺ -type source / drain regions 24 and the Al film 20 are formed, and then Ti, Al, and Ti are deposited on the entire surface. The basic structure of an n-channel TFT is obtained by sequentially depositing and patterning to form a source / drain electrode 28 having a Ti / Al / Ti structure and a gate lead electrode (not shown).

As described above, in the embodiment of the present invention, after the impurity is implanted into the region where the n ⁻ -type LDD region 23 is to be formed, the laser light 25 is irradiated through the ITO film 18 to perform laser annealing. Therefore, the implanted P can be sufficiently activated, whereby the n ⁻ -type LDD region 23 having a sufficiently low resistance at the time of on can be obtained, so that the mobility does not decrease.

Further, since the channel region is not irradiated with the laser beam 25 using the Al film 20 as a mask,
The crystallinity of the previously optimized channel region changes and the TFT
Does not deteriorate.

Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations and conditions described in the embodiments, and various modifications are possible. For example,
In the above embodiment, the amorphous silicon film is used over the glass substrate with the base insulating film interposed therebetween. However, the base insulating film is not always necessary. When a substrate is used, an amorphous silicon film may be directly deposited on the substrate.

In the above embodiment, the active layer is made of polycrystalline silicon. However, the present invention is not limited to polycrystalline silicon, and polycrystalline silicon germanium may be used. This makes it possible to increase the mobility.

Further, in the above embodiment, a transparent glass substrate is provided as the substrate since the description is made on the assumption that the TFT substrate of the active matrix type liquid crystal display device is used. Since the present invention is not limited to a TFT for a liquid crystal display device, the substrate does not need to be transparent and need not be a glass substrate.

Further, in the above embodiment, ITO is used as a transparent electrode constituting a lower portion of the gate electrode is not limited to ITO, an In ₂ O _3,
Other transparent conductive films such as SnO ₂ , ZnO, and CdO may be used.

In the above embodiment, the IT
Although an Mo / Al laminated film is used as an opaque electrode constituting the upper part of the gate electrode in order to suppress the generation of the battery effect between the O film and the O film, depending on the type of the transparent electrode, Mo / A is used.
It is not limited to the 1-layer film, and if the battery effect does not occur in consideration of the electronegativity, Al, Ti, C
r, Mo, Ti / Al, or Cr / Al may be used.

Further, in the above-described embodiment, the description has been made of the n-channel TFT, but the n-channel TFT is described.
It is needless to say that the present invention is not limited to the FT, but is also applicable to a p-channel type TFT, and is also applicable to a complementary type TFT.

Further, in the above embodiment, in the impurity activation step, laser annealing using an excimer laser is used. However, the present invention is not limited to laser annealing, and lamp annealing using a flash lamp or the like is used. It is good to go.

[0044]

According to the present invention, by forming the gate electrode with a laminated structure of a wide transparent conductive film and a narrow opaque conductive film, the LDD region covered with the gate electrode is interposed through the transparent conductive film. Light annealing becomes possible,
As a result, the impurity implanted into the LDD region can be sufficiently activated without adversely affecting the channel region to improve the operating characteristics of the thin-film semiconductor device, thereby contributing to the performance improvement of the active matrix type liquid crystal display device and the like. But big.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a basic configuration of the present invention.

FIG. 2 is an explanatory diagram of a manufacturing process partway through an embodiment of the present invention.

FIG. 3 is an explanatory diagram of a manufacturing process of the embodiment of the present invention up to the middle of FIG. 2 and thereafter.

FIG. 4 is an explanatory diagram of a manufacturing process of the embodiment of the present invention after FIG. 3;

FIG. 5 is an explanatory diagram of a manufacturing process of a conventional TFT halfway.

FIG. 6 is an explanatory view of a manufacturing process of the conventional TFT after FIG. 5;

[Explanation of symbols]

REFERENCE SIGNS LIST 1 insulating substrate 2 base insulating film 3 polycrystalline semiconductor film 4 gate insulating film 5 transparent conductive film 6 opaque conductive film 7 gate electrode 8 light energy 9 source / drain region 10 low impurity concentration region 11 glass substrate 12 SiO ₂ film 13 amorphous silicon Film 14 laser light 15 polycrystalline silicon film 16 polycrystalline silicon pattern 17 gate oxide film 18 ITO film 19 Mo film 20 Al film 21 resist pattern 22 P ion 23 n ^- type LDD region 24 n ⁺ type source / drain region 25 laser light 26 SiO ₂ film 27 SiN film 28 source and drain regions 31 glass substrate 32 SiO ₂ film 33 an amorphous silicon film 34 laser beam 35 polycrystalline silicon film 36 of polycrystalline silicon pattern 37 a gate oxide film 38 Mo film 39 Al film 40 resist pattern 1 P ions 42 n ^- -type LDD region 43 n ⁺ -type source and drain regions 44 laser beam

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/265 602 G02F 1/136 500 21/28 301 H01L 29/78 616L 617K 617L 617M (72) Inventor Yashima Mishima 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture F-term in Fujitsu Limited (reference) 2H092 HA03 HA04 HA28 JA25 JA33 JA35 JA39 JA40 JA44 KA04 KA05 KA10 KA12 KA18 MA05 MA08 MA18 MA19 MA27 MA30 MA41 NA21 4M104 AA01 AA08 AA09 BB36 CC05 DD10 DD11 FF13 GG20 5F052 AA02 BB07 DA02 DB03 EA11 JA01 5F110 AA16 BB01 CC02 DD02 DD13 EE03 EE04 EE07 EE11 EE14 EE15 EE22 EE44 FF02 FF30 GG01 GG01 GG01 GG02 GG01 GG01

Claims (3)

[Claims] In a thin-film semiconductor device in which at least a polycrystalline semiconductor film, a gate insulating film, and a gate electrode are sequentially laminated on an insulating substrate, when the gate electrode is activated in order from the gate insulating film, impurities are activated. A transparent conductive film having a small absorptance and reflectivity for light energy applied to the transparent conductive film, and an opaque conductive film having a narrower width than the transparent conductive film and having a large absorptance and reflectivity for the light energy, and A thin-film semiconductor device, wherein a low-impurity-concentration region is formed in the polycrystalline semiconductor film immediately below a region not overlapping the opaque conductive film of the film. 2. The opaque conductive film is made of Al, Mo, T
i, Cr, Mo / Al, Ti / Al, or Cr / Al, and the transparent conductive film is made of ITO, In _2
2. The thin-film semiconductor device according to claim 1, wherein the thin-film semiconductor device is any one of O ₃ , SnO ₂ , ZnO, and CdO. 3. A method of manufacturing a thin-film semiconductor device in which at least a polycrystalline semiconductor film, a gate insulating film, and a gate electrode are sequentially stacked on an insulating substrate,
A transparent conductive film having a small absorptance and reflectivity for light energy applied when activating impurities in order from the gate insulating film side, and a narrower than the transparent conductive film and having an absorptivity and a reflectivity for the light energy. A large opaque conductive film, and irradiating light energy through the transparent conductive film to activate impurities implanted in the polycrystalline semiconductor film immediately below a region that does not overlap the opaque conductive film. A method for manufacturing a thin-film semiconductor device, comprising a region having an impurity concentration.