JP2002040962A - Electro-optical device, manufacturing method therefor, and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a degree of freedom for designing a peripheral circuit such as a sampling circuit in an electro-optical device, or to reduce wiring resistance of the peripheral circuit. SOLUTION: Six picture signal lines 122 are wiring of a 3rd layer formed of the same layer as data lines 114. Here, wiring 193 branching from a certain picture signal line 122 and crossing the other picture signal line 122 is used by being connected in parallel with 1st layer wiring 112b and 2nd layer wiring 181b. The wiring 112b of these is formed of the same layer as the scanning lines in a display area, and the wiring 181b is formed of the same layer as the TFT barrier film in the display area, therefore, although both wiring 112b, 181b are singly of high resistance, they are reduced in resistance in parallel connection. Moreover, in the other parts, a degree of freedom for designing is improved by singly using the 2nd layer wiring.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electro-optical device which uses a conductive layer different from a conductive layer forming a scanning line or a data line for a peripheral circuit to improve the degree of freedom in designing the peripheral circuit. The present invention relates to a device, a method of manufacturing the same, and an electronic apparatus using the electro-optical device for a display unit.

[0002]

2. Description of the Related Art Generally, an electro-optical device, for example, a liquid crystal device for performing a predetermined display by using liquid crystal as an electro-optical material has a structure in which liquid crystal is sandwiched between a pair of substrates. Among them, for example, an active matrix liquid crystal device in which a pixel electrode is driven by a three-terminal switching element has the following configuration. That is, in this type of liquid crystal device, a plurality of scanning lines and a plurality of data lines are provided on one of a pair of substrates so as to cross each other, and a thin film transistor ( A pair of a three-terminal switching element represented by a Thin Film Transistor (hereinafter referred to as a “TFT”) and a pixel electrode are provided. Here, the TFT is turned on when the scanning signal supplied to the scanning line corresponding to the intersection becomes an active level, and supplies the image signal applied to the corresponding data line to the pixel electrode. Further, a transparent counter electrode facing the pixel electrode is provided on the other substrate.

On the other hand, a driving circuit for driving these scanning lines and data lines includes a scanning line driving circuit, a data line driving circuit,
It is composed of a sampling circuit and the like. Among them, the scanning line driving circuit supplies a scanning signal to a scanning line at a predetermined timing, and the data line driving circuit supplies a sampling signal at a predetermined timing. An image signal supplied via an image signal line is sampled in accordance with a sampling signal by a sampling switch provided for each data line and supplied to a corresponding data line.

Further, an electro-optical device with a built-in peripheral circuit has been developed in which these driving circuits themselves are provided on the periphery of a region (display region) where pixel electrodes are arranged on one substrate. In this type of electro-optical device, from the viewpoint of, for example, increasing the efficiency of the manufacturing process, an active element that forms a drive circuit is formed by a common process with a switching element connected to a pixel electrode. For example, in the above-described liquid crystal device, an element forming a driving circuit is a TFT formed by the same process as a switching element connected to a pixel electrode. Such an electro-optical device with a built-in peripheral circuit is advantageous in reducing the size and cost of the entire device as compared with an electro-optical device of a type in which a drive circuit is separately provided externally.

In recent years, not only electro-optical devices but also general display devices, for example, XGA (1024 × 768)
Dot), SXGA (1365 x 1024 dots), UXGA
(1600 x 1200 dots), the demand for higher definition is increasing.

[0006]

However, in order to attain high definition and at the same time to reduce the size of the device, there is a need for a technique for correspondingly reducing the arrangement pitch of the scanning lines and the arrangement pitch of the data lines. You. That is, since the scanning line driving circuit supplies a scanning signal to each of the scanning lines, a unit circuit (latch circuit) constituting the scanning line driving circuit
Etc. must be within the scanning line arrangement pitch. Similarly, since the data line driving circuit sequentially supplies a sampling signal to a sampling switch provided for each data line, a unit circuit or the like constituting the data line driving circuit has an arrangement pitch of the data lines or It must be within the pitch of the integral multiple. As described above, in an electro-optical device with a built-in peripheral circuit, in order to achieve high definition and miniaturization, unit circuits and the like in a scanning line driving circuit and a data line driving circuit must be accommodated in a very limited space. Since it must be formed, there is a problem that its design becomes very difficult.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described circumstances, and has as its object to improve the degree of freedom in designing peripheral circuits, a method of manufacturing the same, and the electro-optical device. The present invention provides an electronic device using the same as a display unit.

[0008]

In order to achieve the above object, an electro-optical device according to a first aspect of the present invention comprises a plurality of scanning lines and a plurality of data lines, and the scanning lines and the data lines. , A pair of a switching element and a pixel electrode provided corresponding to the intersection of, an intermediate conductive film that electrically connects the switching element and the corresponding pixel electrode, and a conductive material that forms the intermediate conductive film. It includes a wiring formed of the same layer as the layer, and a peripheral circuit for driving each of the switching elements.

According to this structure, in the region where the pixel electrodes are arranged (display region), the intermediate conductive film is used for connection between the switching element and the pixel electrode, and is formed of the same conductive layer as the intermediate conductive film. The wiring will be used also in the peripheral circuit. That is, in the present invention, the intermediate conductive film originally used in the display region is also used as a part of the wiring of the peripheral circuit. Therefore, in the peripheral circuit, the number of new wiring layers is increased, and accordingly, the degree of freedom in design is improved.

Here, in the present invention, the intermediate conductive film is a first conductive film provided corresponding to an electrode of a switching element.
While being electrically connected through the contact hole of
Preferably, the pixel electrode is electrically connected through a second contact hole. In this configuration, the electrode of the switching element is connected to the intermediate conductive film via the first contact hole, while the pixel electrode is connected to the intermediate conductive film via the second contact hole. For this reason, the intermediate conductive film functions as a barrier film when connecting the pixel electrode to the other end of the switching element, so that it is possible to reduce defects that occur when the contact hole extends over a long distance.

Further, in the present invention, each pixel electrode is provided with a storage capacitor having one end connected to the pixel electrode and the other end commonly connected, and the intermediate conductive film includes an electrode forming the storage capacitor. Is also desirable. According to this configuration, the voltage holding characteristic of the pixel electrode is improved by the storage capacitor. At this time, the intermediate conductive film functions as a part of the electrode forming the storage capacitor.

Further, in the present invention, the intermediate conductive film may have a light shielding property, and a part of light transmitted or reflected by the pixel electrode may be defined by the intermediate conductive film. . According to this configuration, in a portion defined by the intermediate conductive film in the light transmission or reflection region, at least a dedicated light-shielding film can be omitted, so that the configuration can be simplified accordingly.

Similarly, in order to achieve the above-mentioned object, in the electro-optical device according to the second aspect of the present invention, the first
Forming a second and a third conductive layer in this order;
The third conductive layer is an electro-optical device having a lower resistance than the first conductive layer, and includes a plurality of scanning lines including the first conductive layer and the third conductive layer; A plurality of data lines formed so as to intersect with the plurality of scanning lines, a pair of a switching element and a pixel electrode provided corresponding to an intersection of the scanning lines and the data lines, An intermediate conductive film that electrically connects the switching element and a corresponding pixel electrode, and a wiring that includes the first, second, and third conductive layers. And a peripheral circuit for driving each of them.

According to this configuration, in the display area,
An intermediate conductive film is used for connection between the switching element and the pixel electrode, and the wiring made of the same second conductive layer as the intermediate conductive film is used in the peripheral circuit together with the wiring made of the first and third conductive layers. Will be used. That is, in the present invention, the intermediate conductive film originally used in the display region is also used as a part of the wiring in the peripheral circuit. For this reason, in the peripheral circuit, since the number of new wiring layers is increased by one layer, the degree of freedom in design is improved accordingly.

Here, in the present invention, the intermediate conductive film is a first conductive film provided corresponding to an electrode of a switching element.
While being electrically connected through the contact hole of
Preferably, the pixel electrode is electrically connected through a second contact hole. In this configuration, the electrode of the switching element is connected to the intermediate conductive film via the first contact hole, while the pixel electrode is connected to the intermediate conductive film via the second contact hole. For this reason, the intermediate conductive film functions as a barrier film when connecting the pixel electrode to the other end of the switching element, so that it is possible to reduce defects that occur when the contact hole extends over a long distance.

In the present invention, since the third conductive layer has a lower resistance than the first conductive layer, it is desirable that the entire wiring is formed by the third conductive layer. However,
Since the peripheral circuit always has an intersection or a branch of the wiring, it is impossible to form the entire wiring with the third conductive layer. Therefore, in the present invention, for example, when it is necessary to use a wiring made of a high-resistance first conductive layer, the peripheral circuit includes a wiring made of the first conductive layer and a wiring made of the second conductive layer. And a parallel wiring electrically connected in parallel with each other. As described above, by using the parallel wiring in which the wiring made of the first conductive layer and the wiring made of the second conductive layer are electrically connected in parallel, the wiring made of the first or second conductive layer can be used alone. In this case, the wiring resistance can be suppressed to be lower than in the case of using the same.

As a portion where such a parallel wiring is to be used, for example, a branch wiring branched from a wiring made of the third conductive layer and intersecting with a wiring different from the wiring may be considered. Such a branch wiring should be formed of a third conductive layer having a low resistance. However, the branch wiring formed of the third conductive layer, and a portion that intersects with another wiring different from the wiring is formed of the same wiring. This is because it cannot be formed from the third conductive layer.

The peripheral circuit includes the third conductive layer, and includes h image signal lines for supplying image signals corresponding to h (h is an integer of 2 or more) data lines. , Provided for each of the data lines, among the image signals supplied to the h image signal lines, sample corresponding ones according to a predetermined sampling signal,
When a sampling switch for supplying a corresponding data line is included, at least a part of a wiring branching from the image signal line and reaching the sampling switch may be considered as a part where the parallel wiring is to be used. Such wiring is
Since it supplies an image signal to be applied to the pixel electrode, it should be made of a third conductive layer having low resistance.
This is because it cannot be formed from the same third conductive layer because it crosses another image signal line.

According to the present invention, in the case where parallel wirings are formed, among the parallel wirings, the wiring made of the second conductive layer is replaced with the wiring formed of the first conductive layer in the parallel wirings. Conducting between the exposed third and fourth contact holes, a wiring made of the third conductive layer is provided at a position corresponding to the third or fourth contact hole, and the second conductive layer is formed. A first configuration electrically connected to a fifth contact hole exposing a wiring made of a layer, and a wiring made of the second conductive layer among the parallel wirings, Conduction is provided between the third and fourth contact holes exposing the wiring made of the first conductive layer, respectively, and the wiring made of the third conductive layer is located at a different position from the third and fourth contact holes. Set in It is in the first wiring composed of a conductive layer to a sixth contact hole exposing a and the second configuration being electrically connected conceivable. Here, in the case where stress is applied to the second conductive layer due to warpage or the like, a crack may be generated if a contact hole that exposes a wiring formed of the second conductive layer is provided. In the second configuration, it is not necessary to provide a contact hole for exposing the second conductive layer, so that it is possible to reduce defects due to the occurrence of cracks.

Further, in the first or second configuration, among the parallel wirings, one or a plurality of wirings formed of the second conductive layer are provided between the third and fourth contact holes. It is desirable that the contact hole is electrically connected to the wiring made of the first conductive layer. As a result, in the parallel wiring, the connection is made in parallel also in the contact holes other than the third and fourth contact holes.

Now, in the present invention, the peripheral circuit includes:
A configuration may be adopted in which a wiring including the first, second, and third conductive layers is provided in a part of the region. According to this configuration, different three-layer wirings are laid out in the same region, so that the space can be reduced.

In the present invention, each pixel electrode is provided with a storage capacitor having one end connected to the pixel electrode and the other end commonly connected, and the intermediate conductive film includes an electrode forming the storage capacitor. Is desirable. According to this configuration, the voltage holding characteristic of the pixel electrode is improved by the storage capacitor. At this time, the intermediate conductive film functions as a part of the electrode forming the storage capacitor.

Such a storage capacitor includes a first capacitor having a gate oxide film of the switching element sandwiched between the electrode of the switching element and a capacitance line formed of the second conductive layer, and the intermediate conductive film. And a second capacitor having an interlayer insulating film sandwiched between the capacitor line and the capacitor line. According to this configuration, the storage capacity is equal to the first capacity and the second capacity.
Therefore, the capacity can be increased as compared with the configuration of a single capacity.

Now, in the present invention, the first conductive layer comprises:
Desirably, it is made of polysilicon. This is because if the scanning lines are formed from a metal thin film or a metal silicide, inconveniences such as peeling will occur in a subsequent high-temperature process.

In the present invention, the third conductive layer is preferably made of aluminum. This facilitates lowering the resistance of the third conductive layer.

In addition, in the present invention, it is preferable that the second conductive layer is made of a material having a higher melting point than the material forming the third conductive layer. This is because it is necessary to prevent melting and peeling by a high-temperature process after the formation of the second conductive layer. The material having such a high melting point is, in addition to polysilicon, Ti (titanium), Cr,
(Chrome), W (tungsten), Ta (tantalum), Mo
(Molybdenum) or Pb (lead) alone or an alloy thereof, a metal silicide, or the like.

Next, in order to achieve the above object, in an electro-optical device according to a third aspect of the present invention, a plurality of scanning lines and a plurality of data lines and an intersection of the scanning lines and the data lines are provided. A pair of a switching element and a pixel electrode provided corresponding to the portion, and an intermediate conductive film that electrically connects the switching element and the corresponding pixel electrode;
A peripheral circuit for driving each of the switching elements, and a wiring connected to the peripheral circuit and formed of the same layer as a conductive layer forming the intermediate conductive film are provided.

In the present invention, the wiring connected to the peripheral circuit is formed of the same conductive layer as the intermediate conductive film used for connecting the switching element and the pixel electrode. For this reason, since it can be used as a new wiring layer, the degree of freedom in design is improved.

Here, in the present invention, the wiring is characterized in that it intersects the image signal line formed of the same layer as the conductive layer forming the data line in a lower layer. In this configuration, the wiring that intersects the image signal line can use the same conductive layer as the intermediate conductive film as the wiring.

Further, the image signal lines are provided with a plurality of image signal lines, the wirings are connected corresponding to the respective image signal lines, and the size of each wiring is substantially the same. I do. With this configuration, the resistance of each wiring connected to the image signal can be made equal, the variation of the image signal due to the resistance difference of each wiring can be prevented, and good display can be performed.

Further, in the present invention, a first conductive layer formed of the same layer as the conductive layer forming the data line, and a position separated from the first conductive layer formed of the same layer as the conductive layer forming the data line. And a third conductive layer formed of the same layer as the semiconductor layer of the switching element is electrically connected to the first conductive layer and the second conductive layer via a contact hole. It is characterized by being electrically connected. According to this configuration, the third conductive layer formed of the same layer as the semiconductor layer of the switching element can be formed as a bypass.

Further, in the present invention, the wiring is electrically connected to the third conductive layer via a contact hole. According to this configuration, since the wiring and the third conductive layer are connected in parallel, the resistance of the wiring can be reduced.

In the present invention, the third conductive layer is made of polysilicon. According to this configuration, even if the wiring is formed of a metal having a high melting point or the like, the wiring is electrically connected to the third conductive layer of polysilicon through the contact hole. Absent. The third conductive layer is electrically connected to the first conductive layer and the second conductive layer via a contact hole. However, since the third conductive layer is formed of polysilicon, no crack is generated in the polysilicon. .

Further, in the present invention, at least three contact holes for electrically connecting the wiring and the third conductive layer are provided. According to this configuration, since a redundant wiring can be formed between the wiring and the third conductive layer, a crack or the like occurs in the wiring or the third conductive layer, so that a redundant wiring is formed between the wiring and the third conductive layer. Short circuit can be prevented.

In the present invention, an image signal line formed of the same layer as the conductive layer forming the data line is disposed between the first conductive layer and the second conductive layer. . According to this configuration, the image signal line formed of the same layer as the conductive layer forming the data line can be arranged without interfering with the first conductive layer and the second conductive layer.

Further, since the electronic apparatus of the present invention includes the above-described electro-optical device, the degree of freedom particularly when designing peripheral circuits is improved.

Next, in order to achieve the above object, in the method of manufacturing an electro-optical device according to the fourth aspect of the present invention, a method for manufacturing a plurality of scanning lines corresponding to intersections between the plurality of scanning lines is provided. A method for manufacturing an electro-optical device including a pair of a switching element and a pixel electrode, wherein a step of forming a switching element in a portion where the scanning line and the data line should intersect, and an intermediate conductive film connected to the switching element When,
A step of forming a wiring used for a peripheral circuit for driving each of the switching elements from the same conductive layer, and a step of forming a pixel electrode connected to the intermediate conductive film. I have. According to this manufacturing method, similar to the first aspect of the present invention, the number of new wiring layers is increased in the peripheral circuit, so that the degree of freedom in design is improved accordingly.

According to another aspect of the present invention, there is provided a method of manufacturing an electro-optical device according to a fifth aspect of the present invention, wherein a plurality of scanning lines are switched corresponding to intersections between the plurality of scanning lines. A method of manufacturing an electro-optical device including a pair of an element and a pixel electrode, the method including forming a scan line and a wiring used for a peripheral circuit for driving each of the switching elements from a first conductive layer. There and
Forming a switching element in a portion where the scanning line and the data line should intersect, and then forming an intermediate conductive film connected to the switching element and a wiring used for the peripheral circuit from a second conductive layer, respectively; A step of forming the data line and a wiring used for the peripheral circuit from a third conductive layer, respectively, and a step of forming a pixel electrode connected to the intermediate conductive film. According to this manufacturing method, as in the second invention,
In the peripheral circuit, the number of new wiring layers is increased by one, and accordingly, the degree of freedom in design is improved.

[0039]

Embodiments of the present invention will be described below with reference to the drawings.

<Schematic Configuration of Electro-Optical Device> First, the electro-optical device according to the present embodiment will be described. This electro-optical device uses a liquid crystal as an electro-optical material and performs a predetermined display by an electro-optical change. Figure 1
FIG. 1A is a perspective view illustrating a configuration of a liquid crystal panel 100 excluding an external circuit in the electro-optical device, and FIG.
FIG. 2B is a sectional view taken along line AA ′ in FIG.

As shown in these figures, in the liquid crystal panel 100, an element substrate 101 on which various elements and pixel electrodes 118 and the like are formed, and a counter substrate 102 on which a counter electrode 108 and the like are provided are formed by spacers (not shown). Seal material 1 including (omitted)
The electrodes are bonded so that the electrode-forming surfaces face each other with a certain gap maintained by 04, and a liquid crystal 105 of, for example, a TN (Twisted Nematic) type is sealed as an electro-optical material in this gap.

Here, the element substrate 101 is made of glass,
Although a semiconductor, quartz, or the like is used, glass or the like is used for the counter substrate 102. When an opaque substrate is used as the element substrate 101, it is used as a reflection type instead of a transmission type. In addition, the sealing material 10
Numeral 4 is formed along the periphery of the counter substrate 102, and is partially open to seal the liquid crystal 105. For this reason, after the liquid crystal 105 is sealed, the opening thereof is
6 sealed.

Next, on the opposing surface of the element substrate 101,
In a region 140a on one outer side of the sealing material 104,
A data line driving circuit described later is formed to output a sampling signal. Further, a region 150a near this one side where the sealing material 104 is formed
, An image signal line, a sampling circuit, or the like may be formed. On the other hand, a plurality of mounting terminals 107 are formed on the outer peripheral portion of this one side, so that various signals are input from an external circuit (not shown).

The area 13 on two sides adjacent to this one side
A scanning line driving circuit is formed in each of the pixels 0a to drive the scanning lines from both sides. If the delay of the scanning signal supplied to the scanning line does not matter, a configuration in which the scanning line driving circuit is formed only on one side may be employed.

Then, in the remaining one side area 160a,
A precharge circuit, which will be described later, is formed, and a wiring shared by the two scanning line driving circuits may be formed outside the precharge circuit.

On the other hand, the opposing electrode 108 provided on the opposing substrate 102 is electrically connected to the element substrate 101 by a conductive material in at least one of four corners of the bonding portion with the element substrate 101. ing.

In addition, although not specifically shown, a color layer (color filter) is provided on the counter substrate 102 in a region facing the pixel electrode 118 as necessary. However,
In the case where the present invention is applied to the use of color light modulation as in a double-plate type projector described later, it is not necessary to form a coloring layer on the counter substrate 102.

Conventionally, in the counter substrate 102,
Regardless of whether a colored layer is provided or not, the pixel electrode 1 is used to prevent a decrease in contrast ratio due to light leakage.
Although the light-shielding film is provided in a portion other than the region opposed to the element 18, in the present embodiment, as described later, the element substrate 10
Since the light-shielding region in the pixel portion is defined on one side, the light-shielding film provided on the counter substrate 102 is omitted.

The element substrate 101 and the counter substrate 10
As described later, an alignment film (omitted in FIG. 1) that has been rubbed so that the major axis direction of the molecules of the liquid crystal 105 is continuously twisted by about 90 degrees between the two substrates is provided on the opposite surface of the liquid crystal 105. On the other hand, a polarizer (not shown) corresponding to the alignment direction is provided on each back side. FIG. 1 (b)
In the above, the counter electrode 108, the pixel electrode 118, the mounting terminal 107, and the like are provided with a thickness, but this is a convenient measure for indicating the formation position, and is actually Thin enough to be ignored.

<Electrical Configuration> Next, the electrical configuration of the element substrate 101 of the liquid crystal panel 100 will be described. FIG. 2 is a schematic diagram showing this configuration.

As shown in this figure, the element substrate 101
Is provided with a plurality of mounting terminals 107 for inputting various signals from an external circuit. Signals input through these mounting terminals 107 are supplied to various parts via various wirings. Therefore, these signals will be briefly described.

First, as shown in FIG. 4, each of VID1 to VID6 distributes one image signal VID supplied in synchronization with the dot clock DCLK to six systems and increases the image signal VID by six times in the time axis. The signal is expanded and supplied to the sampling circuit 150 via the six image signal lines 122.

The image signals VID1 to VID6
Is appropriately inverted in polarity by an external circuit. Here, the polarity inversion in the present embodiment refers to the opposite electrode 108.
Refers to alternately inverting the voltage level between positive polarity and negative polarity based on the voltage LCcom applied to the data line. Generally, the method of applying the image signal to the data line Is polarity inversion in scanning line units, polarity inversion in data line units, polarity inversion in pixel units, or polarity inversion in frame units. Horizontal scanning period,
The period is set to the period of the dot clock DCLK or one vertical scanning period. However, in the present embodiment, for convenience of explanation,
A case where the polarity is inverted in units of scanning lines will be described as an example, but the present invention is not limited to this.

Second, VssY and VssX correspond to the scanning line driving circuit 130 and the data line driving circuit 14, respectively.
0 is the lower voltage (ground potential) of the power supply. VddY and VddX are higher voltages of the power supplies in the scanning line driving circuit 130 and the data line driving circuit 140, respectively. Of these, the lower voltage V
Since ssY is the ground potential of the storage capacitor described later, it is also supplied to each pixel via the capacitor line 175.

Third, LCcom is a voltage signal applied to the counter electrode 108. Therefore, the voltage signal LCcom
Are supplied at points corresponding to the corners of the sealing material 104 (see FIG. 1) used for bonding to the counter substrate 102. Therefore, when the element substrate 101 is actually bonded to the counter substrate 102, the electrode 109 and the counter electrode 108 are connected via the conductive material, and the voltage signal L is applied to the counter electrode 108.
Ccom is applied. Note that the voltage signal LCcom
Is a constant voltage with respect to the time axis, and the external circuit sets the image signals VID1 to VID1 based on the voltage signal LCcom.
The VID 6 is divided into a high order side and a low order side every one horizontal scanning period to perform AC driving. Also,
In the present embodiment, there are two points where the electrodes 109 are provided. The reason why the electrodes 109 are provided is as follows.
Since the voltage signal LCcom is applied to the counter electrode 108 via the conductive material, it is sufficient that the electrode 109 is provided in at least one place. For this reason, the electrode 10
9 may be provided at one location or at three or more locations.

Fourth, DY is, as shown in FIG.
A transfer start pulse supplied at the beginning of one vertical effective scanning period, and CLY is a clock signal used in the scanning line driving circuit 130. CLYinv is an inverted clock signal obtained by inverting the level of the clock signal CLY.

Fifth, DX is, as shown in FIG.
A transfer start pulse supplied at the beginning of one horizontal effective scanning period, and CLX is a clock signal used in the data line driving circuit 140. CLXinv is an inverted clock signal obtained by inverting the level of the clock signal CLX. ENB1 and ENB2 are enable signals used to limit each output signal of the shift register in the data line driving circuit 140 to a predetermined pulse width, as described later. In addition, NRG is a precharge control signal, and NRS is a precharge voltage signal, which will be described later in detail.

Now, the display region 100a of the element substrate 101
In this case, a plurality of scanning lines 112 are arranged in parallel along the row (Y) direction, and a plurality of data lines 114 are arranged in parallel along the column (X) direction. Pixels are provided corresponding to each intersection.

More specifically, as shown in FIG. 3, at a portion where the scanning line 112 and the data line 114 intersect,
TFT 11 as a switching element for controlling pixels
6 is connected to the scanning line 112 while the TFT 1
Sixteen sources are connected to data lines 114,
The drain of the TFT 116 has a rectangular transparent pixel electrode 11.
8 is connected.

As described above, in the liquid crystal panel 100,
Since the liquid crystal 105 is interposed between the electrode forming surfaces of the element substrate 101 and the opposing substrate 102, the liquid crystal capacitance of each pixel includes the pixel electrode 118, the opposing electrode 108, and the liquid crystal interposed between these two electrodes. 105. Here, for convenience of explanation, the total number of the scanning lines 112 is “m”, and the total number of the data lines 114 is “6n”.
(Where m and n are integers), the pixel is
Corresponding to each intersection between the scanning line 112 and the data line 114, they are arranged in a matrix of m rows × 6n columns.

The display area 100a also includes a storage capacitor 119 for preventing leakage of the liquid crystal capacitance.
Are provided for each pixel. One end of the storage capacitor 119 is connected to the pixel electrode 118 (the drain of the TFT 116), and the other end is commonly connected by a capacitor line 175. For this reason, the storage capacitor 119 is electrically in parallel with the liquid crystal capacitor, so that the retention characteristics of the liquid crystal capacitor are improved, and a display with a high contrast ratio is achieved. In the present embodiment, the lower voltage VssY of the power supply is applied to the capacitor line 175. However, since a constant voltage may be applied here, the higher voltage of the power supply may be applied. A configuration in which the voltage VddY, the voltage LCcom, or the like is applied may be employed. The detailed configuration of the pixel including the storage capacitor 119 will be further described later.

Therefore, returning to FIG. 2 again, the scanning line driving circuit 130 sets the scanning signals G1, G2,..., Gm, which become active levels sequentially every horizontal scanning period 1H, within one vertical effective display period. This is output to each scanning line 112. The detailed configuration is not shown because it is not directly related to the present invention, but is constituted by a shift register and a plurality of AND circuits (or NAND circuits). Of these, as shown in FIG. 4, the shift register supplies the transfer start pulse DY supplied at the beginning of one vertical effective scanning period.
To the clock signal CLY (and the inverted clock signal CL
Yinv), each time the level transitions (both at the rising edge and the falling edge), the signals G1 ′, G
2 ′, G3 ′,..., Gm ′. Each AND circuit outputs one of the signals G1 ′, G2 ′, G3 ′,.
The AND signal between adjacent signals is obtained, and the scanning signal G
1, G2, G3,..., Gm.

Further, the data line driving circuit 140 outputs the sampling signals S1, S2,
.., Sn are output within one horizontal effective scanning period. Although the detailed configuration is not directly related to the present invention, it is not shown in the figure, but is composed of a shift register and a plurality of AND circuits. The shift register, as shown in FIG. 4, sends the transfer start pulse DX supplied at the beginning of one horizontal effective scanning period to the clock signal CL.
Each time the level of X (and the inverted clock signal CLXinv) transitions, it is sequentially shifted to generate signals S1 ', S2',
3 ′,..., Sn ′. Each AND circuit outputs the pulse widths of the signals S1 ′, S2 ′, S3 ′,..., Sn ′ using the enable signal ENB1 or ENB2. So that the periods SMPa
, S3,..., Sn
Is output.

Subsequently, the sampling circuit 150 includes a sampling switch 151 provided for each data line 114.
It is composed of On the other hand, the data lines 114 are divided into blocks every six lines, and j is counted from the left in FIG.
(J is the first, second,..., N) -th data line 1 among the six data lines 114 belonging to the block.
Sampling switch 151 connected to one end of 14
Is the image signal VI supplied via the image signal line 122.
D1 is sampled during a period in which the sampling signal Sj is active and supplied to the data line 114. The sampling switch 151 connected to one end of the second data line 114 among the six data lines 114 also belonging to the i-th block is connected to the image signal VID2 supplied via the image signal line 122. Is sampled during a period in which the sampling signal Sj is active, and the data line 1
14.

Similarly, among the six data lines 114 belonging to the j-th block, each of the sampling switches 151 connected to one end of the third, fourth, fifth, and sixth data lines 114 is connected to the image switch. Image signals VID3, VID4, VID5, VID supplied via signal line 122
6 is sampled during a period when the sampling signal Sj is active, and the corresponding data line 11 is sampled.
4. That is, when the sampling signal Sj becomes the active level, the image signals VID1 to VID6 are simultaneously sampled on each of the six data lines 114 belonging to the i-th block.

On the other hand, a precharge circuit 160 is provided in a region opposite to the data line drive circuit 140 with the display region 100a interposed therebetween. This precharge circuit 160
Is composed of a pre-charging switch 161 provided for each data line 114.
Numeral 61 designates, when the precharge control signal NRG supplied via the precharge control line 163 becomes active level, the precharge voltage signal NRS supplied via the precharge signal line 165 and the corresponding data line 1
14 is precharged.

Here, the precharge control signal NRG is
As shown in FIG. 5, this signal is an active level signal during a period separated from the temporal front and rear ends of one horizontal blanking period. Also, the precharge voltage signal N
As shown in the figure, RS is a signal whose level is inverted at the voltages Vg + and Vg- with respect to the voltage LCcom every one horizontal scanning period 1H.

On the other hand, the voltage LCcom is a temporally constant voltage applied to the counter electrode 108 as described above, and is the amplitude center voltage of the image signals VID1 to VID6. The voltages Vg + and Vg- have the same effective value of the difference voltage with respect to the voltage LCcom (the absolute values are equal).
The voltages are higher and lower voltages than the voltage LCcom, respectively. Here, when the present embodiment is a normally white mode in which white display is performed without applying a voltage, the voltages to be applied to the pixel electrode 118 for black display on the positive electrode side and the negative electrode side are represented by Vb + and Vb−. Then, the voltage Vg + is set to an intermediate voltage between the voltage Vb + and the voltage LCcom, and the voltage Vg− is set to the voltage Vb− and the voltage LCcom.
Is set to an intermediate voltage between That is, the voltage Vg + and the voltage Vb- correspond to an intermediate (gray) voltage in the writing on the positive and negative sides, respectively.

The precharge circuit 1 having such a configuration
According to 60, the sampling signals S1, S2, S3,
.., 1 before one horizontal effective display period to which Sn is supplied
During the horizontal retrace period, each data line 114 is set to the voltage Vg.
+ Or Vg- beforehand, so that the image signal VID1
As a result, the load when .about.VID6 is sampled on the data line 114 is reduced.

The scanning line driving circuit 130,
The data line driving circuit 140, the sampling circuit 150, the precharge circuit 160, and the like are formed around the display area 100a together with the inspection circuit for determining the presence or absence of a defect after manufacturing, and are therefore called peripheral circuits. is there. However, since the inspection circuit is not directly related to the present case, the description thereof is omitted.

<Operation of Electro-Optical Device> Next, the operation of the electro-optical device according to the above-described configuration will be described. First, attention is paid to one horizontal scanning period 1H in which the scanning signal G1 is at the active level. Note that in this one horizontal scanning period, if writing on the positive electrode side is performed for the sake of convenience, the image signals VID1 to VID6 are higher voltages than the voltage LCcom applied to the counter electrode 108.

Prior to this, as shown in FIG. 5, the precharge control signal NRG becomes an active level during a period separated from the front and rear ends of the retrace period.
At this time, the precharge voltage signal NRS becomes the voltage Vg + corresponding to the writing on the positive electrode side. Therefore, during this period, all the data lines 114 are precharged to the voltage Vg +.

Next, when one horizontal retrace period is completed and one horizontal effective display period is reached, a transfer start pulse DX is firstly input.
Is supplied to the data line driving circuit 140 as shown in FIG. 4 or FIG. This transfer start pulse DX is output as signals S1 ′, S2 ′, S3 ′,..., Sn ′ sequentially shifted every time the level of the clock signal CLX changes. The signals S1 ', S2', S3 ',
, Sn 'are narrowed down to the period SMPa so that adjacent ones do not overlap each other, and are output as sampling signals S1, S2, S3, ..., Sn.

On the other hand, as shown in FIG. 4, an image signal VID of one system is supplied by an external circuit as shown in FIG.
To VID6, and is extended to 6 times the time axis and supplied to the liquid crystal panel 100.

Here, when the sampling signal S1 is at the active level during the period when the scanning signal G1 is at the active level, all the first TFTs 116 counted from the top in FIG. 2 are turned on, and the first block from the left in FIG. The image signals VID1 to VID6 are sampled on the six data lines 114 belonging to.
Then, the sampled image signals VID1 to VID
6 is applied to the corresponding pixel electrode 118 by the TFT 116 of the pixel intersecting with the first scanning line 112 and the six data lines 114.

Thereafter, when the sampling signal S2 becomes the active level, the image signals VID1 to VID1 are respectively applied to the six data lines 114 belonging to the second block.
VID6 is sampled and these image signals VI
D1 to VID6 correspond to the first scanning line 112 and the sixth scanning line 112, respectively.
The data is applied to the corresponding pixel electrode 118 by the TFT 116 of the pixel intersecting the data line 114.

The sampling signal S3,
When S4,..., And Sn sequentially become active levels, 6 belonging to the third, fourth,.
Image signals VID1 to VI
D6 is sampled, and these image signals VID1 to
VID 6 is applied to the corresponding pixel electrodes 118 by the TFTs 116 of the pixels that intersect with the first scanning line 112 and the six data lines 114. Thus, writing to all the pixels in the first row is completed.

Next, a period during which the scanning signal G2 is active will be described. In the present embodiment, as described above, since the polarity inversion is performed in units of scanning lines, the writing on the negative electrode side is performed in this one horizontal scanning period. Therefore, the image signals VID1 to VID6 are lower voltages than the voltage LCcom applied to the counter electrode 108. Prior to this, since the voltage of the precharge voltage signal NRS during the flyback period becomes Vg-, all the data lines 114 are precharged to the voltage Vg- when the precharge control signal NRG becomes active level. The Rukoto.

The other operations are the same, and the sampling signals S1, S2, S3,..., Sn sequentially become active levels, and the writing to all the pixels in the second row is completed.

Similarly, the scanning signals G3, G4,
…, Gm becomes active, and the third and fourth rows
.., Writing is performed on the pixels in the m-th row. As a result, the positive-side writing is performed for the pixels in the odd-numbered rows, while the negative-side writing is performed for the pixels in the even-numbered rows.
Writing over all the pixels in the rows to the m-th row is completed.

Then, also in the next one vertical scanning period,
Similar writing is performed, but at this time, the writing polarity for the pixels in each row is switched. That is, in the next one vertical scanning period, writing is performed on the pixels on the negative side for the pixels on the odd-numbered rows, while writing on the positive side is performed on the pixels on the even-numbered rows.

As described above, since the write polarity for the pixel is switched every one vertical scanning period, no DC component is applied to the liquid crystal 105, and the deterioration is prevented.

In such driving, the data line 11
Compared with the method of driving each pixel 4 one by one, the time for sampling the image signal by each sampling switch 151 is six times, so that the writing power time in each pixel is sufficiently ensured. For this reason, a high contrast ratio is obtained. Further, the number of stages of the shift register in the data line driving circuit 140 and the clock signal CL
Since the frequency of X is reduced to 1/6, the power consumption can be reduced along with the reduction in the number of stages.

Further, the sampling signals S1, S2,
... Since the active period of Sn is narrower than the half cycle of the clock signal CLX and is limited to the period SMPa, the overlap between adjacent sampling signals is prevented in advance. For this reason, it is prevented that the image signals VID1 to VID6 to be sampled on the six data lines 114 belonging to a certain block are simultaneously sampled on the six data lines 114 belonging to the block adjacent thereto. High quality display is possible.

<Detailed Configuration of Pixel> Next, the details of the pixel will be described with reference to FIGS. 6 and 7. FIG. FIG. 6 is a plan view showing a detailed configuration of the pixel portion, and FIG.
FIG. 3 is a sectional view taken along line BB ′ in FIG. In FIG. 6, only the outline of the pixel electrode 118 serving as the uppermost conductive layer is indicated by a broken line for the sake of understanding.

First, as shown in FIG. 7A, a semiconductor layer 30 made of polysilicon is provided on a substrate 10 as a base material of an element substrate 101 with a base insulating film 40 interposed therebetween.
Its surface is covered with an insulating film 32 formed by thermal oxidation.

On the other hand, as shown in FIG.
Reference numeral 14 extends in the Y direction, and the scanning lines 112 extend in the X direction. The capacitance line 175 is provided in parallel with and close to the scanning line 112, but protrudes to the preceding stage (upper side in FIG. 6) at a portion crossing the data line 114 so as to overlap the data line 114. It is formed.

Here, the semiconductor layer 30 is connected to the data line 114.
From the intersection of the capacitor line 175
6 (the right direction in FIG. 6), the direction in which the capacitance line 175 projects in the lower layer of the data line 114 (the same upward direction),
Further, it is formed to extend in a total of three opposite directions (same and downward) in a substantially T-shape and to be covered by these wirings.

Further, in the semiconductor layer 30, the scanning lines 11
The portion overlapping 2 is the channel region 30a. In other words, a portion of the scanning line 112 that intersects with the semiconductor layer 30 is used as the gate electrode 116G. Note that the scanning line 112 including the gate electrode 116G and the capacitor line 175 are formed of, for example, polysilicon or the like as described later.

In the semiconductor layer 30, the source side of the channel region 30a has a low concentration (translation is lightly doped).
Source region 30b, high concentration (translation is heavily
A source region 116S (expressed as doped) is provided, while a low-concentration drain region 30c and a high-concentration drain region 116D are provided on the drain side, so-called LDD.
(Lightly Doped Drain) structure.

Of these, the high concentration source region 116S is
It is connected to a data line 114 made of aluminum or the like by a contact hole 52 that opens the insulating film 32, the first interlayer insulating film 41, and the second interlayer insulating film 42.

On the other hand, the high-concentration drain region 116D is connected to one end of an intermediate conductive film 181 made of a refractory metal, polysilicon, or the like by a contact hole 51 that opens the insulating film 32 and the first interlayer insulating film 41. ing. On the other hand, the other end of the intermediate conductive film 181 is connected to the pixel electrode 118 by a contact hole 53 that opens the second interlayer insulating film 42 and the third interlayer insulating film 43. That is, the pixel electrode 118 is connected to the high-concentration drain region 116D of the TFT 116 via the intermediate conductive film 181.

Here, the pixel electrode 118 is not directly connected to the high-concentration drain region 116D, but the intermediate conductive film 181 is not used.
The configuration for indirectly connecting via is as follows. That is, since the pixel electrode 118 is an electrode for applying a voltage to the liquid crystal capacitance, the pixel electrode 118 is formed in a portion close to the liquid crystal 105, and on the contrary, the semiconductor layer 30 is formed in a portion far away. Further, between the semiconductor layer 30 and the pixel electrode 118, if the TFT 116 is a planar type as in the present embodiment, wiring layers such as the scanning lines 112 and the data lines 114 are laminated via an interlayer insulating film. Therefore, the distance between the semiconductor layer 30 and the pixel electrode 118 is inevitably increased. Therefore, in a configuration in which the pixel electrode 118 is directly connected to the high-concentration drain region 116D, a relatively deep contact hole must be formed by, for example, dry etching. However, when forming a contact hole with such a depth, if it is excessively etched,
A defect that the semiconductor layer 30 is pierced occurs. In particular, there is no great difference in the selectivity between the semiconductor layer 30 and the insulating film, and further, the thickness of the semiconductor layer 30 is extremely smaller than the thickness of the insulating film to be etched. That makes it more difficult.

Therefore, first, the high-concentration drain region 11
A contact hole 51 is provided at a position corresponding to 6D, and the insulating film 32 and the first interlayer insulating film 41 are opened.
An intermediate conductive film 181 electrically connected through the contact hole 51 is formed, and the intermediate conductive film 181 functions as a barrier film of the high-concentration drain region 116D. Thereby, when the contact hole 53 is opened before the pixel electrode 118 is formed,
By using 1 as an etching stopper,
This prevents breakthrough of the semiconductor layer 30 due to excessive etching.

Now, this intermediate conductive film 181 is particularly
As shown in FIG. 7, the capacitance line 175 is substantially covered between the adjacent data lines 114, and a part of the capacitance line 175 extends over the scanning line 112 (but is electrically insulated). Further, a region where the pixel electrode 118 is not formed is
In the Y direction, it is covered with the data line 114, and in the X direction, it is covered with the scanning line 112 and the intermediate conductive film 181. Here, polysilicon may be used as the intermediate conductive layer 181, and Ti may be used.
(Titanium), Cr (Chrome), W (Tungsten), Ta
(Tantalum), Mo (molybdenum) or Pb (lead) alone or an alloy thereof, or metal silicide may be used. Therefore, the light-shielding region in the pixel portion is completely defined by the data lines 114, the scanning lines 112, and the intermediate conductive film 181, so that the light-shielding film separately provided on the counter substrate 102 can be omitted. In addition, the semiconductor layer 30
Since the data lines 114, the scanning lines 112, the capacitance lines 175, and the intermediate conductive film are covered, light from above the substrate
Intrusion into the FT 116 will be prevented. Further, a light shielding film may be formed below the semiconductor layer 30 and between the substrate 10 and the base insulating film 40. This can prevent light from the lower side of the substrate from entering the TFT 116, so that the TFT 11
6 is prevented from changing.

Next, a detailed configuration of the storage capacitor 119 will be described with reference to FIGS. 7B and 7C in addition to FIGS. 6 and 7A. Here, FIG.
FIG. 7B is a cross-sectional view taken along line CC ′ in FIG. 6, and FIG. 7C is a diagram illustrating an equivalent circuit of the storage capacitor 119.

First, in the semiconductor layer 30, a region 30f adjacent to the high-concentration drain region 116D is reduced in resistance by high-concentration doping.
5 is substantially L-shaped in the lower layer. On the other hand, the intermediate conductive film 181 is different from the capacitance line 175 in the first interlayer insulating film 4.
1 and is formed so as to cover the capacitance line 175 in the X direction as described above. Therefore, as shown in FIG. 7B or FIG. 7C, the storage capacitor 119 is obtained by parallelizing two capacitors. Specifically, the storage capacitor 119 uses the region 30f as one electrode,
A first capacitor formed by sandwiching the insulating film 32 formed on the surface of the semiconductor layer 30 using the capacitor line 175 as the other electrode;
The intermediate conductive film 181 is used as one electrode, and the capacitor line 175 is used as the other electrode, and is connected in parallel with a second capacitor sandwiching the first interlayer insulating film 41. For this reason, the storage capacitor 119 is increased in capacity as compared with the case of a single capacitor, so that the retention characteristics of the liquid crystal capacitance are improved and the display quality is improved.

Note that an alignment film 61 made of an organic film such as polyimide is formed on the entire surface of the uppermost layer (that is, the surface in contact with the liquid crystal 108), and a rubbing process is performed before bonding with the counter substrate 102. Is done.

<Detailed Configuration of Peripheral Circuit> Next, regarding the details of the peripheral circuit, a partial area of the sampling circuit 150,
Each part of the scanning line driving circuit 130 will be described as an example. Note that, as will be described in detail in a later manufacturing process, the active elements and wirings constituting the peripheral circuit are formed by the TFTs 116 and the scanning lines 112 (and the capacitance lines 17) in the display area.
5), the intermediate conductive film 181 and the data line 114 are formed by a common process.

In the display area 101a, the wiring is formed in the order of the scanning line 112 (and the capacitance line 175), the intermediate conductive film 181, and the data line 114. Therefore, in the following description, the wiring of the peripheral circuit will be described. Of which, scanning line 1
A wiring formed of the same layer as the conductive layer forming the layer 12 is referred to as a first layer wiring, a wiring formed of the same layer as the conductive layer forming the intermediate conductive film 181 is referred to as a second layer wiring, and A wiring formed of the same layer as the conductive layer forming the data line 114 is referred to as a third-layer wiring. Since the conductive layer forming the intermediate conductive film 181 has not been used in the peripheral circuit region in the past, the third layer wiring in this embodiment corresponds to the second layer wiring in the conventional electro-optical device. Will do.

As described above, when the wiring of three layers from the first layer to the third layer is used in the peripheral circuit, the degree of freedom in designing the peripheral circuit is limited to the wiring of only two layers. Than in each stage. Further, by using the wiring of the second layer as described below, it is possible to reduce the wiring resistance and the circuit formation region.

<Area Around the Sampling Circuit> First, a partial area of the sampling circuit 150 will be described with reference to FIG.
This will be described with reference to FIG. Here, the relationship between the sampling signal Sj output corresponding to the j-th block from the left and the path from the six image signal lines 122 to the six data lines 114 belonging to the block is shown. The explanation will be focused on. Note that j is for generalizing and explaining a block as in the description of FIG. 2, and is an integer from “1” to “n” in the present embodiment.

FIG. 8A is a plan view showing the detailed configuration of this area. First, the sampling signal Sj output from the data line driving circuit 140 is connected to a third layer wiring 391,
The wiring is supplied through a route of a lower wiring 191, a third wiring 393, and six first wirings 412. Here, the wirings are connected to each other via a contact hole, and the wiring 412 in the first layer serves as a gate electrode of a TFT constituting the sampling switch 151 as it is.

On the other hand, of the image signals VID1 to VID6, the image signal VID1 is supplied to the sampling switch 151 through the following route. That is, the image signal VID1 is output from the image signal line 122 formed of the third layer, the lower layer wiring 193, the third layer wiring 395, and the lower layer wiring 195.
In addition, the signal is supplied to the source region of the TFT constituting the sampling switch 151 via a path of a wiring 397 of the third layer. The sampling switches 15 for the other image signals VID2 to VID6 are also routed through similar paths.
1 is supplied to the source region of the TFT constituting the TFT 1. Then, the TFT constituting each sampling switch 151
Are connected to the data lines 114 of the third layer, respectively.
Is connected.

As described above, the wirings of the third layer are used in principle for the various wirings of the sampling circuit 150, except for the parts that intersect with the wirings of the third layer and the parts that are used as the gate electrodes. Is used.

Here, a sectional structure taken along line DD ′ in FIG. 8A will be described with reference to FIG. 8B. As shown in this figure, the image signal VID1 is branched from the image signal line 122 to which the image signal VID1 is supplied.
The wiring 193 that intersects the lower wiring is a parallel wiring in which the wiring 112b of the first layer and the wiring 181b of the second layer are connected in parallel. Specifically, the wiring 181b is connected in parallel to the wiring 112b through the contact holes ₅₅ 1, 56 ₁ of opening the first interlayer insulating film 41 at both ends. Further, the image signal line 122 to the image signals VID1 is supplied, the wiring through a contact hole 55 ₂ provided in the same position as the contact hole 55 ₁ 18
While connected to the 1b, the wiring 395, contact holes 56 ₂ provided in the contact hole 56 ₁ and the same position
Is connected to the wiring 181b via the.

Note that the wiring 193 branched from the image signal line 122 to which the image signals VID2 to VID6 other than the image signal VID1 are supplied also includes the first layer wiring 112b and the second layer wiring 181b. It is a parallel wiring connected in parallel. Further, in addition to the wiring 193 that branches and crosses from the image signal line 122, the sampling signal Sj
Similarly, the wiring 195 for intersecting with the wiring 393 to which is supplied is a parallel wiring in which the wiring 112c of the first layer and the wiring 181c of the second layer are connected in parallel.

Here, in the sampling circuit 150, the parallel wiring of the first layer wiring and the second layer wiring is used for the wirings 193 and 195 for the following reason. That is, the image signals VID1 to VID6 are
Since it is an analog signal that is finally applied to 8 and directly defines the display state, it is desirable that the supply path thereof has a low resistance at least. For this reason, the third layer made of aluminum is used for the image signal line 122,
About the wiring branched from here,
Layers other than layers must be used. Therefore, in the related art, a wiring made of a conductive layer forming the scanning line 112, that is, a wiring of the first layer has been used in this portion.
However, since the first layer is made of polysilicon or the like as described above, compared to aluminum or the like forming the third layer,
It has a much higher resistance. For this reason, even if the wiring length of the first layer is very small, the influence of the resistance is so large that it cannot be ignored.

Thus, in the present embodiment, the image signal VID
In a portion of the supply path of 1 to VID6 where a wiring made of a layer other than the third layer must be used, the second layer originally used in the display area is used in the peripheral circuit area, and the second layer is used in the peripheral circuit area. The two-layer wiring and the first-layer wiring are connected in parallel. For this reason, the resistance value of the portion is reduced to about half as compared with the case of a single-layer wiring. Therefore, in the present embodiment, the image signals VID1 to VID6 are supplied to the data line 114 while preventing waveform blunting and voltage drop in the supply path, and thus, good display is possible.

As shown in FIG. 8A, the parallel wiring 193 branched from the image signal line 122 has substantially the same length over each of the image signals VID1 to VID6.
They have substantially the same width. This is because in the present embodiment, the wiring 193 is composed of the first layer wiring 112b and the second layer wiring 181b.
Although the wiring resistance is reduced as compared with the wiring of the third layer, the resistance value of the wiring 193 is reduced by the image signal VID1.
This is a measure for making them equal to each other over VID6.

The wiring 191 for supplying the sampling signal Sj to intersect with the image signal line 122, which deviates from the supply path of the image signals VID1 to VID6, similarly has a first layer wiring and a second layer wiring. Are connected in parallel. This is because the supply path of the sampling signal Sj is required to have as low a resistance as possible, from the viewpoint of preventing delay due to waveform blunting of the sampling signal Sj.

As described above, in the present embodiment, a low-resistance third-layer wiring is used in principle for various wirings of the sampling circuit 150, while a portion that must intersect with the third-layer wiring is used in the sampling circuit 150. In addition, a parallel wiring of a first layer wiring and a second layer wiring is used. Here, looking at the entire peripheral circuit, the part where parallel wiring should be used in this way is as follows.
Wirings 191, 193 in the sampling circuit 150,
There are many other than 195. For example, the precharge control line 163 in FIG. 2 must branch to the gate electrode of the TFT constituting each precharging switch 161, but after the branch, it must cross the precharge voltage signal line 165. Exists.
The capacitance line 175 is the same wiring of the first layer as the scanning line 112 in the display area 100a. However, in the other area, the capacitance line 175 is connected to the mounting terminal 107 for common connection. It must be composed of three layers of wiring. For such a capacitance line 175, a precharge control line 163, a precharge voltage signal line 165,
Have parts that must intersect as shown in FIG. Further, in the scanning line driving circuit 130,
The power supply voltage Vd
It is necessary to supply the clock signal CLY and the inverted clock signal CLYinv together with dY and VssY. Therefore, the clock signal CLY and the inverted clock signal CL
As for the wiring branched from the main wiring of Yinv, there is a portion that must intersect at least the wiring to which the power supply voltages VddY and VssY are supplied. Similarly, in the data line driving circuit 140, the unit circuits forming the shift register include, together with the power supply voltages VddX and VssX,
Clock signal CLX and inverted clock signal CLXinv
It is necessary to supply enable signals ENB1 and ENB2 together with power supply voltages VddX and VssX to each AND circuit. Therefore, the clock signal CLX
In addition, the wiring branched from the main wiring of the inverted clock signal CLXinv and the wiring branched from the main wiring of the enable signals ENB1 and ENB2 need to intersect with at least the wiring to which the power supply voltages VddY and VssY are supplied, respectively. Exists. Then, by using the parallel wiring in which the wiring of the first layer and the wiring of the second layer are connected in parallel to the portion that must intersect with the wiring of the third layer, the resistance of the portion is reduced. It becomes possible.

<Partial Region of Scanning Line Drive Circuit> Next, a partial region of the scan line drive circuit 130 will be described with reference to FIGS. 9A and 9B. Here, FIG.
FIG. 3 is a plan view showing a configuration of a partial region of the scanning line driving circuit 130, and FIG. 3B is a diagram showing an equivalent circuit thereof. The area shown in the figure is the scanning line driving circuit 130.
Transfer start pulse DY in the shift register
The clock signal CLY and the inverted clock signal CLYin
A circuit for transferring data according to v is partially extracted.

As shown in FIG. 9A, the scanning line driving circuit 130 uses first, second, and third layers of wiring. In this region, the wiring of the third layer is used in principle. However, the exception is that the wiring of the first layer is used for the portion that intersects with the wiring of the third layer and the portion that is used as the gate electrode. And one T
The second layer wiring 181d is used for part of the wiring from the source electrode of the FT to the drain electrode of the other TFT. In particular, in the region 132, the first-layer wiring 112d,
The second-layer wiring 181d and the third-layer wiring 114d are formed so as to be stacked on each other via an interlayer insulating film (not shown here).

Here, in the scanning line driving circuit 130,
Unlike the sampling circuit 150 described above, the second layer wiring 181d is used alone and the three layers of wiring are formed in the same region for the following reason. That is, the data line driving circuit 130 outputs the sampling signal S
1, S2,..., Sn are connected to six data lines 114, respectively.
Since the data is supplied every time, the unit circuit and the AND circuit of the shift register included in the data line driving circuit 130 need only be contained within a pitch six times the data line pitch in FIG. 8A. On the other hand, since the scanning line driving circuit 130 must supply the scanning signals G1, G2,..., Gm to each of the m scanning lines 112, the shift register constituting the scanning line driving circuit 140 Of the unit circuit and the AND circuit must be kept within the same pitch as the scanning line pitch in FIG. 9A. That is, in the scanning line driving circuit 130, the unit circuit and the logical product circuit must be formed in a narrower area than the data line driving circuit 140. Here, temporarily
When three wirings are formed only from the first and third layers without using the wiring 181d in the second layer, one wiring is formed from the first layer, and the remaining two wirings are formed from the third layer. However, in this case, it is impossible to form two layers of the third layer in the same region. For this reason, in the different regions, the third layer wirings must be formed side by side, so that a wider region is required. Therefore, in such a configuration,
This is contrary to the requirement that the unit circuit and the AND circuit constituting the scanning line driving circuit 130 must be formed in a smaller area. On the other hand, in the present embodiment, the second-layer wiring 181d is used alone, and the first-layer wiring 112d, the second-layer wiring 181d, and the third-layer wiring 114d are connected in the same region 132 by (interlayer). When they are formed to overlap with each other (after insulation is achieved via an insulating film), the width of a region required for forming a circuit can be reduced.

In the scanning line driving circuit 130,
Parallel wiring of the first-layer wiring and the second-layer wiring is provided in a portion where the width of the region required for circuit formation is not required to be narrow and which must intersect with the third-layer wiring. Of course, it may be used.

<Manufacturing Process> Next, the manufacturing process of the electro-optical device according to the present embodiment will be described.
The following description focuses on the display area and the peripheral circuit area. Note that, as the peripheral circuit region here, in FIG. 8B, a region near a wiring 193 that branches off from one image signal line 122 and intersects another image signal line 122 is exemplified. .

First, as shown in FIG. 10A, a base insulating film 40 is formed on the surface of a substrate 10 such as a quartz substrate, a glass substrate, or a silicon substrate. For details,
The base insulating film 40 is formed, for example, by a normal pressure method or a low pressure CVD (Chemic
al Vapor Deposition), NSG (non-doped silicate glass), PSG (phosphorus silicate glass), BSG (boron silicate glass), BPS
From high insulating glass such as G (boron phosphorus silicate glass), or silicon oxide film, silicon nitride film, etc.
About 50-1500 nm thick, preferably about 600-500 nm
It is formed with a thickness of about 800 nm.

Subsequently, the entire upper surface of the base insulating film 40 is
For example, an amorphous silicon layer is formed with a thickness of about 100 nm by a low pressure CVD method or the like, and a polysilicon layer is formed by solid phase growth by heat treatment or the like.
At this time, when forming an N-channel TFT, Sb
In the case of forming a P-channel TFT while doping an impurity of a group V element such as (antimony), As (arsenic), or P (phosphorus) by ion implantation or the like,
Al (aluminum), B (boron), Ga (gallium)
Similarly, an impurity of a group III element such as is doped slightly by ion implantation or the like. Then, as shown in FIG. 2B, the polysilicon layer is patterned by photolithography or etching to form the semiconductor layer 30 of the TFT 116 in the display region in an island shape.
At this time, in the peripheral circuits as a whole, the semiconductor layers of the TFTs constituting the scanning line driving circuit 130, the data line driving circuit 140, the sampling circuit 150, and the precharge circuit 160 are formed in the same manner. In addition, TFT11
In the region 30f of the sixth semiconductor layer 30 where the capacitance line 175 is formed, an impurity such as P (phosphorus) may be doped at a high concentration to reduce the resistance in advance.

Further, as shown in FIG.
The surface of the semiconductor layer 30 is thermally oxidized to form the gate insulating film 3.
2 is formed on the surface of the semiconductor layer 30. By this step, the semiconductor layer 30 finally has a thickness of about 30 to 150 nm, preferably about 35 to 45 nm, while the gate insulating film 32 has a thickness of about 60 to 150 nm, preferably about 30 nm. It will be.

Next, a polysilicon layer is deposited on the upper surfaces of the gate insulating film 32 and the base insulating film 40 by a low pressure CVD method or the like. Then, as shown in FIG. 11 (4), the polysilicon layer is patterned by photolithography, etching, or the like, and TF is formed in the display region.
A scanning line 112 also serving as a gate electrode of T116 and a capacitance line 175 forming the other electrode in the storage capacitor 119 are formed. In the peripheral circuit region, a parallel wiring 193 is formed.
Is formed. That is, in the entire peripheral circuit, the first layer wiring including the gate electrode is formed.

Subsequently, the semiconductor layer 30 is doped with an appropriate impurity as shown in FIG. Specifically, when the TFT 116 in the display region is an N-channel type, the channel region 3 of the source / drain region
A region adjacent to Oa is doped at a low concentration with an impurity of a group V element such as P using a gate electrode which is a part of the scanning line 112 as a diffusion mask. At the same time, the N-channel TFT in the entire peripheral circuit is similarly doped with an impurity at a low concentration using the gate electrode, which is a part of the wiring of the first layer, as a diffusion mask. Subsequently, a resist wider than the gate electrode is formed, and using this as a mask, an impurity of a group V element such as P is similarly doped at a high concentration. As a result, the N-channel type TFT becomes the channel region 3
0a, a low-concentration source region 30b and a high-concentration source region 116S are provided on the source side, while a low-concentration drain region 30c and a high-concentration drain region 1c are provided on the drain side.
16D are provided to form an LDD structure. Although not shown, the semiconductor layer 3 of these N-channel TFTs
After masking 0 with a resist, P
Similarly, for the channel type TFT, a region adjacent to the channel region is doped with an impurity of a group III element such as B (boron) using the gate electrode which is a part of the wiring of the first layer as a mask. A high-concentration region is formed by using a resist wider than the gate electrode as a mask, and then doping with an impurity of a group III element such as B. Also, each channel type TFT is set to L
Instead of the DD structure, a TFT having an offset structure may be used, or a simple self-aligned (self-aligned) TFT may be used.

Next, as shown in FIG. 6 (6), the first interlayer insulating film 41 is formed so as to cover the scanning lines 112, the first-layer wirings 112b, the semiconductor layer 30, the base insulating film 40 and the like.
Is deposited by, for example, a CVD method or the like. As a material of the first interlayer insulating film 41, like the base insulating film 40, a silicate glass film such as NSG, PSG, BSG, BPSG, a silicon nitride film, a silicon oxide film and the like can be mentioned.

Further, as shown in FIG.
In the display area the contact hole 51, a contact hole 55 _1, 56 ₁ for In the peripheral circuit region connected to the wiring 112b of the first layer, formed respectively by dry etching or the like. Specifically, the contact hole 51 is formed in the high concentration drain region 116D of the TFT 116.
At a position corresponding to, while being a first interlayer insulating film 41 and the gate insulating film 32 so as to opening the contact holes 55 _1, 56 _1, the first layer wiring 112
b, the first interlayer insulating film 41
It is formed so as to open a hole. In the case where the first layer wiring and the second layer wiring are to be electrically connected in the entire peripheral circuit, contact holes (not shown) are similarly formed corresponding to the conductive portions.

Next, a conductive layer made of a high melting point metal, metal silicide, polysilicon or the like is formed on the first interlayer insulating film 41 by sputtering or the like for about 50 to 50 minutes.
Deposit with a thickness of 500 nm, preferably about 200 nm. It goes without saying that the conductive layer may be formed of a high melting point metal or metal silicide and polysilicon in multiple layers. Thereby, stress relaxation of the conductive layer and reduction of the resistance of the contact hole can be realized. Then, this conductive layer is patterned by photolithography, etching, or the like as shown in FIG.
While forming as an intermediate conductive film 181 connected to D,
In the peripheral circuit area, the other wiring 181b of the parallel wiring 193 is formed. That is, the wiring of the second layer is formed in the entire peripheral circuit.

Subsequently, as shown in FIG. 9G, the second interlayer insulating film 42 is formed so as to cover the intermediate conductive film 181, the second-layer wiring 18b, and the first interlayer insulating film 41. , CV
It is deposited to a thickness of about 500 to 1500 nm by D method or the like. Note that the material of the second interlayer insulating film 42 is NSG similarly to the base insulating film 40 and the first interlayer insulating film 41.
And a silicate glass film such as PSG, BSG, and BPSG, a silicon nitride film, a silicon oxide film, and the like.

Next, as shown in FIG.
A contact hole 52 in the display area, in the peripheral circuit region contact holes 55 _2, 56 ₂ for connecting to the wiring 181b of the second layer, are formed respectively. Specifically, the contact hole 52 is
At a position corresponding to the high concentration source region 116S of
The second interlayer insulating film 42, while being formed so as to opening the first interlayer insulating film 41 and the gate insulating film 32, contact holes ₅₅ 2, 56 _2, the second layer wiring 181b
Are formed so as to open the second interlayer insulating film 42 at both end positions. In the case where the second layer wiring and the third layer wiring are to be electrically connected in the entire peripheral circuit, contact holes (not shown) are similarly formed corresponding to the conductive portions.

Further, contact holes 52, 55 ₂ ,
On the second interlayer insulating film 42 56 ₂ is formed, a conductive film made of a low resistance metal such as aluminum, by sputtering, is deposited to a thickness of about 50 to 500 nm. Then, this conductive film is patterned by photolithography, etching, or the like, as shown in FIG. 11A, to form a data line 114 also serving as a source electrode of the TFT 116 in the display region, while In the circuit area, the wiring 391 and the image signal line 1
22. That is, the wiring of the third layer is formed in the entire peripheral circuit.

Subsequently, as shown in FIG. 13 (12), a third interlayer insulating film 43 is formed by a CVD method or the like so as to cover the third layer wiring such as the data line 114 and the image signal line 122. Deposit to a thickness of about 500-1500 nm.
The material of the third interlayer insulating film 43 includes a base insulating film 40, a first interlayer insulating film 41, and a second interlayer insulating film 4.
As in the case of 2, a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like is used.

Next, as shown in FIG.
The contact hole 53 is formed at a predetermined position in the intermediate conductive film 181 by the third interlayer insulating film 43 and the second interlayer insulating film 43.
Is formed by dry etching or the like so as to open the interlayer insulating film 42 of FIG.

Then, on the surface of the third interlayer insulating film 42 in which the contact hole 53 is formed, a transparent conductive film such as ITO is formed by sputtering or the like for about 50 to 200.
After being deposited to a thickness of nm, the pixel electrode 118 is patterned into a predetermined shape (see FIG. 5) by photolithography, etching or the like, and as shown in FIG.
To form Although illustration of subsequent steps is omitted, an organic solution such as polyimide is applied to the pixel electrode 118 and the third interlayer insulating film 43 which are to be opposed surfaces on the substrate 10.
Is applied and baked on the entire surface of the substrate. As a result, the alignment film 61 is formed. The alignment film 61 is subjected to a rubbing process in a predetermined direction.

The element substrate 1 formed as described above
A liquid crystal 105 is sealed and sealed with a counter substrate 102 that has been rubbed in a direction rotated about 90 degrees from the counter substrate 102 by a sealing material 104, and the electric liquid 01 shown in FIG. It becomes an optical device.

In the element substrate 101, the alignment film 61 is formed over the entire surface. After the liquid crystal is sealed, the alignment film 61 is formed in the peripheral circuit region by plasma processing or the like, in a portion protruding from the counter substrate 102. The alignment film is removed. Therefore, the uppermost layer in the peripheral circuit region is not the alignment film 61 but the third interlayer insulating film 43.

According to such a manufacturing method, the intermediate conductive film 181 used as a barrier film for the high-concentration drain region 116D of the TFT 116 in the display region.
It is possible to use a conductive film of the same layer as the wiring of the second layer in the peripheral circuit without adding a special process. Further, by using three layers of wiring, the degree of freedom in designing peripheral circuits can be improved in each stage. In addition, by connecting in parallel with the wiring of the first layer, the resistance of the wiring can be reduced, and by using the wiring of the second layer alone, the wiring of the three layers in the same region can be obtained. Can be formed.

<Application Example> In the embodiment described above, when the third layer wiring is connected to the parallel wiring of the first layer wiring and the second layer wiring, the third layer wiring is It was configured to be connected to the second layer wiring. For example, FIG.
In (b), the image signal line 122 is connected to the parallel wiring 193.
Of these, the configuration was such that it was connected to the second-layer wiring 181b.

As described above, when the second conductive layer is made of a high melting point metal or the like in which stress is likely to be generated (prone to warpage), the contact hole for connecting to the wiring 181b of such a high melting point metal is used. 55 _2, 56 when ₂ to opening, the second interlayer insulating film by the stress concentration caused by the opening 42
Cracks and the like may occur. Further, the contact holes ₅₅ 2, 56 _2, the second layer wiring 181
When b is exposed, impurities are diffused from the wiring 181b, which causes a defect.

Therefore, the wiring of the third layer is replaced with the wiring 11 of the first layer.
When connecting to one end of the parallel wiring 193 of the wiring 2b and the wiring 181b of the second layer, for example, as shown in FIG. 15A, the wiring 181b of the second layer is connected to the contact hole 57 ₁ slightly inside, 58 are connected ₁ to the first wiring 112b through, with the parallel lines 193, configured to connect the wires of the third layer, the wiring 112b of the first layer through the outer contact hole 57 ₂ or 58 ₂ Is desirable. In this configuration, after the second interlayer insulating film 42 is formed, the wiring 181b of the second layer is not exposed. Therefore, stress concentration due to the opening of the contact hole does not occur, so that cracks in the second interlayer insulating film 42 are prevented, and diffusion of impurities from the wiring 181b is also prevented.

Further, the parallel wiring 193 is the first wiring 1
Although the connection is established only at both ends of the second wiring 12b and the second wiring 181b, as shown in FIG. 15B, the contact holes 58 are formed at one or more points other than both ends.
It is also possible to provide a connection 59 at this point to provide a more reliable connection between the two wirings. Note that even in the configuration in which the connection between the first wiring 112b and the second wiring 181b is performed through one or more contact holes other than both ends, the wiring in the third layer is connected through the outer contact hole. May be connected to the first layer wiring 112b.

<Others> In the above embodiment, the six data lines 114 are grouped into one block, and the six data lines 114 belonging to one block are converted into six systems. The image signals VID1 to VID6 are simultaneously sampled and supplied, but the number of conversions and the number of data lines to be simultaneously applied (that is, the number of data lines constituting one block) are not limited to “6”. . For example, if the response speed of the sampling switch 151 in the sampling circuit 150 is sufficiently high, the image signal is serially transmitted to one image signal line without converting the image signal into parallel, and dot-sequentially for each data line 114. It may be configured to perform sampling. In addition,
In such a configuration, the shift register and the logical product circuit constituting the data line driving circuit 140 must be formed at the same size as the data line pitch.
Like 0, it may be necessary to use the second layer wiring alone.

Further, assuming that the number of data lines to be converted and applied at the same time is “3”, “12”, “24”, etc., three, twelve, twenty-four data lines, etc. , 12-system conversion, 24-system conversion, etc., may be simultaneously supplied. The number of conversions and the number of data lines to be applied simultaneously are 3
A multiple of 3 is preferable from the viewpoint of simplicity of control and circuits in relation to being composed of signals related to two primary colors. However, in the case of a simple light modulation application such as a projector to be described later, a multiple of 3 is not required.
Further, instead of controlling a plurality of sampling switches at the same time, the image signals VID1 to VID1 converted in parallel are converted.
The VID 6 may be sequentially shifted and supplied, and the sampling switch 151 may be sequentially controlled.

In the above-described embodiment, the scanning line 112 is scanned from the top to the bottom, and the block is selected from the left to the right. However, the block may be selected in the opposite direction. Alternatively, a configuration in which any direction can be selected depending on the application may be used.

Further, in the above-described embodiment, the planar type TFT 116 and the like are formed on the element substrate 101, but the present invention is not limited to this. For example, TF
T116 may be a bottom gate type. Further, the element substrate 101 may be formed of a semiconductor substrate, and a field effect transistor may be formed here instead of the TFT 116. Furthermore, SOI (Silicon On Insulato)
By applying the technique of r), a silicon single crystal film may be formed on an insulating substrate of sapphire, quartz, glass, or the like, and various elements may be formed therein to form the element substrate 101. However, when the element substrate 101 does not have transparency, it is necessary to use the liquid crystal panel 100 as a reflective type by forming the pixel electrode 118 with aluminum or separately forming a reflective layer.

In the above-described embodiment, a TN type liquid crystal is used, but a BTN (Bi-stable Twisted Nemati
c) Bistable type with memory properties such as type and ferroelectric type,
A dye (guest) having a polymer dispersed type and further having anisotropy in absorption of visible light in the major axis direction and the minor axis direction of a molecule is dissolved in a liquid crystal (host) having a fixed molecular arrangement to form a dye molecule. May be used as a guest-host type liquid crystal in which are arranged in parallel with liquid crystal molecules.

The liquid crystal molecules are aligned vertically with respect to both substrates when no voltage is applied, while the liquid crystal molecules are aligned horizontally with respect to both substrates when voltage is applied. It may be configured,
When a voltage is not applied, the liquid crystal molecules are arranged in a horizontal direction with respect to both substrates, while when a voltage is applied, the liquid crystal molecules are arranged in a direction perpendicular to both substrates. good. As described above, the present invention can be applied to various types of liquid crystal or alignment method.

In addition, as electro-optical devices, in addition to liquid crystal devices, various electro-optical devices which perform display by the electro-optical effect using electroluminescence (EL), fluorescence by plasma emission or electron emission, etc. Applicable to At this time, the electro-optical material is an EL, a mirror device, a gas, a phosphor, or the like. Note that in the case where EL is used as the electro-optical material, the EL on the element substrate 101 is
Therefore, the counter substrate 102 becomes unnecessary. Thus, the present invention is applicable to all electro-optical devices having a configuration similar to the above-described configuration.

<Electronic Equipment> Next, some electronic equipment using the electro-optical device according to the above-described embodiment will be described.

<Part 1: Projector> First, a projector using the above-described liquid crystal panel 100 as a light valve will be described. FIG. 16 is a plan view showing the configuration of this projector. As shown in this figure, inside the projector 2100, a lamp unit 2102 including a white light source such as a halogen lamp is provided. The projection light emitted from the lamp unit 2102 is separated into three primary colors of RGB by three mirrors 2106 and two dichroic mirrors 2108 disposed inside, and the light valve 100 corresponding to each primary color is separated.
R, 100G and 100B respectively. Here, the configuration of the light valves 100R, 100G, and 100B is the same as that of the liquid crystal panel 100 according to the above-described embodiment, and the primary colors of R, G, and B supplied from a processing circuit (not shown) that inputs image signals. Each is driven by a signal. In addition, since the light of B color has a longer optical path compared to the other R and G colors, in order to prevent the loss, the light of B color is transmitted through a relay lens system 2121 including an entrance lens 2122, a relay lens 2123, and an exit lens 2124. Be guided.

Now, the light valves 100R, 100G,
The lights modulated by 100B respectively enter dichroic prism 2112 from three directions. And
In the dichroic prism 2112, the R and B lights are refracted at 90 degrees, while the G light travels straight. Therefore, after the images of each color are combined, a color image is projected on the screen 2120 by the projection lens 2114.

Since light corresponding to each of the primary colors R, G and B is incident on the light valves 100R, 100G and 100B by the dichroic mirror 2108, it is not necessary to provide a color filter as described above. The transmitted images of the light valves 100R and 100B are projected after being reflected by the dichroic mirror 2112, whereas the transmitted images of the light valve 100G are projected as they are.
Is inverted left and right with respect to the display image by the light valve 100G.

<Part 2: Mobile Computer> Next, an example in which the above-described liquid crystal panel 100 is applied to a mobile personal computer will be described. Figure 1
FIG. 7 is a perspective view showing the configuration of this personal computer. In the figure, a computer 2200 includes a main body 2204 having a keyboard 2202 and a liquid crystal panel 100 used as a display. A backlight unit (not shown) for improving visibility is provided on the back surface of the liquid crystal panel 100.

<Part 3: Mobile Phone> An example in which the above-described liquid crystal panel 100 is applied to a display unit of a mobile phone will be described. FIG. 18 is a perspective view showing the configuration of the mobile phone. In the figure, a mobile phone 2300 includes a plurality of operation buttons 2302, an earpiece 2304, a mouthpiece 2
The liquid crystal panel 100 described above is provided together with the liquid crystal panel 100 described above. A back light unit (not shown) for improving visibility is also provided on the back of the liquid crystal panel 100.
Is provided.

As the electronic equipment, FIGS.
In addition to those described with reference to FIG. 18 and FIG. 18, a liquid crystal television, a viewfinder type / monitor direct-view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, a word processor, a workstation, a videophone, a POS terminal , A digital still camera, a device equipped with a touch panel, and the like. It goes without saying that the electro-optical device according to the embodiment and the applied form can be applied to these various electronic devices.

[0153]

As described above, according to the present invention, it is possible to use a wiring made of the same conductive layer as the intermediate conductive film used to connect the other end of the switching element and the pixel electrode in the display area. Thus, the degree of freedom in designing peripheral circuits can be improved.

[Brief description of the drawings]

FIG. 1A is a perspective view showing a configuration of a liquid crystal panel of an electro-optical device according to an embodiment of the present invention, and FIG.
FIG. 3A is a cross-sectional view taken along line AA ′ of FIG.

FIG. 2 is a block diagram showing an electrical configuration of the liquid crystal panel.

FIG. 3 is a diagram showing an equivalent circuit in a display area of the liquid crystal panel.

FIG. 4 is a timing chart for explaining the operation of the liquid crystal panel.

FIG. 5 is a timing chart for explaining the operation of the liquid crystal panel.

FIG. 6 is a plan view showing a detailed configuration of a pixel in a display area of the liquid crystal panel.

7A is a cross-sectional view taken along the line BB ′ in FIG. 6, FIG. 7B is a cross-sectional view taken along the line CC ′ in FIG. 5, and FIG. 5 is an equivalent circuit showing the configuration of the storage capacitor in FIG.

FIG. 8A is a plan view showing a configuration near a sampling circuit of the liquid crystal panel, and FIG.
It is sectional drawing of the D 'line.

FIG. 9A is a plan view illustrating a partial configuration of a scanning line driving circuit of the liquid crystal panel, and FIG. 9B is a diagram illustrating an electrical configuration thereof.

FIGS. 10A to 10C are cross-sectional views illustrating a manufacturing process of an element substrate in the liquid crystal panel.

FIGS. 11 (4) to (6) are cross-sectional views each showing a manufacturing process of an element substrate in the same liquid crystal panel.

FIGS. 12 (7) to (9) are cross-sectional views each showing a manufacturing process of an element substrate in the same liquid crystal panel.

FIGS. 13A to 13C are cross-sectional views illustrating a manufacturing process of an element substrate in the liquid crystal panel.

FIGS. 14A and 14B are cross-sectional views illustrating a manufacturing process of an element substrate in the same liquid crystal panel.

FIGS. 15A and 15B are cross-sectional views each showing a configuration near a sampling circuit of an electro-optical device according to a modified example of the invention.

FIG. 16 is a plan view illustrating a configuration of a projector as an example of an electronic apparatus to which the electro-optical device according to the embodiment is applied.

FIG. 17 is a perspective view showing a configuration of a personal computer as an example of the electronic apparatus.

FIG. 18 is a perspective view showing a configuration of a mobile phone as an example of the electronic apparatus.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Substrate 30 ... Semiconductor layer 40 ... Base insulating film 41 ... First interlayer insulating film 42 ... Second interlayer insulating film 43 ... Third interlayer insulating film 61 ... Alignment film 100 ... Liquid crystal panel 101 ... Element substrate 102 ... Counter substrate 105 ... Liquid crystal 108 ... Counter electrode 112 ... Scan line 112b, 112c, 112d ... Wiring 114 ... Data line 114b, 114c, 114d ... Wiring 116 ... TFT 118 ... Pixel electrode 119 ... Storage capacitance 122 ... Image signal line 130 ... Scanning Line drive circuit 140 Data line drive circuit 150 Sampling circuit 151 Sampling switch 160 Precharge circuit 161 Precharge switch 175 Capacitance line 181 Intermediate conductive film 191, 193, 195 Wiring 181b, 181c, 181d Wirings 391, 393, 395 ... Wiring 2100 ... Projector 2200: Personal computer 2300: Mobile phone

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H01L 29/786 H01L 29/78 612C

Claims (30)

[Claims] A plurality of scanning lines and a plurality of data lines; a pair of a switching element and a pixel electrode provided corresponding to an intersection of the scanning line and the data line; a switching element and a corresponding pixel electrode And a peripheral circuit for driving each of the switching elements, including an interconnect made of the same layer as the conductive layer constituting the intermediate conductive film. Electro-optical device characterized. 2. The intermediate conductive film is electrically connected through a first contact hole provided corresponding to an electrode of a switching element, while the pixel electrode is electrically connected through a second contact hole. 2. The electro-optical device according to claim 1, wherein the electro-optical device is electrically connected. 3. One end is connected to the pixel electrode,
2. The electro-optical device according to claim 1, wherein a storage capacitor having the other end connected in common is provided for each pixel electrode, and the intermediate conductive film forms a part of an electrode forming the storage capacitor. 4. The intermediate conductive film has a light-shielding property, and a part of light transmitted or reflected by the pixel electrode is defined by the intermediate conductive film. An electro-optical device according to claim 1. 5. An electro-optical device having a first, a second and a third conductive layer formed in this order, wherein the third conductive layer has a lower resistance than the first conductive layer. A plurality of scanning lines made of the first conductive layer; a plurality of data lines made of the third conductive layer and formed so as to intersect with the plurality of scanning lines; A pair of a switching element and a pixel electrode provided corresponding to an intersection of a line and the data line; and a second conductive layer for electrically connecting the switching element and the corresponding pixel electrode. An electro-optical device, comprising: a conductive film; and wirings each including the first, second, and third conductive layers, and a peripheral circuit for driving each of the switching elements. 6. The intermediate conductive film is electrically connected via a first contact hole provided corresponding to an electrode of a switching element, while the pixel electrode is electrically connected via a second contact hole. The electro-optical device according to claim 5, wherein the electro-optical device is electrically connected. 7. The peripheral circuit has a parallel wiring in which a wiring made of the first conductive layer and a wiring made of the second conductive layer are electrically connected in parallel. 6. The electro-optical device according to 5. 8. The parallel wiring, wherein the parallel wiring is a branch wiring branched from a wiring made of the third conductive layer, and is used at a portion crossing a wiring different from the wiring. 8. The electro-optical device according to 7. 9. The peripheral circuit includes the third conductive layer, and includes h image signal lines that supply image signals corresponding to h (h is an integer of 2 or more) data lines. A corresponding one of the image signals supplied to the h image signal lines is provided according to a predetermined sampling signal and supplied to the corresponding data line. The electro-optical device according to claim 7, further comprising a sampling switch, wherein the parallel wiring is used for at least a part of a wiring branched from the image signal line and reaching the sampling switch. 10. A wiring formed of the second conductive layer in the parallel wiring, and a third and fourth contact hole exposing a wiring formed of the first conductive layer in the parallel wiring, respectively. Between the third or fourth conductive layer and the wiring made of the third conductive layer.
8. The electro-optic device according to claim 7, wherein the electro-optic device is provided at a position corresponding to the first contact hole and is electrically connected to a fifth contact hole exposing a wiring made of the second conductive layer. 9. apparatus. 11. A wiring formed of the second conductive layer in the parallel wiring, and a third and a fourth contact hole exposing a wiring formed of the first conductive layer in the parallel wiring, respectively. The wiring made of the third conductive layer is connected to the third and fourth conductive layers.
8. The electro-optical device according to claim 7, wherein the electro-optical device is provided at a position different from the first contact hole and is electrically connected to a sixth contact hole exposing a wiring made of the first conductive layer. apparatus. 12. The first conductive layer of the parallel wiring, wherein the wiring made of the second conductive layer is provided in one or a plurality of contact holes provided between the third and fourth contact holes. The electro-optical device according to claim 10, wherein the electro-optical device is electrically connected to a wiring made of a layer. 13. The electro-optical device according to claim 5, wherein the peripheral circuit includes a wiring made of the first, second, and third conductive layers in a part of the peripheral circuit. 14. A storage capacitor having one end connected to the pixel electrode and the other end commonly connected is provided for each pixel electrode, and the intermediate conductive film forms a part of an electrode forming the storage capacitor. The electro-optical device according to claim 5, wherein: 15. The storage capacitor comprises: a first capacitor having a gate oxide film of the switching element sandwiched between the electrode of the switching element and a capacitance line formed of the second conductive layer; and the intermediate conductive film. And a second capacitor having an interlayer insulating film sandwiched between the capacitor and the capacitor line.
5. The electro-optical device according to 4. 16. The intermediate conductive film has a light-shielding property, and a part of light transmitted or reflected by the pixel electrode is defined by the intermediate conductive film. An electro-optical device according to claim 1. 17. The electro-optical device according to claim 5, wherein the first conductive layer is made of polysilicon. 18. The electro-optical device according to claim 5, wherein the third conductive layer is made of aluminum. 19. The electro-optical device according to claim 5, wherein the second conductive layer is made of a material having a higher melting point than a material forming the third conductive layer. 20. A plurality of scanning lines and a plurality of data lines; a pair of a switching element and a pixel electrode provided corresponding to an intersection of the scanning line and the data line; a switching element and a corresponding pixel electrode An intermediate conductive film electrically connecting between the semiconductor device, a peripheral circuit for driving each of the switching elements, and a wiring connected to the peripheral circuit and formed of the same layer as a conductive layer forming the intermediate conductive film. An electro-optical device, comprising: 21. The electro-optical device according to claim 20, wherein the wiring crosses an image signal line formed of the same layer as a conductive layer forming the data line in a lower layer. 22. The image signal line, wherein a plurality of image signal lines are provided, and the wirings are connected corresponding to the respective image signal lines, and the size of each wiring is substantially the same. 22. The electro-optical device according to claim 21. 23. A first conductive layer formed of the same layer as the conductive layer forming the data line, and formed at a position separated from the first conductive layer formed of the same layer as the conductive layer forming the data line. A third conductive layer, comprising a same layer as the semiconductor layer of the switching element.
The electro-optical device according to claim 20, wherein the conductive layer is electrically connected to the first conductive layer and the second conductive layer via a contact hole. 24. The electro-optical device according to claim 23, wherein the wiring is electrically connected to the third conductive layer via a contact hole. 25. The electro-optical device according to claim 24, wherein the third conductive layer is made of polysilicon. 26. The electro-optical device according to claim 24, wherein there are at least three contact holes for electrically connecting the wiring and the third conductive layer. 27. An image signal line comprising the same layer as the conductive layer forming the data line is disposed between the first conductive layer and the second conductive layer.
An electro-optical device according to claim 1. An electronic apparatus comprising the electro-optical device according to any one of claims 1 to 27. 29. A method of manufacturing an electro-optical device including a plurality of scanning lines and a pair of pixel electrodes corresponding to intersections of the plurality of scanning lines, wherein the scanning lines and the data lines are provided. Forming a switching element in a portion to be crossed; forming an intermediate conductive film connected to the switching element; and forming a wiring used for a peripheral circuit for driving each of the switching elements from the same conductive layer. And a step of forming a pixel electrode connected to the intermediate conductive film. 30. A method for manufacturing an electro-optical device comprising a plurality of scanning lines and a pair of pixel electrodes corresponding to intersections of the plurality of scanning lines, the method comprising: After forming a wiring used for a peripheral circuit for driving each from the first conductive layer, and after forming a switching element at a portion where the scanning line and the data line should intersect, Forming an intermediate conductive film connected to a switching element and a wiring used for the peripheral circuit from a second conductive layer, and forming the data line and a wiring used for the peripheral circuit from a third conductive layer, respectively And a step of forming a pixel electrode connected to the intermediate conductive film.