JP2002026155A - Semiconductor storage device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To actualize a floating gate memory which is free of writing errors causing readout destruction, even if a tunnel insulating film is made thin as to a semiconductor storage device. SOLUTION: This device has a doped 1st channel part 13A, which operates at write and erase time between a source region 24S and a drain region 24D, a 1st tunnel insulating film 14A which covers the 1st channel part 13A and has thickness allowing a carrier directly tunnel, a 2nd channel part 13B which operates at reading time between the source region 24S and drain region 24D and is doped to decrease density lower than the 1st channel part 13A, a 2nd tunnel insulating film 14B which covers the 2nd channel part 13B and allows a carrier to directly tunnel and is thicker than the 1st tunnel insulating film, a floating gate 15 which is present on each tunnel insulating film, and a control gate 17 which is formed on the floating gate 15 across a control gate insulating film 16.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a semiconductor memory device effective for suppressing read destruction of a gate memory and a method for manufacturing the same.

[0002]

2. Description of the Related Art At present, it goes without saying that the progress of the information society is remarkable. Due to its influence, further increase in the density of semiconductor memory devices is demanded.

In recent years, flash memories have the advantage of not requiring refreshing, and are in the state of being used in many electronic devices. In order to realize the voltage operation, the high writing voltage and the erasing voltage are a bottleneck.

[0004] Usually, in a flash memory, the thickness is 1 unit.
A high voltage of about ± 10 [V] must be applied to tunnel carriers between the channel and the floating gate through a tunnel oxide film of about 0 [nm].

In order to solve such a problem that a high voltage must be applied, a floating gate memory using a thin tunnel oxide film has been proposed. The thickness of the tunnel oxide film is about 3 nm. With such a thickness, the carrier can be directly tunneled at a low voltage, for example, ± 5 [V] or less.

However, in a flash memory, if the thickness of the tunnel gate oxide film is simply reduced, carriers accumulated in the floating gate are lost by tunneling to the extension portions of the source region and the drain region. The retention time of the stored information is shortened.

In order to avoid such a problem, there has been proposed a flash memory in which the floating gate does not overlap with the extension portions of the source region and the drain region.

FIG. 24 is a cutaway side view showing a main part of a floating gate memory having a thin tunnel oxide film. In FIG. 24, reference numeral 1 denotes a substrate, 2 denotes a thin gate oxide film, and 3 denotes a thin gate oxide film.
Represents a floating gate, 4 represents a control gate, 5 represents a source region, 5A represents an extension portion of a source region, 6 represents a drain region, and 6A represents an extension portion of a drain region.

FIG. 25 is a diagram for explaining the operation of the floating gate memory. The horizontal axis represents the control gate voltage V _g [V], and the vertical axis represents the drain current I.
_D [A] is taken. It should be noted that the extra electrons in the figure are those when compared with the thermal equilibrium state.

In this floating gate memory, electrons can flow in and out through the thin gate oxide film 2 between the floating gate 3 and the channel between the extension 5A of the source region and the extension 6A of the drain. Do.

[0011] To perform a read, so that sensing the magnitude of current due to some floating gate 3 in electrons when the control gate voltage V _g = 1 [V] degree.

One of the problems with this floating gate memory is that when reading a state where there is no extra electron in the floating gate, that is, when a current flows through the memory, the tunnel oxide film is thin. Channel electrons tunnel to the floating gate and are accumulated as extra electrons in the floating gate. That is, erroneous writing occurs due to read destruction.

FIG. 26 is an energy band diagram for explaining the read destruction, and the same symbols as those used in FIG. 24 represent the same parts or have the same meanings.

In the figure, for the sake of simplicity, only the lower end of the conduction band is shown.
Tunneling to the floating gate 3 through the thin tunnel oxide film 2 causes the threshold value to shift positively.

[0015]

SUMMARY OF THE INVENTION In the present invention, there is provided a floating gate memory which does not cause erroneous writing which leads to readout destruction even if the gate tunnel insulating film is thinned so that carriers can be tunneled at a low voltage. And

[0016]

According to the present invention, a channel through which a current flows at the time of writing and erasing has a high threshold voltage, a thin tunnel insulating film, and a channel through which a current flows at the time of reading. Low threshold voltage,
In addition, the tunnel insulating film is basically based on a thick semiconductor memory device.

FIGS. 1A and 1B are main part explanatory views showing a semiconductor memory device for explaining the principle of the present invention. FIG. 1A is a cutaway side view of a main part, FIG. 1B is a plan view of a main part, and FIG. (B) shows a cut surface along a line YY seen in (B).

In the figure, 11 is a substrate, 12 is an insulating layer,
13A is a first channel portion (substrate upper surface side channel),
13B is a second channel portion (shallow trench side channel), 14A is a thin tunnel insulating film (first tunnel insulating film), 14B is a thick tunnel insulating film (second tunnel insulating film), and 15 is a floating gate. , 16 is a control gate insulating film, 17 is a control gate, 19 is an insulating film, 20P is a gate pad, 20W
Is a sidewall made of polycrystalline Si, and 23W is Si
A sidewall made of O ₂ , 24S a source region,
24D is the drain region, 25 is the control gate
Contact electrodes are shown.

In the semiconductor memory device shown in FIG. 1, since the surface of the substrate 11 in contact with the thin tunnel insulating film 14A is subjected to heavy channel doping, the threshold value is high and the thick tunnel insulating film is thick. Substrate 11 in contact with 14B
Has a low threshold value because of the thin channel doping.

Accordingly, in FIG. 1, the first channel portion (channel on the upper surface of the substrate) 13A shows a high threshold value, and the second channel portion (channel on the shallow trench side) 13B has a low threshold value. It is configured to indicate a value.

FIGS. 2A and 2B are cutaway side views for explaining the operation of the semiconductor memory device shown in FIG. 1, wherein FIG. 2A shows a read operation, FIG. 2B shows a write operation, and FIG. The same symbols as those shown and used in FIG. 1 represent the same parts or have the same meaning.

At the time of reading (see FIG. 2A) A voltage of, for example, 1.0 [V] is applied between the source and the drain, and a voltage of, for example, 1.0 V is applied to the control gate contact electrode 25 and, therefore, the control gate 17. [V]
Is applied.

When the gate voltage is applied, the second channel portion 13B is turned on. The carrier flowing through the second channel portion 13B is connected to the floating gate 15 because the tunnel insulating film 14B is thick. It does not flow in and therefore no erroneous writing occurs.

Here, when electrons are accumulated in the floating gate 15, the current flowing between the source and the drain is small, and when the electrons are not accumulated, the current flowing becomes large. It can be performed.

At the time of writing (see FIG. 2B) A case where a positive voltage of 3 [V] to 5 [V] is applied to the control gate 15 and a bias condition of 0 [V] is applied between the source and the drain. Since the first channel portion 13A is also turned on, the carrier tunnels through the thin tunnel insulating film 14A and enters the floating gate 15, so that writing is performed.

At the time of erasing (see FIG. 2 (C)).
When a negative voltage of [V] to -5 [V] is applied and a bias condition of 0 [V] is applied between the source and the drain, electrons accumulated in the floating gate 15 pass through the thin tunnel insulating film 14A. Erasing is performed because the channel is tunneled to the channel.

As is apparent from the above description, in the floating gate memory according to the present invention,
Writing and erasing can be performed at a relatively low voltage by the action of a channel having a thin tunnel insulating film, and a channel having a thick tunnel insulating film acts for reading. Does not occur.

[0028]

FIG. 3 to FIG. 13 are main part explanatory views showing a semiconductor memory device in important steps for explaining a process of manufacturing the semiconductor memory device according to the first embodiment.
(A) is a main part plane, (B) is a main part cut side surface along line XX of (A), (C) is a main part cut side surface along line YY of (A), and hereinafter, Description will be made with reference to these figures.

FIG. 3 3- (1) Resist process in lithography technology and
RIE (reacti) using HBr as an etching gas
By applying a part etching method, the Si semiconductor substrate 11 is etched using a resist film (not shown) as a mask to form a shallow trench 11A having a depth of about 100 [nm]. In the figure, the adjacent portions are omitted, so that the shallow trench 11A
Is represented as a notch.

See FIG. 4 4- (1) CVD (chemical vapor deposition)
The thickness is 100 [n] by applying the method.
m] of the insulating layer 12 made of SiO ₂ .

Referring to FIG. 5, 5- (1) the insulating layer 12 is etched by applying the RIE method using CF ₄ as an etching gas. In this case, over-etching is performed and the Si substrate 11 is etched. Of course, the side surface is exposed in the shallow trench 11A.

The surface of the Si semiconductor substrate 11 exposed here becomes a channel on the upper surface of the substrate, that is, the first channel portion 13A after the impurity for threshold adjustment is introduced later. Is about 50 [nm], and this portion is later doped with a threshold adjusting impurity to form a shallow trench side channel, that is, a second channel portion 13B.

FIG. 6 6- (1) By applying the ion implantation method, the ion acceleration energy is 5 [keV] and the dose is 1.2 × 10 ¹³ [cm ⁻² ].
B ⁺ is implanted as a degree,
The implantation is performed from a direction inclined by about 70 ° from a direction perpendicular to the Si semiconductor substrate 11.

In the case described above, the incident angle of B ⁺ is larger on the side surface of the shallow trench than on the surface of the Si semiconductor substrate 11. 11 and low at the sides of the shallow trench.

FIG. 7 7- (1) By applying the thermal oxidation method, an insulating film on which carriers can be directly tunneled is formed on the surface of the Si semiconductor substrate 11 and the side surfaces of the shallow trenches. Since the side surfaces of the shallow trench have damage during etching, the oxidation rate is higher than that of the surface of the Si semiconductor substrate 11, and therefore, the surface of the Si semiconductor substrate 11,
That is, if the thin tunnel insulating film 14A formed on the first channel portion 13A is about 3 [nm], it naturally becomes about 5 [nm] on the second channel portion 13B and is thick. This becomes the tunnel insulating film 14B.

7- (2) The thin tunnel insulating film 1 is formed by applying the CVD method.
N ⁺ polycrystalline S having a thickness of about 100 nm on 4A
A floating gate 15 made of i is formed.

7- (3) A control gate insulating film 16 made of SiO ₂ having a thickness of about 5 [nm] is formed on the floating gate 15 made of polycrystalline Si by applying the thermal oxidation method. I do.

7- (4) A control gate 17 made of n ⁺ polycrystalline Si having a thickness of about 100 [nm] is formed on the control gate insulating film 16 by applying the CVD method.

FIG. 8 8- (1) By applying a resist process in the lithography technique, a portion from the buried insulating layer 12 to the surface which is laminated and reaches the surface is formed into a stripe mesa. A resist layer 18 is formed.

8- (2) HBr (for Si), CF ₄ (SiO
Etching from the surface of the control gate 17 to the surface of the buried insulating layer 12 is performed by applying the RIE method ( ₂ ).

9- (1) Resist layer 18 used as a mask for mesa etching
Is removed, an insulating layer 19 made of SiO ₂ having a thickness of about 5 [nm] is formed by applying a thermal oxidation method.

9- (2) An n ⁺ polycrystalline Si having a thickness of about 80 nm on a flat portion on the insulating layer 19 by applying the CVD method.
The layer 20 is formed.

10- (1) A resist film 21 is formed to cover a portion where a gate pad is to be formed by applying a resist process in lithography.

10- (2) HBr (for Si) and CF ₄ (S
By applying the RIE method (for iO ₂ ), n ⁺
Anisotropic etching of the polycrystalline Si layer 20 and the insulating layer 19 is performed to perform side wall 20W made of n ⁺ polycrystalline Si.
To form The side wall 20W also functions as a control gate, and plays a role of eliminating the overlap between the floating gate and the source / drain.

11- (1) Resist film 2 covering portion where gate pad is to be formed
1 is removed to expose the gate pad 20P. 11- (2) By applying the ion implantation method, the ion acceleration energy is set to 5 [keV], the dose is set to about 4 × 10 ¹⁴ [cm ⁻² ], and As ⁺ is implanted to extend the extension source region 22S. And extension drain region 2
Form 2D.

Referring to FIG. 12, 12- (1) S of 80 nm thick is formed by applying the CVD method.
After an insulating film made of iO ₂ is formed, the insulating film is anisotropically etched to form a sidewall 23W by applying a RIE method using CF ₄ as an etching gas.

12- (2) By applying the ion implantation method, the ion acceleration energy is about 40 [keV] and the dose is 2 × 10 ¹⁵ [c
m ^-2] performed As ⁺ implant to form the source region 24S and drain region 24D as about.

13- (2) A resist process in the sputtering method and the lithography technique, and RI in which the etching gas is Cl-based gas
By applying the E method, the thickness is, for example, 50 [nm].
And Ti having a thickness of, for example, 400 nm
1 is formed, and the control gate 1 is formed.
7 and the gate pad 20P. The gate pad 20P is also coupled to a side wall 20W made of n ⁺ polycrystalline Si that functions as a control gate.

In the semiconductor memory device manufactured through the above steps, the channel on the shallow trench side, that is, the second channel portion 1 is formed due to channel doping.
The threshold voltage of 3B is lower although the tunnel insulating film 14B is formed thicker.

Therefore, if the gate voltage at the time of reading is set to a voltage value between the threshold voltage of the second channel portion 13B and the channel on the substrate upper surface side, that is, the threshold voltage of the first channel portion 13A, Since the current flows only through the second channel portion 13B, and the tunnel insulating film 14B on the second channel portion 13B is thick, no carrier tunneling to the floating gate 15 occurs, and no read breakdown occurs.

Further, by setting the gate voltage at the time of writing to a voltage higher than the threshold voltage of the first channel portion 13A, current is supplied to both the first channel portion 13A and the second channel portion 13B. Flows, and the carrier flows through the floating gate 15 through the thin tunnel insulating film 14A.
To tunnel.

FIGS. 14 to 23 are main part explanatory diagrams showing the semiconductor memory device in the main steps for explaining the steps of manufacturing the semiconductor memory device according to the second embodiment.
Is a main part plane, (B) is a main part cut side surface along line XX of (A), (C) is a main part cut side surface along line YY of (A). Although the description will be made with reference to the drawings, in the description of the first embodiment, the steps described with reference to FIGS. The steps will be described.

Referring to FIG. 14, 14- (1) By applying the thermal oxidation method, an insulating film is formed on the surface of the Si semiconductor substrate 11 and on the side surfaces of the shallow trenches so that carriers can be directly tunneled. Side surface of the shallow trench, that is, the second channel portion 13B
A thick tunnel insulating film 26B having a thickness of about 5 [nm]
Is formed.

14- (2) By applying the CVD method, an n ⁺ polycrystalline Si layer 27 having a thickness enough to sufficiently fill the shallow trench is formed.

14- (3) By applying the RIE method using HBr as an etching gas, the thick tunnel insulating film 26B is formed and S
The polycrystalline Si layer 27 is etched until a thin tunnel insulating film formed on the surface of the i semiconductor substrate 11 is exposed.

14- (4) The Si semiconductor substrate 11 is immersed in a hydrofluoric acid-based etchant.
The thin tunnel insulating film formed on the surface of the substrate is removed.

15- (1) By applying the thermal oxidation method, the thickness of 3 nm is formed on the surface of the Si semiconductor substrate 11 and the surface of the n ⁺ polycrystalline Si layer 27 filling the shallow trench. ] Is formed.

15- (2) By applying a resist process in the lithography technique, an opening 28A corresponding to the n ⁺ polycrystalline Si layer 27 filling the shallow trench is provided, and the active region is covered. A resist layer 28 is formed.

See FIG. 16. 16- (1) Wet / hydrofluoric acid etchant is used as an etchant.
By applying the etching method, the thin tunnel insulating film 26A is etched using the resist film 28 as a mask, and the n ⁺ polycrystalline Si layer 2 filling the shallow trench is formed.
Make 7 appear.

16- (2) After removing the resist film 28, a floating gate 29 made of W having a thickness of about 100 [nm] is formed by applying the CVD method.

Referring to FIG. 17, 17- (1) Ta ₂ having a thickness of about 10 [nm] is formed on floating gate 29 made of W by applying the CVD method.
A control gate insulating film 30 made of O ₅ is formed.

17- (2) A control gate 31 made of n ⁺ polycrystalline Si having a thickness of about 100 [nm] is formed on the control gate insulating film 30 by applying the CVD method.

18- (1) By applying a resist process in the lithography technique, a portion from the buried insulating layer 12 to the surface thereof, which is laminated and reaches the surface, is formed into a mesa shape of a stripe. A resist pattern 32 is formed.

18- (2) HBr (for Si), CF ₄ (Ta ₂
Etching from the surface of the control gate 31 to the surface of the buried insulating layer 12 is performed by applying the RIE method of using O ₅ (for O ₅ ) and Cl ₂ (for W).

19- (1) After removing the resist pattern 32 used as a mask for the mesa-forming etching, Ta ₂ O having a thickness of about 5 [nm] is obtained by applying a CVD method. _An insulating layer 33 of ₅ is formed.

19- (2) By applying the CVD method, n ⁺ polycrystalline Si having a thickness of about 80 nm on a flat portion on the insulating layer 33
The layer 34 is formed.

Referring to FIG. 20, 20- (1) A resist film 35 covering a portion where a gate pad is to be formed is formed by applying a resist process in lithography.

20- (2) Anisotropic etching of the n ⁺ polycrystalline Si layer 34 is performed by applying the RIE method using HBr as an etching gas to form a side wall 34W made of n ⁺ polycrystalline Si.
To form It is needless to say that the side wall 34W also functions as a control gate and plays a role of eliminating the overlap between the floating gate and the source / drain. The insulating layer 33 made of Ta ₂ O ₅ formed on the substrate 11 and the insulating layer 12
Remains as is.

Referring to FIG. 21 21- (1) Resist film 3 covering a portion where a gate pad is to be formed
5 is removed to expose the gate pad 34P.

[0070] 21- (2) depending on applying an ion implantation method, an ion acceleration energy 5 [keV], extension performs As ⁺ implantation as 4 × 10 ¹⁴ [cm ^-2] about the dose Source region 36S and extension / drain region 3
Form 6D.

See FIG. 22. 22- (1) By applying the CVD method, an 80 nm thick S
After an insulating film made of iO ₂ is formed, the insulating film is anisotropically etched to form a side wall 37W by applying a RIE method using CF ₄ as an etching gas. At this time, the insulating layer 33 made of Ta ₂ O ₅ on the substrate 11 is removed together with the SiO ₂ .

22- (2) By applying the ion implantation method, the ion acceleration energy is about 40 [keV] and the dose is 2 × 10 ¹⁵ [c
m ^-2] performed As ⁺ implant to form the source region 38S and drain region 38D as about.

Referring to FIG. 23, 23- (2) a resist process in a sputtering method and a lithography technique, and R in which an etching gas is a Cl ₂ -based gas.
By applying the IE method, an electrode 39 made of TiN having a thickness of about 50 [nm] and Al having a thickness of about 400 [nm] is formed, and the control gate 31 and the gate pad 34P are electrically connected. Connecting. The gate pad 34P is also connected to a side wall 34W made of n ⁺ polycrystalline Si that functions as a control gate.

In the semiconductor memory device according to the second embodiment formed through the above steps, W is used as the material of the floating gate 29 facing the channel on the upper surface of the substrate, ie, the first channel portion 13A. ing.

In this case, due to the difference in work function between Si and W, the first channel portion 13A and the shallow trench side channel, that is, the second channel portion 13A are formed.
Even if the doping profile of B is exactly the same,
The threshold voltage in the first channel portion 13A becomes higher.

Therefore, with respect to the first embodiment, the channel doping means described with reference to FIG.
In the case where the first channel portion 13A and the second channel portion 13B have different doping profiles, the semiconductor memory device of the second embodiment is
Compared with the semiconductor memory device of the first embodiment, the difference in threshold voltage is larger and the operation margin is larger.

The present invention can be embodied in many forms, including the above-described embodiment, and will be exemplified below as additional notes.

(Appendix 1) Source (for example, source region 24)
S) and a first channel portion (for example, the first channel portion 13A) which is provided between the drain (for example, the drain region 24D) and which is used for writing and erasing information and which is channel-doped; A first tunnel insulating film (for example, the first tunnel insulating film 1) having a thickness covering the first channel portion and having a thickness capable of directly tunneling the carrier;
4A) and a second channel portion (e.g., a second channel portion) which acts between the source and the drain to read information and is lightly doped compared to the first channel portion. A portion 13B) and a second tunnel insulating film (for example, the second tunnel insulating film 14) which covers the second channel portion and is thicker than the first tunnel insulating film.
B), a floating gate (eg, floating gate 15) formed on the first and second tunnel insulating films, and a control gate insulating film (eg, control gate insulating film 16) on the floating gate. And a control gate (for example, control gate 17) formed through the semiconductor memory device. (1)

(Supplementary Note 2) A first channel portion between the source and the drain, which acts when writing and erasing information, and a thickness covering the first channel portion and allowing the carrier to directly tunnel. A first tunnel insulating film between the source and the drain, the second channel portion acting when reading information, and the first tunnel insulating film covering the second channel portion. A second tunnel insulating film thicker than the first tunnel insulating film, a portion formed on the first and second tunnel insulating films and located on the first tunnel insulating film and on the second tunnel insulating film. A floating gate in which the first portion is made of a material having a different work function (for example, W and Si) and the threshold voltage of the first channel portion is higher than the threshold voltage of the second channel portion; And the float The semiconductor memory device characterized by comprising a control gate formed over the control gate insulating film on the ring gate. (2)

(Supplementary Note 3) The first channel portion is located on the upper surface of the substrate, and the second channel portion is located on the side surface of a shallow trench connected to the upper surface of the substrate (Supplementary Note 1). Alternatively, the semiconductor memory device according to (Supplementary Note 2).
(3)

[0081]

In the semiconductor memory device according to the present invention, the channel through which a current flows at the time of writing and erasing has a high threshold voltage, the tunnel insulating film is thin, and the current flows at the time of reading. It is based on that the channel through which the current flows has a low threshold voltage and the tunnel insulating film has a large thickness.

By employing the above configuration, writing and erasing can be performed at a relatively low voltage by the action of the channel having the thin tunnel insulating film, and the channel having the thick tunnel insulating film acts for reading. Therefore, an erroneous write that leads to read destruction does not occur.

[Brief description of the drawings]

FIG. 1 is an essential part explanatory view showing a semiconductor memory device for explaining a principle of the present invention;

FIG. 2 is a fragmentary side view for explaining the operation of the semiconductor memory device shown in FIG. 1;

FIG. 3 is an essential part explanatory view showing the semiconductor memory device in a process essential point for describing a process of manufacturing the semiconductor memory device according to the first embodiment;

FIG. 4 is an essential part explanatory view showing the semiconductor memory device in a process essential point for describing a process of manufacturing the semiconductor memory device according to the first embodiment;

FIG. 5 is an explanatory diagram of a main part of the semiconductor memory device in a process key point for describing a process of manufacturing the semiconductor memory device according to the first embodiment;

FIG. 6 is an essential part explanatory view showing the semiconductor memory device in a process essential point for describing a process of manufacturing the semiconductor memory device according to the first embodiment;

FIG. 7 is a fragmentary side view showing the semiconductor memory device at a key step in the process of manufacturing the semiconductor memory device according to the first embodiment;

FIG. 8 is an essential part explanatory view showing the semiconductor memory device in a process essential point for explaining a process of manufacturing the semiconductor memory device according to the first embodiment;

FIG. 9 is an explanatory diagram of a main part of the semiconductor memory device in a process key point for describing a process of manufacturing the semiconductor memory device according to the first embodiment;

10 is an essential part explanatory view showing the semiconductor memory device at a key step in the process of manufacturing the semiconductor memory device according to the first embodiment; FIG.

FIG. 11 is an explanatory diagram of a main part of the semiconductor memory device in a process key point for describing a process of manufacturing the semiconductor memory device according to the first embodiment;

FIG. 12 is an essential part explanatory view showing the semiconductor memory device in a process essential point for explaining a process of manufacturing the semiconductor memory device according to the first embodiment;

FIG. 13 is an essential part explanatory view showing the semiconductor memory device at a key step in the process of manufacturing the semiconductor memory device according to the second embodiment;

FIG. 14 is an explanatory diagram of a main part of a semiconductor memory device in a process key point for describing a process of manufacturing the semiconductor memory device according to the second embodiment;

FIG. 15 is an essential part explanatory view showing the semiconductor memory device in a process essential point for describing a process of manufacturing the semiconductor memory device according to the second embodiment;

FIG. 16 is an essential part explanatory view showing a semiconductor memory device in a process essential point for describing a process of manufacturing the semiconductor memory device according to the second embodiment;

FIG. 17 is an essential part explanatory view showing a semiconductor memory device in a process essential point for describing a process of manufacturing the semiconductor memory device according to the second embodiment;

FIG. 18 is an essential part explanatory view showing the semiconductor memory device at a key step in the process of manufacturing the semiconductor memory device according to the second embodiment;

FIG. 19 is an essential part explanatory view showing a semiconductor memory device in a process essential point for explaining a process of manufacturing the semiconductor memory device according to the second embodiment;

FIG. 20 is an essential part explanatory view showing the semiconductor memory device in a process essential point for describing a process of manufacturing the semiconductor memory device according to the second embodiment;

FIG. 21 is an essential part explanatory view showing the semiconductor memory device at a key step in the process of manufacturing the semiconductor memory device according to the second embodiment;

FIG. 22 is an essential part explanatory view showing the semiconductor memory device in a process essential point for describing a process of manufacturing the semiconductor memory device according to the second embodiment;

FIG. 23 is an essential part explanatory view showing the semiconductor memory device in a process essential point for describing a process of manufacturing the semiconductor memory device according to the second embodiment;

FIG. 24 shows a floating tunnel having a thin tunnel oxide film.
It is a principal part cut-away side view showing a gate memory.

FIG. 25 is a diagram for explaining the operation of the floating gate memory;

FIG. 26 is an energy band diagram for explaining read destruction.

[Explanation of symbols]

Reference Signs List 11 substrate 11A shallow trench 12 insulating layer 13A first channel portion 13B second channel portion 14A thin tunnel insulating film (first tunnel insulating film) 14B thick tunnel insulating film (second tunnel insulating film) 15 floating Gate 16 Control gate insulating film 17 Control gate 18 Resist layer 19 Insulating layer 20 n ⁺ Polycrystalline Si layer 20P Gate pad 20W Side wall 21 Resist film 22S Extension source region 22D Extension drain region 23W Side wall 24S Source region 24D Drain region 25 Control gate contact electrode

Claims (3)

[Claims] A first channel portion which is provided between a source and a drain and which is used for writing and erasing information and which is channel-doped, and which covers the first channel portion and is directly connected to a carrier. A first tunnel insulating film having a thickness capable of being tunneled and having a lower concentration than the first channel portion, acting between the source and the drain to read information; A second channel portion, a second tunnel insulating film covering the second channel portion and being thicker than the first tunnel insulating film, and formed on the first and second tunnel insulating films. A floating gate, and a control gate formed on the floating gate with a control gate insulating film interposed therebetween. 2. A first channel portion between a source and a drain, which acts when writing and erasing information, and has a thickness covering the first channel portion and allowing a carrier to directly tunnel. A first tunnel insulating film, a second channel portion between the source and the drain, which operates when reading information, and covers the second channel portion and is compared with the first tunnel insulating film. A thick second tunnel insulating film; a portion formed on the first and second tunnel insulating films and located on the first tunnel insulating film; and a portion located on the second tunnel insulating film. A floating gate, wherein the threshold voltage of the first channel portion is higher than the threshold voltage of the second channel portion; Conte The semiconductor memory device characterized by comprising a control gate formed over the Lumpur gate insulating film. 3. The method according to claim 2, wherein the first channel portion is on a top surface of the substrate,
2. The semiconductor device according to claim 1, wherein the second channel portion is on a side surface of a shallow trench connected to the upper surface of the substrate.
Alternatively, the semiconductor memory device according to claim 2.