CN106328656A - Process method for adding ILD (Inter Layer Deposition) filling window of adjustable control gate poly - Google Patents
Process method for adding ILD (Inter Layer Deposition) filling window of adjustable control gate poly Download PDFInfo
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- CN106328656A CN106328656A CN201610703052.4A CN201610703052A CN106328656A CN 106328656 A CN106328656 A CN 106328656A CN 201610703052 A CN201610703052 A CN 201610703052A CN 106328656 A CN106328656 A CN 106328656A
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- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
Abstract
A process method for adding an ILD (Inter Layer Deposition) filling window of an adjustable control gate poly comprises the steps of providing a substrate with a cell memory region and a peripheral region; depositing a first poly gate layer on a surface of the substrate; growing a silicon oxide blocking layer on a surface of the first poly gate layer; performing photoresist coating and developing on a surface of the silicon oxide blocking layer to expose the peripheral region, and only etching to remove the silicon oxide blocking layer on the peripheral region; depositing second poly gate layers on surfaces of the silicon oxide blocking layer of the cell memory region and the first poly gate layer of the peripheral region; performing photoresist coating and developing on a surface of the second poly gate layers to expose the cell memory region, and etching to only remove the second poly gate layer on the cell memory region; etching to remove the remaining silicon oxide blocking layer; and performing photoresist coating and developing on surfaces of poly gates of the cell memory region and the peripheral region, and forming a final dual-poly gate structure by dry etching.
Description
Technical field
The present invention relates to IC manufacturing field, particularly relating to a kind of adjustable control grid increases the work of ILD filling window
Process.
Background technology
Floating gate type nonvolatile storage (Non-volatile memory is called for short NVM) is a kind of common integrated circuit device
Part, it includes a source electrode, a drain electrode, a gate pole and a floating boom (Floating Gate).Generally, classics can be used
Stacking gate technique (stack-gate) formed floating gate type Nonvolatile memory structure.Polysilicon layer near tunnel oxide is made
For floating boom, the polysilicon layer at top is as control gate (control gate poly), and the insulating barrier between two polysilicon layers is two
Silicon oxide or ONO (Oxide-Nitride-Oxide) structure, play the effect of isolation floating gate region.
Compared with volatile memory, due to the existence of floating boom, even if nonvolatile storage cuts out or non-transformer confession in system
At once remain to keep data message, be therefore widely used in flash memory.
In order to ensure erasing and the read or write speed of floating gate type Nonvolatile memory device, transistor is needed to possess bigger hitting
Wear voltage.In general, the energy improving lightly doped drain (Lightly Doped Drain, be called for short LDD) IMP can obtain relatively
High junction breakdown voltage, and high-octane LDD IMP is accomplished by thicker polysilicon gate and stops ion penetration.
Technique generally uses boiler tube (Furnace) process deposits to form at present, and thickness is right at 2000 Izods, passes through the most again
Dry etch process ultimately forms device control gate, and technological process is as shown in Figure 1.
Referring to Fig. 1, Fig. 1 is the schematic flow sheet forming device control gate in prior art.As it is shown in figure 1, the method
Comprise the steps:
Step S01: semiconductor base 100 is provided, this quasiconductor 100 substrate surface at least unit storage (cell
Memory) region and peripheral components (Peripheral) region.
Referring to Fig. 2, Fig. 2 is the structural profile schematic diagram after completing step S01 in Fig. 1.In figure, unit memory area bag
Include tunnel oxide 101, tunnel oxide is formed multi-crystal silicon floating bar 102, multi-crystal silicon floating bar is formed insulating barrier ONO103；Figure
In peripheral device region include gate oxide 105；This semiconductor base also include STI (Self-aligned Isolation,
Autoregistration shallow trench isolation) 104.
Step S02: form polysilicon gate 106 on semiconductor base 100 surface (as it is shown on figure 3, Fig. 3 is to complete step in Fig. 1
Structural profile schematic diagram after rapid S02).
Step S03: carry out photoresist coating and development on polysilicon gate 106 surface, forms final control through dry etching
(as shown in Figure 4, Fig. 4 ultimately forms the structural profile signal of device control gate to grid structure processed after completing step S03 in being Fig. 1
Figure).
At present, the peripheral device region of floating gate type nonvolatile storage and the control gate of unit memory area can use stove
Plumber's skill one step deposition forms, and thickness is typically right at 2000 Izods, and the unit memory area of floating gate type non-volatile memory device
In addition to having with the control gate of peripheral device region same thickness, also has the FGS floating gate structure of about 1000 angstroms of thickness, along with NVM
The continuous reduction of size, the depth-to-width ratio of the groove (space trench) of unit memory area substantially increases, at ILD (inter
Layer Deposition) during easily produce cavity (void), unit memory area groove be filled up completely with change very
Difficulty, this will have a strong impact on the reliability performance of device.
Summary of the invention
In order to overcome problem above, it is desirable to provide a kind of adjustable control grid increase the technique side that ILD fills window
Method, this technique can regulate control gate thickness according to demand.On the one hand, thinning control under conditions of not affecting peripheral components performance
Grid thickness processed effectively reduces the depth-to-width ratio of the unit memory area groove of unit memory area, and final realization is conducive to ILD to fill
Purpose；On the other hand, under conditions of not affecting peripheral components performance, thinning control gate thickness can improve ILD (inter
Layer Deposition) fill after the planarization of device surface, follow-up photoetching process.
For achieving the above object, technical scheme is as follows:
The present invention provides a kind of adjustable control grid to increase ILD and fills the process of window, comprising:
Step S1: semiconductor base, described semiconductor substrate surface at least unit memory area and a peripheral device are provided
Part region；
Step S2: deposit the first polycrystalline silicon grid layer at semiconductor substrate surface；
Step S3: in one layer of silica barrier layer of the first polycrystalline silicon grid layer superficial growth；
Step S4: carry out photoresist coating and development on silica barrier layer surface, expose peripheral device region, only etch
Remove the silica barrier layer of peripheral device region, remove remaining photoresist；
Step S5: on silica barrier layer and the first polycrystalline silicon grid layer surface of peripheral device region of unit memory area
Deposit the second polycrystalline silicon grid layer；
Step S6: carry out photoresist coating and development on the second polycrystalline silicon grid layer surface, exposes unit memory area, etching
Remove the second polycrystalline silicon grid layer of only unit memory area, remove remaining photoresist；
Step S7: etching removes remaining silica barrier layer；
Step S8: the polycrystalline silicon gate surface in unit memory area and peripheral device region carries out photoresist coating and shows
Shadow, forms final polysilicon dual gate structure through dry etching.
Preferably, the first polysilicon gate layer thickness formed in described step 2, depends on the control gate of unit memory area
Thickness, span is 100 angstroms～2500 angstroms.
Preferably, described step 2 use furnace process deposit the first polycrystalline silicon grid layer at semiconductor substrate surface.
Preferably, the silica barrier layer thickness formed in described step 3 is at 50 angstroms～500 angstroms.
Preferably, described silica barrier layer as remove described unit memory area polycrystalline silicon grid layer barrier layer, its
The process of growth is ISSG, boiler tube, RTO or CVD.
Preferably, the photoresist used in described step 4 is negative glue or positive glue, removes described peripheral boiler tube zone oxidation
The technique on silicon barrier layer is wet-etching technology.
Preferably, the described silica barrier layer at unit memory area and the first of peripheral device region in step 5
Polycrystalline silicon grid layer surface deposit the thickness of the second polycrystalline silicon grid layer depend on described first polycrystalline silicon grid layer thickness and described outside
The thickness requirements of peripheral device region polycrystalline silicon grid layer, span is 100 angstroms～2500 angstroms.
Preferably, described step 5 use furnace process at the silica barrier layer of unit memory area and peripheral components
The first polycrystalline silicon grid layer surface in region deposits the second polycrystalline silicon grid layer.
Preferably, the photoresist used in described step 6 is negative glue or positive glue, more than the second of described unit memory area
Crystal silicon gate layer uses dry etch process to remove.
Preferably, in described step 7, wet-etching technology is used to remove residual silicon oxide barrier layer.
From technique scheme it can be seen that the adjustable control grid that the present invention provides increase the technique side that ILD fills window
Method, it is possible to obtain the relatively thin control gate of unit memory area and the polysilicon dual gate structure of the thicker control gate of peripheral device region.Should
Structure can reach following effect:
1., the present invention can obtain simultaneously deposit compared with the unit of the peripheral device region of thick polysilicon grid and relatively thin polysilicon gate
The structure of the dual poly gate layer in storage area territory, effectively reduces the depth-to-width ratio of unit memory area groove, is not affecting peripheral components
The control gate thickness of thinning unit memory area under conditions of performance, effectively reduces the depth-to-width ratio of unit memory area groove,
Realize the purpose being conducive to ILD to fill eventually；
2., under conditions of not affecting peripheral components performance, the control gate thickness of thinning unit memory area can improve
The planarization of device surface, follow-up photoetching process after ILD (inter layer Deposition) filling；
3., can according to the polysilicon gate thickness of device requirement adjustment unit memory area and peripheral device region freely,
Technological process is the most controlled.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet forming device control gate in prior art
Fig. 2 is the structural profile schematic diagram after completing step S01 in Fig. 1
Fig. 3 is the structural profile schematic diagram after completing step S02 in Fig. 1
Fig. 4 be Fig. 1 completes step S03 after ultimately form the structural profile schematic diagram of device control gate
Fig. 5 is the schematic flow sheet forming device control gate in the embodiment of the present invention
Fig. 6 is the structural profile schematic diagram after completing step S1 in the embodiment of the present invention
Fig. 7 is the structural profile schematic diagram after completing step S2 in the embodiment of the present invention
Fig. 8 is the structural profile schematic diagram after completing step S3 in the embodiment of the present invention
Fig. 9 is the structural profile schematic diagram after completing step S4 in the embodiment of the present invention
Figure 10 is the structural profile schematic diagram after completing step S5 in the embodiment of the present invention
Figure 11 is the structural profile schematic diagram after completing step S6 in the embodiment of the present invention
Figure 12 is the structural profile schematic diagram after completing step S7 in the embodiment of the present invention
Figure 13 is the structural profile schematic diagram after completing step S8 in the embodiment of the present invention
Detailed description of the invention
Embodiment feature of present invention will describe with the embodiment of advantage in the explanation of back segment in detail.It it should be understood that the present invention
Can have various changes in different examples, it neither departs from the scope of the present invention, and explanation therein and being shown in
Substantially as purposes of discussion, and it is not used to limit the present invention.
Below in conjunction with accompanying drawing, by specific embodiment, the adjustable control grid of the present invention are increased the technique that ILD fills window
Method is described in further detail.It should be noted that the problem that the present invention solves is keeping peripheral device region thicker
While polycrystalline silicon grid layer, again can be with the control gate thickness of thinning unit memory area.
Below in conjunction with the accompanying drawings the detailed description of the invention of the present invention is described in detail.
Referring to Fig. 5, Fig. 5 is the schematic flow sheet forming device control gate in the embodiment of the present invention, as it can be seen, the party
The forming step of method may include that
Step S1: semiconductor base, described semiconductor substrate surface at least unit memory area and a peripheral device are provided
Part region.Specifically, as shown in Figure 6, the semiconductor base 200 in figure can use P-type semiconductor substrate (P
Substrate), the tunnel oxide 201 in figure can be silicon dioxide.Assuming to be formed in ISSG mode, its thickness can be
About 8nm.Floating boom 202 in figure is monocrystal silicon or polysilicon, such as, and 90nm polysilicon；Its group of interpolar oxide layer 203 in figure
One-tenth can be oxygen-nitrogen-oxygen or silicon dioxide, and in the present embodiment, the thickness of oxygen-nitrogen-oxygen oxide layer can be 11nm；In figure
Gate oxide 205 can be earth silicon material, in the present embodiment, can be to comprise 16.9nm and 3.8nm two kinds not simultaneously
The gate oxide of stack pile.
Step S2: deposit the first polycrystalline silicon grid layer at semiconductor substrate surface.Specifically, in the present embodiment, can in step 2
To use furnace process at full wafer semiconductor substrate surface uniform deposition the first polycrystalline silicon grid layer 206, in deposition process, step
The the first polysilicon gate layer thickness formed in 2 can be 100 angstroms～2500 angstroms (for example, 1150 angstroms), deposits the first polysilicon gate
The temperature of layer can be 620 degree Celsius.Referring to step S7, Fig. 7 is that the structure after completing step S2 in the embodiment of the present invention is cutd open
Face schematic diagram.
Step S3: in one layer of silica barrier layer of the first polycrystalline silicon grid layer superficial growth.In the present embodiment, oxide barrier
Layer can use RTO (Rapid Thermal Oxidation) or ISSG (In-Situ Steam Generation) and stove
Plumber's skill obtains.
It is assumed that use ISSG technique to be formed, oxide is SiO2, during forming silica barrier layer, technological temperature can
Thinking 1000C, thickness can be 10nm.It should be noted that this barrier oxide layers 207 is at subsequent etching (poly Etch)
During play the effect of protected location memory area the first polycrystalline silicon grid layer 206, and, deposit for being finally successfully formed unit
The polysilicon dual gate structure of storage area territory polysilicon gate thickness different with logic area, plays an important role.Referring to Fig. 8, Fig. 8 is
The embodiment of the present invention completes the structural profile schematic diagram after step S3.
Step S4: carry out photoresist coating and development on silica barrier layer surface, exposes peripheral device region, and etching is gone
Remove the silica barrier layer of only peripheral device region, remove remaining photoresist.
As it is shown in figure 9, the barrier oxide layers 207 of unit memory area retained, only remove peripheral device region
SiO2Barrier layer.Specifically, covered by photoresist at unit memory area, peripheral device region development is opened, and can use light
Carving method i.e. uses wet-etching technology the barrier oxide layers 207 of peripheral device region to be removed, and then, then will remain photoetching
Glue is removed, and ultimately forms unit memory area the first polycrystalline silicon grid layer 206 surface and covers silica barrier layer and peripheral components district
The first polycrystalline silicon grid layer 206 surface, territory does not has the structure of silica barrier layer 207.
In an embodiment of the present invention, this photoresist can use positive glue or negative glue, it is assumed that as a example by negative glue, wet etching
HF or BOE can be used, in the present embodiment as a example by BOE, and over etching (Over etch is called for short OE) 50%, outside guaranteeing
The residual of silica barrier layer 207 is not had between the two-layer polysilicon grid of peripheral device region.
Step S5: on silica barrier layer and the first polycrystalline silicon grid layer surface of peripheral device region of unit memory area
Deposit the second polycrystalline silicon grid layer.
As shown in Figure 10, at silica barrier layer and first polycrystalline silicon grid layer of peripheral device region of unit memory area
206 surfaces deposit the second polycrystalline silicon grid layer 209.This second polycrystalline silicon grid layer 209 still uses the boiler tube of the first polycrystalline silicon grid layer 206
Depositing operation.After wet processing cleans, in the of the silica barrier layer 207 of unit memory area and peripheral device region
One polycrystalline silicon grid layer 206 surface deposits the second polycrystalline silicon grid layer 209.In the present embodiment, it is assumed that temperature with 620C, thickness is
650A, the wet-cleaning before the second polycrystalline silicon grid layer 209 deposition can be on peripheral device region the first polycrystalline silicon grid layer 206 surface
Form the chemical oxide layer (chemical Oxide) 208 of thin layer.
So, through above step, final unit memory area is formed as substrate the-the first polycrystalline silicon grid layer-oxide resistance
The structure of barrier the-the second polycrystalline silicon grid layer, and peripheral device region be formed as substrate the-the first polycrystalline silicon grid layer-chemical oxide layer-
The structure of the second polycrystalline silicon grid layer.
Step S6: carry out photoresist coating and development on the second polycrystalline silicon grid layer surface, exposes unit memory area, etching
Remove the second polycrystalline silicon grid layer of only unit memory area, remove remaining photoresist.
As shown in figure 11, carry out photoresist coating and development on the second polycrystalline silicon grid layer 209 surface, expose unit memory block
Territory, etching is removed the second polycrystalline silicon grid layer 209 of only unit memory area, is removed remaining photoresist.Specifically, first, adopt
By photoetching process, being opened by unit memory area photoresist developing, peripheral device region photoresist covers；Then, dry method is used
Second polycrystalline silicon grid layer 209 of etching technics removal unit memory area, is parked in silica barrier layer 207；Finally, removal is surplus
Remaining photoresist, ultimately forms the structure that unit memory area is substrate the-the first polycrystalline silicon grid layer-silica barrier layer, and outer
Peripheral device region is then for the structure of substrate the-the first polycrystalline silicon grid layer-chemical oxide layer the-the second polycrystalline silicon grid layer.
After above-mentioned steps completes, the present invention is successfully realized the peripheral device region structural requirement compared with thick polysilicon grid.?
In the present embodiment, it is added final thickness with two-layer polysilicon grid and can be 1750 angstroms.In this step, removal unit memory area
The second polycrystalline silicon grid layer 209 after, it is also possible to carry out the ion implantation technology of polysilicon gate with regulation polysilicon (poly)
Resistance.
Step S7: etching removes remaining silica barrier layer.As shown in 12, wet-etching technology is used to remove remaining
Silica barrier layer 207.This wet-etching technology can use in HF or BOE, this enforcement still as a example by BOE, wet etching mistake
In journey, OE is still 50%, to guarantee that unit memory area the first polycrystalline silicon grid layer 206 surface does not has the residual of silica barrier layer 207
Stay.
Step S8: the polycrystalline silicon gate surface in unit memory area and peripheral device region carries out photoresist coating and shows
Shadow, forms final polysilicon dual gate structure through dry etching.
As shown in figure 13, the polycrystalline silicon gate surface in unit memory area and peripheral device region carry out photoresist coating and
Development, forms final polysilicon dual gate structure through dry etching, and this photoresist can be negative glue or positive glue.In this enforcement
In example, as a example by positive glue, unit storage and peripheral device region use dry etch process to etch respectively, ultimately form control
Grid.
To sum up, the invention provides and a kind of can obtain thicker peripheral device region polysilicon gate and relatively thin control simultaneously
The polysilicon dual gate structure of grid processed, effectively reduces the depth-to-width ratio of unit storage channel, in the breakdown voltage not sacrificing peripheral components
In the case of reach to improve the purpose of ILD filling capacity, and the reduction of unit memory area control gate height, complete it at ILD
After can be effectively improved the flatness on wafer (wafer) surface, follow-up photoetching process.
Compared with prior art, this process can be according to the storage of device requirement adjustment unit freely and peripheral components district
The polysilicon gate thickness in territory, process stabilizing is controlled, is suitable for batch production.
Above is only embodiments of the invention, and embodiment is also not used to limit the scope of patent protection of the present invention, therefore
The equivalent structure change that the description of every utilization present invention and accompanying drawing content are made, in like manner should be included in the protection of the present invention
In the range of.
Claims (10)
1. the process of an adjustable control grid increase ILD filling window, it is characterised in that including:
Step S1: semiconductor base, described semiconductor substrate surface at least a unit memory area and peripheral components district are provided
Territory；
Step S2: deposit the first polycrystalline silicon grid layer at semiconductor substrate surface；
Step S3: in one layer of silica barrier layer of the first polycrystalline silicon grid layer superficial growth；
Step S4: carry out photoresist coating and development on silica barrier layer surface, expose peripheral device region, only etches removal
The silica barrier layer of peripheral device region, removes remaining photoresist；
Step S5: in silica barrier layer and the first polycrystalline silicon grid layer surface deposition of peripheral device region of unit memory area
Second polycrystalline silicon grid layer；
Step S6: carry out photoresist coating and development on the second polycrystalline silicon grid layer surface, exposes unit memory area, and etching is removed
Only the second polycrystalline silicon grid layer of unit memory area, removes remaining photoresist；
Step S7: etching removes remaining silica barrier layer；
Step S8: the polycrystalline silicon gate surface in unit memory area and peripheral device region carries out photoresist coating and development, warp
Cross dry etching and form final polysilicon dual gate structure.
Adjustable control grid the most according to claim 1 increase ILD and fill the process of window, it is characterised in that described
The the first polysilicon gate layer thickness formed in step 2, depends on the thickness of the control gate of unit memory area, and span is
100 angstroms～2500 angstroms.
Adjustable control grid the most according to claim 1 increase ILD and fill the process of window, it is characterised in that described
Step 2 use furnace process deposit the first polycrystalline silicon grid layer at semiconductor substrate surface.
Adjustable control grid the most according to claim 1 increase ILD and fill the process of window, it is characterised in that described
The silica barrier layer thickness formed in step 3 is at 50 angstroms～500 angstroms.
Adjustable control grid the most according to claim 1 increase ILD and fill the process of window, it is characterised in that described
Silica barrier layer as the barrier layer of the described unit memory area polycrystalline silicon grid layer of removal, process of its growth is
ISSG, boiler tube, RTO or CVD.
Adjustable control grid the most according to claim 1 increase ILD and fill the process of window, it is characterised in that described
The photoresist used in step 4 is negative glue or positive glue, and the technique removing described peripheral boiler tube zone oxidation silicon barrier layer is wet
Method etching technics.
Adjustable control grid the most according to claim 1 increase ILD and fill the process of window, it is characterised in that step 5
In the described silica barrier layer at unit memory area and the first polycrystalline silicon grid layer surface deposition the of peripheral device region
The thickness of two polycrystalline silicon grid layers depends on the thickness of described first polycrystalline silicon grid layer and described peripheral device region polycrystalline silicon grid layer
Thickness requirements, span is 100 angstroms～2500 angstroms.
Adjustable control grid the most according to claim 1 increase ILD and fill the process of window, it is characterised in that described
Step 5 uses the furnace process silica barrier layer at unit memory area and the first polycrystalline silicon grid layer of peripheral device region
Surface deposits the second polycrystalline silicon grid layer.
Adjustable control grid the most according to claim 1 increase ILD and fill the process of window, it is characterised in that described
The photoresist used in step 6 uses dry method to carve for negative glue or positive glue, the second polycrystalline silicon grid layer of described unit memory area
Etching technique is removed.
Adjustable control grid the most according to claim 1 increase ILD and fill the process of window, it is characterised in that in institute
State in step 7, use wet-etching technology to remove residual silicon oxide barrier layer.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109192730A (en) * | 2018-09-18 | 2019-01-11 | 武汉新芯集成电路制造有限公司 | A kind of semiconductor devices and its manufacturing method |
| CN113224067A (en) * | 2021-04-28 | 2021-08-06 | 华虹半导体(无锡)有限公司 | Control grid back-etching method of NOR Flash Cell area, storage medium and control module |
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| CN1713370A (en) * | 2004-06-23 | 2005-12-28 | 上海先进半导体制造有限公司 | Production of multi-layer poly-silicon memory element |
| CN101099236A (en) * | 2004-12-22 | 2008-01-02 | 桑迪士克股份有限公司 | Eeprom array with self-aligned shallow-trench isolation |
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| US6127696A (en) * | 1991-12-06 | 2000-10-03 | Intel Corporation | High voltage MOS transistor for flash EEPROM applications having a uni-sided lightly doped drain |
| CN1713370A (en) * | 2004-06-23 | 2005-12-28 | 上海先进半导体制造有限公司 | Production of multi-layer poly-silicon memory element |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109192730A (en) * | 2018-09-18 | 2019-01-11 | 武汉新芯集成电路制造有限公司 | A kind of semiconductor devices and its manufacturing method |
| CN113224067A (en) * | 2021-04-28 | 2021-08-06 | 华虹半导体(无锡)有限公司 | Control grid back-etching method of NOR Flash Cell area, storage medium and control module |
| CN113224067B (en) * | 2021-04-28 | 2022-09-20 | 华虹半导体(无锡)有限公司 | Control grid back-etching method of NOR Flash Cell area, storage medium and control module |
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| CN106328656B (en) | 2019-05-10 |
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