CN109192730A - A kind of semiconductor devices and its manufacturing method - Google Patents
A kind of semiconductor devices and its manufacturing method Download PDFInfo
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- CN109192730A CN109192730A CN201811088641.1A CN201811088641A CN109192730A CN 109192730 A CN109192730 A CN 109192730A CN 201811088641 A CN201811088641 A CN 201811088641A CN 109192730 A CN109192730 A CN 109192730A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
Abstract
The present invention provides a kind of manufacturing method of semiconductor devices, first grid floor and second grid floor are respectively formed in flash memory area and the area MOS simultaneously, protective layer is yet formed on first grid layer, by the protective layer make memory block floating gate layer will not side wall technique and before technique in be damaged, play the role of protecting floating gate, compared to the method for protecting floating gate layer by the thickness for increasing the grid layer on the floating gate layer of flash memory area, avoid the increase of the second grid thickness degree in the area MOS being formed together with the first grid floor of flash memory area, to, while meeting the storage performance of flash memory area flash memory, the thickness of MOS device second grid layer can be effectively reduced, improve the mutual conductance of MOS device, and then improve the performance of device.
Description
Technical field
The present invention relates to field of semiconductor manufacture, in particular to a kind of semiconductor devices and its manufacturing method.
Background technique
With the continuous development of semiconductor technology, memory is widely used.Floating gate type flash memory is a kind of non-easy
The property lost memory has many advantages, such as that integrated level is high, storage speed is fast and is easy to wipe and rewrite.
In specific application, floating gate type flush memory device is usually and by MOS (Metal-Oxide-Semiconductor, gold
Belonging to oxide semiconductor) peripheral circuit of device composition integrates together, the control gate of floating gate type flush memory device and peripheral circuit
The grid of MOS device is formed together, and in order to guarantee the storage performance of floating gate type flash memory, it is ensured that the thickness of control gate, this meeting
So that the grid of MOS device is blocked up.However, also proposed with the continuous reduction of device feature size to the performance of MOS device
Higher requirement, blocked up grid will have a direct impact on exhausting for gate electrode, reduce the mutual conductance of MOS device, influence the property of MOS device
Energy.
Summary of the invention
In view of this, guaranteeing that floating gate type dodges the purpose of the present invention is to provide a kind of semiconductor devices and its manufacturing method
The mutual conductance of the storage performance and raising MOS device deposited.
To achieve the above object, the present invention has following technical solution:
A kind of manufacturing method of semiconductor devices, comprising:
Semiconductor substrate is provided, the substrate includes flash memory area and the area MOS；
Form gate structure on the flash memory area, the gate structure include the floating gate layer stacked gradually, separation layer and
First grid layer, and second grid floor is formed in the area MOS, the first grid layer and the second grid layer are simultaneously
It is formed, and forms matcoveredn on the first grid layer；
The first side wall is formed on the side wall of the gate structure and the second grid layer；
Remove the protective layer.
Optionally, gate structure is formed on the flash memory area, and second grid floor is formed in the area MOS, packet
It includes:
Floating gate layer and separation layer are successively covered on the flash memory area；
It is sequentially depositing gate material layers and protective layer；
The patterning of the floating gate layer, separation layer, gate material layers and protective layer is carried out, to be formed on the flash memory area
Gate structure, the protective layer on second grid floor and first grid floor and second grid floor in the area MOS.
Optionally, the protective layer is silicon nitride.
Optionally, the first side wall is formed on the side wall of the gate structure and the second grid layer；Described in removal
Protective layer, comprising:
The deposition of the first spacer material layer is carried out, the first spacer material layer includes material layer identical with protective layer；
The anisotropic etching of the first spacer material layer and protective layer is carried out, to remove the protective layer and only exist
The first side wall is formed on the side wall of the gate structure and second grid layer.
Optionally, first side wall includes the silicon oxide layer and silicon nitride layer stacked gradually, further includes:
The second side wall technique of silica is carried out, to form the second side wall in the side wall of first side wall of the area MOS, together
When, the filled layer of silica is formed between the first side wall of the flash memory area.
Optionally, after forming the first side wall, before the second side wall technique of progress, further includes:
The first source-drain area is formed in the substrate of the gate structure two sides of the flash memory area；
After carrying out the second side wall technique, further includes:
The second source-drain area is formed in the substrate of the second grid floor two sides in the area MOS.
Optionally, the thickness range of the first grid layer and the second grid layer isThe guarantor
The thickness range of sheath is
A kind of semiconductor devices, comprising:
Semiconductor substrate, the substrate include flash memory area and the area MOS；
Gate structure on the flash memory area, the gate structure include the floating gate layer stacked gradually, separation layer and first
Grid layer；
Second grid floor in the area MOS, the second grid layer and the first grid layer material having the same
Material and essentially identical thickness；
The first side wall on the side wall of the gate structure and the second grid layer.
Optionally, first side wall includes the silicon oxide layer and silicon nitride layer stacked gradually, further includes:
The filled layer of silica between first side wall of the flash memory area；
The side wall of silica on the side wall of first side wall of the area MOS.
Optionally, the thickness range of the first grid layer and the second grid layer is
Semiconductor devices provided in an embodiment of the present invention and its manufacturing method, while being respectively formed in flash memory area and the area MOS
First grid layer and second grid layer, yet form protective layer on first grid layer, make memory block by the protective layer
Floating gate layer will not side wall technique and before technique in be damaged, play the role of protect floating gate, compared to pass through increase
The thickness of grid layer on the floating gate layer of flash memory area avoids the first grid layer one with flash memory area come the method for protecting floating gate layer
With the increase of the second grid thickness degree in the area MOS formed, thus, it, can while meeting the storage performance of flash memory area flash memory
The thickness of MOS device second grid layer is effectively reduced, the mutual conductance of MOS device is improved, and then improve the performance of device.
Furthermore, it is possible to be formed simultaneously the grid layer and grid layer in flash memory area and the area MOS by a Patternized technique
On protective layer, without increasing additional photoetching process, process costs are low and integrated level is high.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is the present invention
Some embodiments for those of ordinary skill in the art without creative efforts, can also basis
These attached drawings obtain other attached drawings.
Fig. 1 shows the flow diagram of the manufacturing method of semiconductor devices according to embodiments of the present invention；
The device that Fig. 2-11 shows during manufacturing method according to an embodiment of the present invention forms semiconductor devices cuts open
Face structural schematic diagram.
Specific embodiment
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
In the following description, numerous specific details are set forth in order to facilitate a full understanding of the present invention, but the present invention can be with
Implemented using other than the one described here other way, those skilled in the art can be without prejudice to intension of the present invention
In the case of do similar popularization, therefore the present invention is not limited by the specific embodiments disclosed below.
Secondly, combination schematic diagram of the present invention is described in detail, when describing the embodiments of the present invention, for purposes of illustration only, table
Show that the sectional view of device architecture can disobey general proportion and make partial enlargement, and the schematic diagram is example, is not answered herein
Limit the scope of protection of the invention.In addition, the three-dimensional space of length, width and depth should be included in actual fabrication.
In addition, the present invention can in different examples repeat reference numerals and/or letter.This repetition be in order to simplify and
Clear purpose itself does not indicate the relationship between discussed various embodiments and/or setting.In addition, the present invention provides
Various specific techniques and material example, but those of ordinary skill in the art may be aware that other techniques are applied
In the use of property and/or other materials.In addition, structure of the fisrt feature described below in the "upper" of second feature may include
First and second features are formed as the embodiment directly contacted, also may include that other feature is formed in the first and second features
Between embodiment, such first and second feature may not be direct contact.
In the manufacture of floating gate type flush memory device, in the technique after grid formation, especially to before side wall technique
Technique in, floating gate is easy to be damaged, and then storage performance is caused to be affected, and by arriving the thickening of the thickness of control gate
To a certain degree, can play the role of protecting floating gate, so that floating gate be avoided to be damaged.However, in floating gate type flush memory device
It in manufacture, is usually integrated together with MOS device, the control gate of flush memory device and the grid of MOS device are the shapes in same technique
At, in order to guarantee the thickness of control gate, so that the grid of MOS device is blocked up, blocked up grid will have a direct impact on gate electrode
It exhausts, reduces the mutual conductance of MOS device, influence the performance of MOS device.
For this purpose, present applicant proposes a kind of manufacturing methods of semiconductor devices, while being respectively formed in flash memory area and the area MOS
First grid layer and second grid layer, yet form protective layer on first grid layer, make memory block by the protective layer
Floating gate layer will not side wall technique and before technique in be damaged, play the role of protect floating gate, compared to pass through increase
The thickness of grid layer on the floating gate layer of flash memory area avoids the first grid layer one with flash memory area come the method for protecting floating gate layer
With the increase of the second grid thickness degree in the area MOS formed, thus, meeting the same of the storage performance of flash memory area flush memory device
When, the thickness of MOS device second grid layer can be effectively reduced, improve the mutual conductance of MOS device, and then improve the performance of device.
The technical solution and technical effect of the application in order to better understand, below with reference to flow chart 1 and attached drawing 2-11
Specific embodiment is described in detail.
In step S101, semiconductor substrate 100 is provided, the substrate 100 includes flash memory area 1001 and the area MOS 1002, ginseng
It examines shown in Fig. 2.
In the application preferred embodiment, semiconductor substrate 100 can be for Si substrate, Ge substrate, SiGe substrate, SOI (absolutely
Silicon on edge body, Silicon On Insulator) or GOI (germanium on insulator, Germanium On Insulator) etc..At it
In his embodiment, semiconductor substrate can also be include the substrate of other elements semiconductor or compound semiconductor, such as GaAs,
InP or SiC etc. can also be laminated construction, such as Si/SiGe etc. can be with other epitaxial structures, such as SGOI (insulator
Upper germanium silicon) etc..The semiconductor substrate 100 can be already formed with isolated area (not shown go out), and isolated area may include dioxy
SiClx or other can separate the material of the active area of device.In the present embodiment, the substrate 100 is body silicon substrate.
In the embodiment of the present application, there is flash memory area 1001 and the area MOS 1002, flash memory area 1001 is used to form on substrate 100
Flush memory device, the flush memory device are floating gate type flush memory device, and the area MOS is used to form MOS device, can for p-type MOS device and/
Or N-type MOS device, the MOS device in the area MOS can be used for being formed driving circuit, read/write circuit and/or control circuit etc..
In step S102, gate structure 10 is formed on the flash memory area 1001, the gate structure 10 includes successively layer
Folded floating gate layer 104, separation layer 106 and first grid layer 1121, and second grid floor 1122 is formed in the area MOS,
The first grid layer 1121 and the second grid layer 1122 are formed simultaneously, and are formed with guarantor on the first grid layer 1121
Sheath 114, with reference to shown in Fig. 5.
In the gate structure of flash memory area, floating gate layer 104 is the floating gate of flush memory device, at floating state, for storing
Charge, first grid layer 1121 are the control gate of flush memory device, are usually connect with external electrode such as wordline, floating for controlling
The storage and release of charge in grid layer 104, separation layer 106 are situated between for floating gate layer 104 and first grid layer 1121 to be isolated for insulation
Material.Second grid layer 1122 is the grid of MOS device, is formed simultaneously with first grid layer, that is, in identical work
It is formed in skill, material having the same and essentially identical thickness.At this point, the thickness of the second grid layer formed can foundation
The demand of the area MOS device is formed, and the requirement of the area MOS device performance is met, and due to the presence of protective layer, it can satisfy flash memory
The requirement of the storage performance of area's flush memory device.Preferably, the thickness range of the first grid layer and the second grid layer can
ThinkThe thickness range of the protective layer can be
It is understood that being also formed with tunnel oxide skin(coating) between gate structure 10 and the substrate of flash memory area 1001
102, gate dielectric layer 110, tunnel oxide skin(coating) 102 are also formed between second grid floor 1122 and the substrate in the area MOS 1002
It can choose suitable dielectric material with gate dielectric layer 110 to be formed, can be respectively formed in same technique or different technique.
Protective layer 114 is also formed on first grid layer 1121, which is sacrificial layer, is forming grid knot
It after the side wall of structure 10, removes it, plays the role of before side wall technique, protect floating gate layer not by other process-induced damages.
Suitable material can be selected to form the protective layer according to specific needs, which can be dielectric material, more preferably,
It can have material identical with the side wall of gate structure and second grid, in this way, can be during forming side wall, together
It removes it.
In a specific embodiment, the floating gate layer 104 can be polysilicon, and the separation layer 106 can be ONO
The lamination of (oxide nitride oxide), the i.e. lamination of oxide, nitride and oxide, first grid layer 1121 and
Two grid layers 1122 can be polysilicon, and protective layer 114 can be silicon nitride.Tunnel oxide skin(coating) 102 and gate dielectric layer 110 can
Think silica.
In specific application, protective layer 114 can be only formed on first grid layer 1121, and in preferred embodiment
In, in order not to increase additional photoetching process, that is, do not increase process costs, gate structure and first will be formed in patterning
While grid layer, protective layer 114 is formed simultaneously on first grid layer 1121 and second grid layer 1122.
Specifically, floating gate layer 104 and separation layer 106 are successively covered on flash memory area 1001 in S1021, with reference to Fig. 3 institute
Show.
As shown in figure 3, the tunnel oxide skin(coating) of thermal oxidation silicon can be first formed on substrate 100 by thermal oxidation technology
102, then, using suitable depositing operation, it is sequentially depositing the floating gate layer 104 of polysilicon and the separation layer 106 of ONO.Then, such as
It shown in Fig. 3, is once patterned, for example, by using the method for reactive ion etching (RIE), only forms covering flash memory area 1001
Floating gate layer 104 and separation layer 106.
In S1022, it is sequentially depositing gate material layers 112 and protective layer 114, with reference to shown in Fig. 4.
As shown in figure 4, grid Jie for forming thermal oxidation silicon on the substrate in the area thermal oxidation technology Xian MOS 1002 can be first passed through
Matter layer 110 then using suitable depositing operation, is sequentially depositing the gate material layers 112 of polysilicon and the protective layer of silicon nitride
114。
In S1023, the pattern of the floating gate layer 104, separation layer 106, gate material layers 112 and protective layer 114 is carried out
Change, with the gate structure 10 formed on the flash memory area 1001, gate structure 10 includes the floating gate layer 104 stacked gradually, isolation
Layer 106 and first grid layer 1121, form 1121 He of second grid floor 1122 and first grid floor in the area MOS 1002
Protective layer 114 on second grid layer 1122, with reference to shown in Fig. 4-5.
In the present embodiment, tunnel oxide skin(coating) 102 and gate dielectric layer 110 are formed in different technique, and gate medium
Layer 110 carries out after forming the floating gate layer 104 of flash memory area 1001, separation layer 106, it is ensured that the matter of the area MOS gate dielectric layer
Amount, and processing step is reduced, improve the integrated level of technique.
Mask layer can be first initially formed on above-mentioned protective layer 114, and by photoetching technique, by flash memory area and the area MOS
The pattern of grid is transferred in mask layer, then, be can use lithographic technique, such as the method for RIE, is etched the protective layer
114, gate material layers 112, separation layer 106, floating gate layer 104 and tunnel oxide skin(coating) 102, gate dielectric layer 110 will dodge respectively
Protective layer 114, gate material layers 112, separation layer 106, floating gate layer 104 and the tunnel oxide skin(coating) 102 for depositing area 1001 carry out figure
Case forms the gate structure 10 of flash memory area 1001, and the protective layer 114 in the area MOS 1002, gate material layers 112, grid is situated between
Matter layer 110 is patterned, and forms the grid region in the area MOS, as shown in Figure 5.In this way, forming grid by flash memory area and the area MOS
Patternized technique just in the first grid 1121 of flash memory area 1001, that is, forms on control gate for protecting floating gate layer
104 are not reduced manufacturing cost without increasing additional mask plate by the protective layer of other process-induced damages 114.
In step S103, the first side wall is formed on the side wall of the gate structure 10 and the second grid layer 1122
116；And in step S104, the protective layer 114 is removed, with reference to shown in Fig. 7.
First side wall 116 can be the final sidewall structure of gate structure 10 and/or second grid layer 1122, can also
To be the sidewall structure of part, the first side wall 116 can have single or multi-layer structure, can be by silicon nitride, silica, nitrogen oxygen
SiClx, silicon carbide, fluoride-doped silica glass, low k dielectric material and combinations thereof and/or other suitable materials are formed.
It can be while forming the first side wall 116, or after forming the first side wall 116, remove the protective layer.?
In the application preferred embodiment, the protective layer 114 has material layer identical with first side wall, in this way, can be
While forming the first side wall, protective layer 114 is removed, advanced optimizes technique, improves process integration.
Specifically, carrying out the deposition of the first spacer material layer 1161,1162, the first spacer material layer in S1031
1161,1162 include material layer identical with protective layer 114, with reference to shown in Fig. 6.
In the present embodiment, the first spacer material layer is double-layer structure, including the silicon oxide layer 1161 stacked gradually
With silicon nitride layer 1162, the protective layer 114 is silicon nitride, as shown in fig. 6, suitable deposition method can be used, is successively sunk
First spacer material layer of product silicon oxide layer 1161 and silicon nitride layer 1162.
In S1032, the anisotropic etching of the first spacer material layer 1161,1162 and protective layer 114 is carried out, with
It removes the protective layer 114 and only forms the first side wall 116 on the side wall of the gate structure and second grid layer 1122,
With reference to shown in Fig. 7.
It in anisotropic etching, is mainly removed in vertical direction, in this way, substrate 100, gate structure and
The first spacer material layer 1161,1162 on two grid layers 1122 can be all removed, and only retain gate structure and second grid
First spacer material layer 1161,1162 on 1122 side wall of layer, so that the first side wall 116 is formed, meanwhile, protective layer 114 and first
Material layer material having the same in spacer material layer, in anisotropic etching, as shown in fig. 7, forming the first side wall 116
While, protective layer 114 can also be got rid of together.
Specifically, can be performed etching using the method for RIE, etching stopping is in first grid layer 1121 and second grid layer
On 1122.
Later, as needed, subsequent device manufacturing process is carried out.
In the application preferred embodiment, the first above-mentioned side wall includes the silicon oxide layer 1161 stacked gradually and nitridation
Silicon layer 1162 can carry out flash memory while continuously forming another part side wall for the part side wall of second grid layer 1122
Filling between 1001 gate structure of area when depositing spacer material, usually all uses quality of forming film in the technique for forming side wall
Higher depositing operation, such as furnace process facilitate the filling energy for improving dielectric material between 1001 gate structure of flash memory area
Power improves the device performance of flash memory area.It is possible to further preferably be integrated with the source and drain formation process in flash memory area and the area MOS.
Specifically, manufacturing method below can be continued.
In step S105, the first source-drain area is formed in the substrate 100 of 10 two sides of gate structure of the flash memory area 1001
130, with reference to shown in Fig. 8.
As shown in figure 8, a mask layer 120 can be covered in the area Xian MOS, which for example can be photosensitive etching
Agent, under the masking of the mask layer 120, using ion implanting or other methods, into the substrate of flash memory area 1001 implant n-type or
P-type dopant or impurity then carry out thermal annealing, to activate doping, thus, in gate structure 10 two sides of flash memory area 1001
The first source-drain area 130 is formed in substrate 100, as shown in Figure 8.Later, mask layer 120 can be removed.
In step S106, the second side wall technique of silica is carried out, in the side of 1,002 first side wall 116 of the area MOS
Wall forms the second side wall 142 of silica, meanwhile, silica is formed between the first side wall 116 of the flash memory area 1001
Filled layer 140, with reference to shown in Fig. 9.
It is understood that first having to the deposition for carrying out spacer material in side wall technique, then, anisotropy is carried out
Etching forms side wall to retain spacer material on the side wall of structure needed for carrying out.
Gate structure 10 in this preferred embodiment, while carrying out the second side wall technique, in flash memory area 1001
Between form filled layer.Specifically, the deposition of the second spacer material of silica is first carried out, in the deposition of the silica,
The higher depositing operation of quality of forming film is usually all used, such as can be the depositing operation carried out in boiler tube, the silica of deposition
Spreadability it is good, pass through technology controlling and process, deposit the silica the second spacer material after, the first side wall of flash memory area 1001
Also it is filled with the second spacer material of silica between 116, then, anisotropic etching, such as the side of RIE can be carried out
Method removes the second spacer material on substrate surface and gate structure surface, as shown in figure 9, in 1,002 first side of the area MOS
While the side wall of wall 116 forms the second side wall 142 of silica, also formed between the first side wall 116 of flash memory area 1001
The filled layer 140 of silica.The method of the embodiment helps to improve dielectric material between 1001 gate structure of flash memory area
Filling capacity improves the device performance of flash memory area, meanwhile, improve process integration.
In step S107, the second source and drain is formed in the substrate 100 of 1122 two sides of second grid floor in the area MOS 1002
Area 132, with reference to Figure 10.
As shown in Figure 10, another mask layer 122 can first be covered on flash memory area 1001, which for example can be with
For photosensitive etching agent, under the masking of the mask layer 122, using ion implanting or other methods, into the substrate in the area MOS 1002
Implant n-type or p-type dopant or impurity, then carry out thermal annealing, to activate doping, thus, the second grid floor in the area MOS 1002
The second source-drain area 132 is formed in the substrate 100 of 1122 two sides, as shown in Figure 10.Later, mask layer 122 can be removed.
It should be noted that the step of thermal annealing can be carried out in step s105, activate doping, and in step S107
In, by a thermal anneal process, while the activation of the doping of the first source-drain area 130 and the second source-drain area 132 is carried out, with into one
Step improves process integration.
Then, can be with further progress others processing technology, such as interlayer dielectric layer 150 is formed, and form first
The second contact 162 on first the 160, second source-drain area 132 of contact on source-drain area 130.
So far the semiconductor devices of the present embodiment is formd, in the embodiment, by forming protective layer on grid, is avoided
The increase of the second grid thickness degree in the area MOS being formed together with the first grid floor of flash memory area, thus, meeting flash memory area
While the storage performance of flash memory, the thickness of MOS device second grid layer can be effectively reduced, improve the mutual conductance of MOS device, into
And improve the performance of device.In addition, passing through the grid that can be formed simultaneously flash memory area and the area MOS by a Patternized technique
Protective layer on layer and grid layer, without increasing additional photoetching process, while improving between the gate structure of flash memory area
Filling capacity, process costs are low and integrated level is high.
In addition, present invention also provides the semiconductor devices formed by above-mentioned manufacturing method, with reference to shown in Figure 11, comprising:
Semiconductor substrate 100, the substrate 100 include flash memory area 1001 and the area MOS 1002；
Gate structure on the flash memory area 1001, the gate structure include floating gate layer 104, the separation layer stacked gradually
106 and first grid layer 1121；
Second grid floor 1122 in the area MOS 1002, the second grid layer 1121 and the first grid layer
1122 materials having the same and essentially identical thickness；
The first side wall 116 on the side wall of the gate structure and the second grid layer 1122.
In the semiconductor devices of the embodiment of the present application, the first grid layer 1121 and second grid layer 1122 are simultaneously
It is formed, therefore material having the same and essentially identical thickness, essentially identical thickness refers to herein, in fabrication error
It is approximately uniform in the range of permission.
Further, the thickness range of the first grid layer 1121 and the second grid layer 1122 isIn this way, make second grid layer 1122 that there is relatively thin thickness, so that the mutual conductance of MOS device increases,
And then improve the performance of MOS device.
Further, first side wall 116 includes the silicon oxide layer and silicon nitride layer stacked gradually, and the device also wraps
It includes:
The filled layer 140 of silica between first side wall 116 of the flash memory area 1001；
Second side wall 142 of silica on the side wall of 1,002 first side wall 116 of the area MOS.
The filled layer 140 and the second side wall 142 can be formed simultaneously in side wall technique, therefore, so that flash memory area 1002
Device between media filler performance improve, in turn, improve the performance of flush memory device.
It should be noted that all the embodiments in this specification are described in a progressive manner, each embodiment it
Between same and similar part may refer to each other, each embodiment focuses on the differences from other embodiments.
For device embodiments, since it is substantially similar to the method embodiment, so describe fairly simple, correlation
Place illustrates referring to the part of embodiment of the method.
The above is only a preferred embodiment of the present invention, although the present invention has been disclosed in the preferred embodiments as above, so
And it is not intended to limit the invention.Anyone skilled in the art is not departing from technical solution of the present invention ambit
Under, many possible changes and modifications all are made to technical solution of the present invention using the methods and technical content of the disclosure above,
Or equivalent example modified to equivalent change.Therefore, anything that does not depart from the technical scheme of the invention, according to the present invention
Technical spirit any simple modification, equivalent variation and modification made to the above embodiment, still fall within the technology of the present invention side
In the range of case protection.
Claims (10)
1. a kind of manufacturing method of semiconductor devices characterized by comprising
Semiconductor substrate is provided, the substrate includes flash memory area and the area MOS；
Gate structure is formed on the flash memory area, the gate structure includes the floating gate layer stacked gradually, separation layer and first
Grid layer, and second grid floor, the first grid layer and the second grid layer while shape are formed in the area MOS
At, and matcoveredn is formed on the first grid layer；
The first side wall is formed on the side wall of the gate structure and the second grid layer；
Remove the protective layer.
2. the manufacturing method according to claim 1, which is characterized in that gate structure is formed on the flash memory area, and
Second grid floor is formed in the area MOS, comprising:
Floating gate layer and separation layer are successively covered on the flash memory area；
It is sequentially depositing gate material layers and protective layer；
The patterning of the floating gate layer, separation layer, gate material layers and protective layer is carried out, with the grid formed on the flash memory area
Protective layer in pole structure, second grid floor and first grid floor and second grid floor in the area MOS.
3. the manufacturing method according to claim 1, which is characterized in that the protective layer is silicon nitride.
4. the manufacturing method according to claim 1, which is characterized in that in the gate structure and the second grid layer
Side wall on form the first side wall；Remove the protective layer, comprising:
The deposition of the first spacer material layer is carried out, the first spacer material layer includes material layer identical with protective layer；
The anisotropic etching of the first spacer material layer and protective layer is carried out, to remove the protective layer and only described
The first side wall is formed on the side wall of gate structure and second grid layer.
5. manufacturing method according to claim 4, which is characterized in that first side wall includes the silica stacked gradually
Layer and silicon nitride layer, further includes:
The second side wall technique of silica is carried out, to form the second side wall in the side wall of first side wall of the area MOS, meanwhile,
The filled layer of silica is formed between first side wall of the flash memory area.
6. manufacturing method according to claim 5, which is characterized in that after forming the first side wall, carry out the second side wall
Before technique, further includes:
The first source-drain area is formed in the substrate of the gate structure two sides of the flash memory area；
After carrying out the second side wall technique, further includes:
The second source-drain area is formed in the substrate of the second grid floor two sides in the area MOS.
7. manufacturing method according to claim 1 to 6, which is characterized in that the first grid layer and described
The thickness range of two grid layers isThe thickness range of the protective layer is
8. a kind of semiconductor devices characterized by comprising
Semiconductor substrate, the substrate include flash memory area and the area MOS；
Gate structure on the flash memory area, the gate structure include the floating gate layer, separation layer and first grid stacked gradually
Layer；
Second grid floor in the area MOS, the second grid layer and the first grid layer material having the same with
And essentially identical thickness；
The first side wall on the side wall of the gate structure and the second grid layer.
9. semiconductor devices according to claim 8, which is characterized in that first side wall includes the oxidation stacked gradually
Silicon layer and silicon nitride layer, further includes:
The filled layer of silica between first side wall of the flash memory area；
Second side wall of silica on the side wall of first side wall of the area MOS.
10. semiconductor devices according to claim 8 or claim 9, which is characterized in that the first grid layer and the second gate
Pole layer thickness range be
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811088641.1A CN109192730A (en) | 2018-09-18 | 2018-09-18 | A kind of semiconductor devices and its manufacturing method |
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| CN112563277A (en) * | 2020-11-13 | 2021-03-26 | 上海华力微电子有限公司 | NOR flash unit structure and manufacturing method thereof |
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| JPH07193198A (en) * | 1993-12-27 | 1995-07-28 | Mitsubishi Electric Corp | Involatile semiconductor memory and its manufacture |
| US20030042530A1 (en) * | 2001-09-04 | 2003-03-06 | Nec Corporation | Non-volatile semiconductor memory device and fabrication method therefor |
| CN106328656A (en) * | 2016-08-22 | 2017-01-11 | 上海华力微电子有限公司 | Process method for adding ILD (Inter Layer Deposition) filling window of adjustable control gate poly |
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| EP0200364A1 (en) * | 1985-03-29 | 1986-11-05 | Advanced Micro Devices, Inc. | Method of fabricating metal silicide gate electrodes and interconnections |
| JPH07193198A (en) * | 1993-12-27 | 1995-07-28 | Mitsubishi Electric Corp | Involatile semiconductor memory and its manufacture |
| US20030042530A1 (en) * | 2001-09-04 | 2003-03-06 | Nec Corporation | Non-volatile semiconductor memory device and fabrication method therefor |
| CN106328656A (en) * | 2016-08-22 | 2017-01-11 | 上海华力微电子有限公司 | Process method for adding ILD (Inter Layer Deposition) filling window of adjustable control gate poly |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112563277A (en) * | 2020-11-13 | 2021-03-26 | 上海华力微电子有限公司 | NOR flash unit structure and manufacturing method thereof |
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