CN106298665B - The manufacturing method of semiconductor devices - Google Patents
The manufacturing method of semiconductor devices Download PDFInfo
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- CN106298665B CN106298665B CN201510271246.7A CN201510271246A CN106298665B CN 106298665 B CN106298665 B CN 106298665B CN 201510271246 A CN201510271246 A CN 201510271246A CN 106298665 B CN106298665 B CN 106298665B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 48
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 38
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 38
- 239000010937 tungsten Substances 0.000 claims abstract description 38
- 238000002347 injection Methods 0.000 claims abstract description 26
- 239000007924 injection Substances 0.000 claims abstract description 26
- NXHILIPIEUBEPD-UHFFFAOYSA-H tungsten hexafluoride Chemical compound F[W](F)(F)(F)(F)F NXHILIPIEUBEPD-UHFFFAOYSA-H 0.000 claims abstract description 22
- 239000002243 precursor Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 20
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910000085 borane Inorganic materials 0.000 claims abstract description 13
- 229910000077 silane Inorganic materials 0.000 claims abstract description 13
- UORVGPXVDQYIDP-UHFFFAOYSA-N trihydridoboron Substances B UORVGPXVDQYIDP-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims description 40
- 239000002184 metal Substances 0.000 claims description 40
- 230000004888 barrier function Effects 0.000 claims description 19
- 230000008569 process Effects 0.000 claims description 8
- 238000000137 annealing Methods 0.000 claims description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical group [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 5
- 239000002245 particle Substances 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 40
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 14
- 239000000463 material Substances 0.000 description 12
- 239000000377 silicon dioxide Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- PNEHEYIOYAJHPI-UHFFFAOYSA-N lithium tungsten Chemical group [Li].[W] PNEHEYIOYAJHPI-UHFFFAOYSA-N 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000010926 purge Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- -1 Pyrex Chemical compound 0.000 description 1
- 229910004156 TaNx Inorganic materials 0.000 description 1
- 229910010038 TiAl Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000005297 pyrex Substances 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7845—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being a conductive material, e.g. silicided S/D or Gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a kind of manufacturing methods of semiconductor devices, comprising: provides semiconductor substrate, has the opening for removing and being formed after pseudo- grid on the substrate；Using ALD technique, the top-level metallic of tungsten is filled in the opening, precursor gas is silane or borine and tungsten hexafluoride, and to the top-level metallic in NMOS device region, carries out decrystallized injection.Method of the invention improves the carrier mobility of PMOS device channel, enhances the performance of PMOS device, and the tensile stress of the top-level metallic of NMOS device is reduced, and guarantees the performance of NMOS device.
Description
Technical field
The invention belongs to field of semiconductor manufacture more particularly to a kind of manufacturing methods of semiconductor devices.
Background technique
Currently, in the integrated of advanced CMOS FET (complementary metal oxide semiconductor field effect transistor) manufacturing process
Research can probably be divided into both direction, i.e., preceding grid technique and rear grid technique.
Grid technique is now widely used in advanced integrated circuit technology manufacture afterwards, is usually to be initially formed pseudo- grid and source
Drain region then removes pseudo- grid and re-forms the replacement gate of high-k/metal gate stacking in gate groove.Since grid is formed in source
After drain electrode, grid does not need to bear very high annealing temperature in this technique, to grid layer material selection more extensively and more can body
The intrinsic characteristic of existing material.
Since dimensions of semiconductor devices constantly reduces, to the performance of semiconductor devices, higher requirements are also raised, wherein
Stress engineering is that different adaptabilitys to changes is introduced by the channel region to NMOS and PMOS device, so as to improve channel carrier
Mobility further increases the performance of device.In rear grid technique, it is generally filled with tungsten and makees into the opening of removal dummy grid
The good filling of the coverage rate of not hole how is formed, and can be further especially after device size reduction for metal gates
The fill method for improving device channel carrier mobility is one of the critical issue that replacement gate filling needs to solve.
Summary of the invention
It is an object of the invention to overcome deficiency in the prior art, a kind of manufacturing method of semiconductor devices is provided, is mentioned
For the grid slot filling capacity that has had and can strain needed for introduction means device manufacturing method.
To achieve the above object, the technical solution of the present invention is as follows:
A kind of manufacturing method of semiconductor devices, comprising:
Semiconductor substrate is provided, there is the opening for removing and being formed after pseudo- grid on the substrate；
Using ALD technique, fill the top-level metallic of tungsten in the opening, precursor gas be silane or borine with it is lithium
Tungsten, and to the top-level metallic in NMOS device region, carry out decrystallized injection.
Optionally, in the opening fill tungsten top-level metallic the step of include:
Using ALD technique, the top-level metallic of tungsten is filled in the opening in PMOS device region, precursor gas is silane
With tungsten hexafluoride；
Using ALD technique, the top-level metallic of tungsten is filled in the opening in NMOS device region, precursor gas is borine
With tungsten hexafluoride.
Optionally, the particle of decrystallized injection is Ge.
Optionally, the process conditions of decrystallized injection are as follows: the energy of injection is -0.5-30keV, and the dosage of injection is
5E14-5E16/cm2。
Optionally, the top-level metallic of tungsten is filled in the opening and includes: the step of carrying out decrystallized injection
The deposit of tungsten is carried out using ALD technique, precursor gas is silane or borine and tungsten hexafluoride；
Carry out flatening process；
The mask film covering layer on PMOS device region；
Carry out decrystallized injection；
Remove mask layer；
Tungsten except removal opening, to form the top-level metallic of tungsten in the opening.
Optionally, it before carrying out ALD technique, further comprises the steps of:
High-k gate dielectric layer is formed on the inner wall of opening, and carries out thermal annealing.
Optionally, the temperature of thermal annealing is 450 DEG C, time 15s.
Optionally, it before carrying out ALD technique, forms high-k gate dielectric layer and further comprises the steps of: later
The first metal barrier is formed on high-k gate dielectric layer；
Metal work function layer is formed on the first metal barrier；
The second metal barrier is formed on metal work function layer.
Optionally, first metal barrier or the second metal barrier are TiN or WN.
The manufacturing method of semiconductor devices provided in an embodiment of the present invention, in rear grid technique, using ALD process filling top
When layer metal, precursor gas is silane or borine and tungsten hexafluoride, and the top-level metallic that this method is formed has channel vertical direction
The carrier mobility of PMOS device channel can be improved in the effect of tensile stress, the performance of PMOS device is enhanced, for NMOS
The top-level metallic of device, the decrystallized injection of further progress guarantee so that the tensile stress of the top-level metallic of NMOS device reduces
The performance of NMOS device, meanwhile, ALD technique can guarantee top-level metallic grid slot filling capacity.
Detailed description of the invention
It, below will be to attached drawing needed in the embodiment in order to illustrate more clearly of the technical solution that the present invention is implemented
It is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, general for this field
For logical technical staff, without creative efforts, it is also possible to obtain other drawings based on these drawings.
Fig. 1 shows the flow chart of the manufacturing method of semiconductor devices according to an embodiment of the present invention；
Fig. 2-Fig. 9 is to be illustrated according to the section of device in each manufacturing process of manufacturing semiconductor devices of the embodiment of the present invention
Figure, section are along fin direction.
Specific embodiment
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
In the following description, numerous specific details are set forth in order to facilitate a full understanding of the present invention, but the present invention can be with
Implemented using other than the one described here other way, those skilled in the art can be without prejudice to intension of the present invention
In the case of do similar popularization, therefore the present invention is not limited by the specific embodiments disclosed below.
Secondly, combination schematic diagram of the present invention is described in detail, when describing the embodiments of the present invention, for purposes of illustration only, table
Show that the sectional view of device architecture can disobey general proportion and make partial enlargement, and the schematic diagram is example, is not answered herein
Limit the scope of protection of the invention.In addition, the three-dimensional space of length, width and depth should be included in actual fabrication.
In the present invention, a kind of manufacturing method of semiconductor devices is provided, with reference to shown in figure Fig. 1, this method comprises:
Semiconductor substrate is provided, there is the opening for removing and being formed after pseudo- grid on the substrate；
Using ALD technique, fill the top-level metallic of tungsten in the opening, precursor gas be silane or borine with it is lithium
Tungsten, and for the top-level metallic in NMOS device region, carry out decrystallized injection.
The manufacturing method of the present invention is applied in rear grid technique, when filling top-level metallic in the opening using ALD technique,
Precursor gas is silane or borine and tungsten hexafluoride, and the top-level metallic that this method is formed has the work of tensile stress to channel vertical direction
With the carrier mobility of PMOS device channel can be improved, enhance the performance of PMOS device, for the top layer of NMOS device
Metal, the decrystallized injection of further progress guarantee the property of NMOS device so that the tensile stress of the top-level metallic of NMOS device reduces
Can, meanwhile, ALD technique can guarantee top-level metallic grid slot filling capacity.
In the present invention, this method can be for applied in the rear grid technique of FinFET, or is applied to normal
In the rear grid technique of the planar device of rule.Technical solution and technical effect in order to better understand the present invention, below with reference to
The embodiment of the manufacturing method of FinFET is described in detail in flow chart Fig. 1, and the manufacturing process of the embodiment is shown
It is intended to the diagrammatic cross-section along fin direction.
Firstly, providing semiconductor substrate 100, pseudo- gate device is formed on a semiconductor substrate, with reference to shown in Fig. 2.
In embodiments of the present invention, the semiconductor substrate 100 can be for Si substrate, Ge substrate, SiGe substrate, SOI (absolutely
Silicon on edge body, Silicon On Insulator) or GOI (germanium on insulator, Germanium On Insulator) etc., may be used also
Think the substrate including other elements semiconductor or compound semiconductor, such as GaAs, InP or SiC etc. can also be lamination knot
Structure, such as Si/SiGe etc. can be with other epitaxial structures, such as SGOI (silicon germanium on insulator) etc..
In the present embodiment, the semiconductor substrate 100 is body silicon substrate, has PMOS device region 1001 on the substrate
With NMOS device region 1002, to be respectively formed NMOS and PMOS device.
In a specific embodiment, pseudo- gate device can be provided as follows.
Trap doping is carried out it is possible, firstly, to use conventional methods, the doping of p-type particle is carried out for N-type device, for P
Type device carries out the doping of N-type particle, is formed in the substrate 100 of body silicon well region (not shown go out).
Then, using lithographic technique, such as the method for RIE (reactive ion etching), etched substrate 100 form fin 102 and
Afterwards, the filling of the isolated material of silica is carried out, and carries out flatening process, such as carrying out chemical-mechanical planarization then can
To use wet etching, such as using the isolated material of the certain thickness silica of hydrofluoric acid erosion removal, retain part
Isolated material is between fin, so as to form isolation (not shown go out).
Then, pseudo- gate dielectric layer and dummy grid material are deposited, and is patterned, forms gate dielectric layer on the surface of fin
104 and dummy grid 106, pseudo- gate dielectric layer can be silica, can be formed using thermal oxidation method, dummy grid material can be non-
Crystal silicon, polysilicon etc., in the present embodiment, dummy grid material is amorphous silicon, then, forms side wall 108, side in the side wall of dummy grid
Wall can be single or multi-layer structure, such as can be silica, silicon oxynitride, silicon nitride or their lamination.Then, in puppet
It forms source-drain area on the fin of grid two sides, in the present embodiment, is doped simultaneously by epitaxial growth (EPI), at the both ends of fin
Form source-drain area 110.Then, the deposit of interlayer dielectric layer, such as undoped silica (SiO are carried out2), doping silica
(such as Pyrex, boron-phosphorosilicate glass), silicon nitride (Si3N4) or other low k dielectric materials, then planarized, such as
CMP (chemically mechanical polishing), until exposure dummy grid 106, forms interlayer dielectric layer 109.So far, it forms in rear grid technique
Pseudo- gate device.
Then, dummy grid is removed, opening 112 is formed, with reference to shown in Fig. 3.
In the present embodiment, can remove dummy grid using wet etching in one embodiment can be by centainly matching
The dummy grid 106 of tetramethylammonium hydroxide (TMAH) the removal amorphous silicon of specific concentration, and pseudo- gate dielectric layer 104 is further removed,
To form opening 112, further, after removing pseudo- gate dielectric layer, required gate dielectric layer can be re-formed, improve device
The interfacial characteristics of part in the present embodiment, can remove pseudo- gate dielectric layer 104 using diluted BOE, meanwhile, on the surface of fin
A bed boundary oxide layer 114 is formed, as shown in Figure 3.
Then, deposit substitutes gate dielectric layer 116 again, as shown in figure 4, substitution gate dielectric layer 116 can be high K medium material
Material, (for example, being compared with silica, the material with high dielectric constant) or other suitable dielectric materials, high K medium material example
Such as hafnium base oxide, HFO2, HfSiO, HfSiON, HfTaO, HfTiO etc., and carry out PDA (Post Deposition
Anneal thermal annealing), annealing temperature can be 450 DEG C, time 15s.
Then, deposited metal gate, metal gates may include more metal layers, such as Ti, TiAlx、TiALC、TiN、
TaNx、HfN、TiCx、TaCx, W etc., in the present embodiment, metal gates include the first metal barrier, the gold stacked gradually
Belong to work-function layer and the second metal barrier, metal work function layer can be respectively formed for NMOS device and PMOS device, with
The work function for adjusting different components respectively, improves the performance of device, specifically, firstly, as shown in figure 5, deposit the first metal resistance
Barrier 118, first metal barrier 118 can be TiN or WN etc., which avoids the metal on upper layer from diffusing to gate medium
In layer and channel, then, as shown in fig. 6, forming first on first metal barrier 118 in PMOS device region 1001 respectively
Metal work function layer 120 forms the second metal work function layer on first metal barrier 118 in NMOS device region 1002
122, the first metal work function layer 120 adjusts the effective work function of PMOS device, the second metal function such as can be for Ti, TiN
Function layer 122 adjusts the effective work function of NMOS device such as can be for TiAl, TiALC, then, deposit the second metal resistance
Barrier 124, the second metal barrier 124 can be TiN or WN etc., which avoids the metal on upper layer from diffusing to metal work function
In several layers and gate dielectric layer.
Then, tungsten is filled, the filling of tungsten is carried out using ALD technique, precursor gas uses silane (SiH4) with
Tungsten hexafluoride (WF6) or borine (B2H6) and tungsten hexafluoride (WF6)。
In some embodiments, for NMOS and PMOS device region, metal can be carried out using identical precursor gas
The deposit of tungsten, can also deposit the tungsten of NMOS and PMOS device region respectively using different precursor gas, before this two groups
Purging body deposits the tungsten to be formed, and all has the function of tensile stress on channel vertical direction, and PMOS device ditch can be improved
The carrier mobility in road.
In the present embodiment, it is preferred that as shown in fig. 7, in PMOS device region, using silane (SiH4) and tungsten hexafluoride
(WF6) precursor gas, carry out the filling of 1001 tungsten 130 of PMOS device region, and planarized, this group of precursor gas
The tungsten of formation has bigger tensile stress, conducive to the raising of PMOS device performance；Then, the gold of covering PMOS area filling
Belong to tungsten, by NMOS area be open in filling tungsten remove；Then, using borine (B2H6) and tungsten hexafluoride (WF6) before
Purging body, carries out the filling of the tungsten 132 in NMOS device region 1002, and is planarized, thus in NMOS device region
Opening in filling by precursor gas borine (B2H6) and tungsten hexafluoride (WF6) tungsten that is formed, the deposit of this group of precursor gas
Tungsten, compared with silane (SiH4) and tungsten hexafluoride (WF6) precursor gas deposit tungsten, have lesser tensile stress, it is right
The channel of NMOS device influences smaller.
Then, to the tungsten in NMOS device region 1002, decrystallized injection is carried out.
Specifically, firstly, on PMOS device region 1001 mask film covering layer 134, as shown in figure 8, mask layer 134 can be with
Decrystallized injection, the grain of decrystallized injection then are carried out to the tungsten in NMOS device region 1002 for hard exposure mask or mask layer
Son can be Ge, N, F etc., and decrystallized injection does not change the electric property of the tungsten in NMOS device region 1002, only changes
The structure distribution of its crystal inside discharges the tensile stress of the tungsten in NMOS device region, reduces tungsten to NMOS device
Channel influences smaller.
In the present embodiment, the particle of preferably amorphous injection is Ge, and the process conditions of decrystallized injection can be with are as follows: injection
Energy is 0.5-30keV, and the dosage of injection is 5E14-5E16/cm2。
Then, as shown in figure 9, removing mask layer 134, and flatening process is carried out, until exposing the second metal barrier
Layer 124 forms the top-level metallic 130,132 of tungsten in the opening.
So far, the semiconductor devices of the embodiment of the present invention is formd, later, can according to need, complete subsequent device
Processing, such as form contact and interconnection architecture etc..
The above described is only a preferred embodiment of the present invention, being not intended to limit the present invention in any form.
Although the present invention has been disclosed in the preferred embodiments as above, however, it is not intended to limit the invention.It is any to be familiar with ability
The technical staff in domain, without departing from the scope of the technical proposal of the invention, all using in the methods and techniques of the disclosure above
Appearance makes many possible changes and modifications or equivalent example modified to equivalent change to technical solution of the present invention.Therefore,
Anything that does not depart from the technical scheme of the invention are made to the above embodiment any simple according to the technical essence of the invention
Modification, equivalent variations and modification, all of which are still within the scope of protection of the technical scheme of the invention.
Claims (8)
1. a kind of manufacturing method of semiconductor devices characterized by comprising
Semiconductor substrate is provided, there is the opening for removing and being formed after pseudo- grid on the substrate；
Using ALD technique, the top-level metallic of tungsten is filled in the opening, precursor gas is silane or borine and tungsten hexafluoride,
And the top-level metallic to NMOS device region, carry out decrystallized injection；
The step of top-level metallic of filling tungsten includes: in the opening
Using ALD technique, the top-level metallic of tungsten is filled in the opening in PMOS device region, precursor gas is silane and six
Tungsten fluoride；
Using ALD technique, the top-level metallic of tungsten is filled in the opening in NMOS device region, precursor gas is borine and six
Tungsten fluoride.
2. the manufacturing method according to claim 1, which is characterized in that the particle of decrystallized injection is Ge.
3. manufacturing method according to claim 2, which is characterized in that the process conditions of decrystallized injection are as follows: the energy of injection
Amount is 0.5-30keV, and the dosage of injection is 5E14-5E16/cm2。
4. the manufacturing method according to claim 1, which is characterized in that in the opening fill tungsten top-level metallic and
The step of carrying out decrystallized injection include:
The deposit of tungsten is carried out using ALD technique, precursor gas is silane or borine and tungsten hexafluoride；
Carry out flatening process；
The mask film covering layer on PMOS device region；
Carry out decrystallized injection；
Remove mask layer；
Tungsten except removal opening, to form the top-level metallic of tungsten in the opening.
5. the manufacturing method according to claim 1, which is characterized in that before carrying out ALD technique, further comprise the steps of:
High-k gate dielectric layer is formed on the inner wall of opening, and carries out thermal annealing.
6. manufacturing method according to claim 5, which is characterized in that the temperature of thermal annealing is 450 DEG C, time 15s.
7. manufacturing method according to claim 5, which is characterized in that before carrying out ALD technique, form high-k gate dielectric
It is further comprised the steps of: after layer
The first metal barrier is formed on high-k gate dielectric layer；
Metal work function layer is formed on the first metal barrier；
The second metal barrier is formed on metal work function layer.
8. manufacturing method according to claim 7, which is characterized in that first metal barrier or the second metal barrier
Layer is TiN or WN.
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| US20120146159A1 (en) * | 2010-11-30 | 2012-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for overlay marks |
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| US20120146159A1 (en) * | 2010-11-30 | 2012-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for overlay marks |
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