CN113224067A - Control grid back-etching method of NOR Flash Cell area, storage medium and control module - Google Patents
Control grid back-etching method of NOR Flash Cell area, storage medium and control module Download PDFInfo
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- CN113224067A CN113224067A CN202110466875.0A CN202110466875A CN113224067A CN 113224067 A CN113224067 A CN 113224067A CN 202110466875 A CN202110466875 A CN 202110466875A CN 113224067 A CN113224067 A CN 113224067A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
- H10B41/44—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a control gate layer also being used as part of the peripheral transistor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/60—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the control gate being a doped region, e.g. single-poly memory cell
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
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Abstract
The invention discloses a control grid back-etching method for a NOR Flash Cell area, which comprises the following steps: controlling the deposition of polycrystalline silicon; defining a cell area by photoetching, opening the cell area, removing photoresist in the cell area, and reserving photoresist in a peripheral area; etching to remove a part of polycrystalline silicon, and reducing the overall height of the polycrystalline silicon in the cell area; defining a cell area Drain end and a GATE end through photoetching and etching processes, and executing subsequent processes. The invention changes the appearance of the junction of the cell area and the peripheral circuit by improving the CGEB PH process, improves the on-line silicon residual defect and can improve the reliability of a 55nm NOR product.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a control grid back-etching method for a NOR Flash Cell area. The invention also relates to a computer readable storage medium for executing the steps in the NOR Flash Cell area control gate etching back method, and a control module for executing the steps in the NOR Flash Cell area control gate etching back method.
Background
flash memory is a non-volatile memory that can erase and reprogram blocks of memory cells called blocks. The write operation of any flash device can only be performed in empty or erased cells, so in most cases, the erase must be performed before the write operation can be performed.
Nor flash is one of the two major non-volatile flash technologies on the market. The characteristic of the Nor flash process is that the height of a cell region Poly (cell region polysilicon) is higher than that of a Peri region (peripheral region polysilicon); meanwhile, the drift end space of the 55Nor process cell region is reduced from the previous 260nm to the current 200nm, so that ILD filling is more difficult and BL Bridge is easy to appear.
Therefore, the CG Poly etch back (CGEB) process is applied to reduce the Poly height reduction in the Cell region, resulting in a final CG + FG (control gate and floating gate) height reduction, easier ILD filling, and reduced void risk.
However, after the new process is on line, poly residual (silicon residual) is remained at the junction of the cell and the peri after the CG etch (control gate etch), and cannot be removed optimally by the CG etch or poly etch process (polysilicon etch process). The silicon residual defect seriously affects monitoring of other types of defects of a production line, and if the defect is broken and remains in a cell area, a reliability risk exists.
Disclosure of Invention
In this summary, a series of simplified form concepts are introduced that are simplifications of the prior art in this field, which will be described in further detail in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
The technical problem to be solved by the invention is to provide a NOR Flash Cell area control gate back etching method which can avoid silicon residue defects caused by height difference of a Cell area Poly (Cell area polysilicon) and a Peri area (peripheral area polysilicon).
Correspondingly, the invention also provides a computer readable storage medium for executing the steps in the NOR Flash Cell area control gate back etching method, and a control module for executing the steps in the NOR Flash Cell area control gate back etching method.
In order to solve the technical problem, the control grid back-etching method for the NOR Flash Cell area provided by the invention comprises the following steps:
s1) controlling gate polysilicon deposition;
s2) defining a cell area by photoetching, opening the cell area, removing photoresist in the cell area, and reserving photoresist in a peripheral area;
s3) etching to remove part of the polysilicon and reduce the overall height of the polysilicon in the cell area; the CGEB process has the advantages that the depth-to-width ratio of the groove behind the CG ET is reduced, so that ILDHDP filling is facilitated;
s4) defining a Drain end and a GATE end of the cell area through photoetching and etching processes, and executing subsequent processes.
Optionally, the control gate etching back method for the NOR Flash Cell area is further improved, and when step S2) is implemented, the negative photoresist is coated after the anti-reflection coating is coated, and the Cell area pattern is defined by exposure and development of the first mask.
Optionally, the control gate etching back method for the NOR Flash Cell area is further improved, and when step S2) is implemented, the positive photoresist is coated after the anti-reflection coating is coated, and a Cell area pattern is defined by exposure and development using a second mask.
Optionally, the control gate back etching method for the NOR Flash Cell area is further improved, and in step S3), after the overall height of the polysilicon in the Cell area is reduced, the difference between the polysilicon height in the Cell area and the polysilicon height in the peripheral area is less than or equal to 450 angstroms.
To solve the above technical problem, the present invention provides a computer readable storage medium for use in any one of the steps of the NOR Flash Cell area control gate etching back method.
In order to solve the technical problems, the invention provides a control module of a control grid back etching process of a NOR Flash Cell area, which can be integrated in a semiconductor machine and controls the semiconductor machine to execute the following steps;
s1) controlling gate polysilicon deposition;
s2) defining a cell area graph by photoetching, opening the cell area, removing photoresist in the cell area, and reserving photoresist in a peripheral area;
s3) etching to remove part of the polysilicon and reduce the overall height of the polysilicon in the cell area;
s4) defining a Drain end and a GATE end of the cell area through photoetching and etching processes, and executing subsequent processes.
Optionally, the control module of the NOR Flash Cell area control gate etching back process is further improved, and when step S2) is implemented, the negative photoresist is coated after the anti-reflection coating is coated, and a Cell area pattern is defined by exposure and development of the first mask.
Optionally, the control module of the NOR Flash Cell area control gate etching back process is further improved, and when step S2) is implemented, the positive photoresist is coated after the anti-reflection coating is coated, and a Cell area pattern is defined by exposure and development using a second mask.
Optionally, the control module of the NOR Flash Cell area control gate etching back process is further improved, and in step S3), after the overall height of the Cell area polysilicon is reduced, the difference between the Cell area polysilicon height and the peripheral area polysilicon height is less than or equal to 450 angstroms.
The principle and the technical effect of the invention are as follows:
the method aims at the technical problem of poly residual (silicon residue, one type of quality inspection online defect) generated after an online CGEB (Cell area control gate etch back) process of a 55nm NOR product. The invention solves the problem of poly residual by changing the CGEB PH (photoetching) process.
In the prior art, a CGEB PH process is used for coating photoresist, exposing and developing, and an anti-reflection coating is not used, so that a serious silicon residue defect exists at a junction during subsequent CG ET (Cell area control gate etching). The invention changes the CGEB PH process into the steps of firstly coating an anti-reflection coating (BARC film), coating Photoresist (PR), exposing and developing. The mask and the Photoresist (PR) used can be 2 types, namely a first mask1+ negative photoresist and a second mask2+ positive photoresist.
Compared with the prior art, the biggest change after adding BARC coating is that the section slicing result shows the appearance difference of the boundary of a cell area and a peripheral circuit: referring to fig. 1, it shows the appearance of the interface between the cell area and the peripheral circuit in the prior art, which is approximately a right angle; referring to fig. 2, the appearance of the junction between the cell area and the peripheral circuit is changed from a right angle to an oblique angle by adopting the process of the invention, and the change of the appearance is beneficial to completely etching the junction during subsequent CG ET etching, thereby removing silicon residues, improving the defect of the silicon residues on line and improving the reliability of a 55nm NOR product.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention, are incorporated in and constitute a part of this specification. The drawings are not necessarily to scale, however, and may not be intended to accurately reflect the precise structural or performance characteristics of any given embodiment, and should not be construed as limiting or restricting the scope of values or properties encompassed by exemplary embodiments in accordance with the invention. The invention will be described in further detail with reference to the following detailed description and accompanying drawings:
FIG. 1 is a schematic diagram of the interface between a cell area and a peripheral circuit in a conventional process.
FIG. 2 is a schematic diagram of the cross-point between the cell region and the peripheral circuit according to the present invention.
FIG. 3 is a schematic view of the topography of the steps of the present invention.
FIG. 4 is a schematic flow chart of a first embodiment of the present invention.
FIG. 5 is a flow chart illustrating a second embodiment of the present invention.
FIG. 6 is a flow chart of a third embodiment of the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and technical effects of the present invention will be fully apparent to those skilled in the art from the disclosure in the specification. The invention is capable of other embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the general spirit of the invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. The following exemplary embodiments of the present invention may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. It is to be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the technical solutions of these exemplary embodiments to those skilled in the art.
A first embodiment;
as shown in fig. 4, the present invention provides a control gate back etching method for a NOR Flash Cell area, which is characterized by comprising the following steps:
s1) controlling gate polysilicon deposition;
s2) defining a cell area by photoetching, opening the cell area, removing photoresist in the cell area, and reserving photoresist in a peripheral area;
s3) etching to remove part of the polysilicon and reduce the overall height of the polysilicon in the cell area;
s4) defining a Drain end and a GATE end of the cell area through photoetching and etching processes, and executing subsequent processes.
A second embodiment;
as shown in fig. 5, the present invention provides a control gate back etching method for a NOR Flash Cell area, which is characterized by comprising the following steps:
s1) controlling gate polysilicon deposition;
s2) coating an anti-reflection coating, then coating a negative photoresist, defining a cell area graph by utilizing first mask exposure and development, opening a cell area, removing photoresist in the cell area, and reserving photoresist in a peripheral area;
s3) etching to remove part of polysilicon, and reducing the overall height of the polysilicon in the Cell area, wherein the difference between the height of the polysilicon in the Cell area and the height of the polysilicon in the peripheral area is less than or equal to 450 angstroms;
s4) defining a Drain end and a GATE end of the cell area through photoetching and etching processes, and executing subsequent processes.
A third embodiment;
as shown in fig. 6, the present invention provides a control gate back etching method for a NOR Flash Cell area, which is characterized by comprising the following steps:
s1) controlling gate polysilicon deposition;
s2) coating an anti-reflection coating, then coating a positive photoresist, defining a cell area graph by utilizing a second mask plate for exposure and development, opening a cell area, removing photoresist in the cell area, and reserving photoresist in a peripheral area;
s3) etching to remove part of polysilicon, and reducing the overall height of the polysilicon in the Cell area, wherein the difference between the height of the polysilicon in the Cell area and the height of the polysilicon in the peripheral area is less than or equal to 450 angstroms;
s4) defining a Drain end and a GATE end of the cell area through photoetching and etching processes, and executing subsequent processes.
A fourth embodiment;
the present invention provides a computer-readable storage medium for executing the steps of the NOR Flash Cell area control gate etch-back method according to any one of the first to third embodiments.
A fifth embodiment;
the invention provides a control grid back-etching process control module of a NOR Flash Cell area, which can be integrated on a semiconductor machine through a computer programming technology and controls the semiconductor machine to execute the following steps;
s1) controlling gate polysilicon deposition;
s2) defining a cell area graph by photoetching, opening the cell area, removing photoresist in the cell area, and reserving photoresist in a peripheral area;
s3) etching to remove part of the polysilicon and reduce the overall height of the polysilicon in the cell area;
s4) defining a Drain end and a GATE end of the cell area through photoetching and etching processes, and executing subsequent processes.
A sixth embodiment;
the invention provides a control grid back-etching process control module of a NOR Flash Cell area, which can be integrated on a semiconductor machine through a computer programming technology and controls the semiconductor machine to execute the following steps;
s1) controlling gate polysilicon deposition;
s2) coating an anti-reflection coating, then coating a negative photoresist, defining a cell area graph by utilizing first mask exposure and development, opening a cell area, removing photoresist in the cell area, and reserving photoresist in a peripheral area;
s3) etching to remove part of polysilicon, and reducing the overall height of the polysilicon in the Cell area, wherein the difference between the height of the polysilicon in the Cell area and the height of the polysilicon in the peripheral area is less than or equal to 450 angstroms;
s4) defining a Drain end and a GATE end of the cell area through photoetching and etching processes, and executing subsequent processes.
A seventh embodiment;
the invention provides a control grid back-etching process control module of a NOR Flash Cell area, which can be integrated on a semiconductor machine through a computer programming technology and controls the semiconductor machine to execute the following steps;
s1) controlling gate polysilicon deposition;
s2) coating an anti-reflection coating, then coating a positive photoresist, defining a cell area graph by utilizing a second mask plate for exposure and development, opening a cell area, removing photoresist in the cell area, and reserving photoresist in a peripheral area;
s3) etching to remove part of polysilicon, and reducing the overall height of the polysilicon in the Cell area, wherein the difference between the height of the polysilicon in the Cell area and the height of the polysilicon in the peripheral area is less than or equal to 450 angstroms;
s4) defining a Drain end and a GATE end of the cell area through photoetching and etching processes, and executing subsequent processes.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The present invention has been described in detail with reference to the specific embodiments and examples, but these are not intended to limit the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (9)
1. A control grid back etching method for a NOR Flash Cell area is characterized by comprising the following steps:
s1) controlling gate polysilicon deposition;
s2) defining a cell area by photoetching, opening the cell area, removing photoresist in the cell area, and reserving photoresist in a peripheral area;
s3) etching to remove part of the polysilicon and reduce the overall height of the polysilicon in the cell area;
s4) defining a Drain end and a GATE end of the cell area through photoetching and etching processes, and executing subsequent processes.
2. The NOR Flash Cell area control gate etch back method of claim 1, wherein:
step S2) is carried out, anti-reflection coating is coated, negative photoresist is coated, and the first mask is used for exposure and development to define the pattern of the cell area.
3. The NOR Flash Cell area control gate etch back method of claim 1, wherein:
step S2) is performed, the anti-reflective coating is applied, then the positive photoresist is applied, and the cell area pattern is defined by exposure and development using the second mask.
4. The NOR Flash Cell area control gate etch back method of claim 1, wherein:
step S3), after the overall height of the polysilicon in the Cell area is reduced, the difference between the polysilicon height in the Cell area and the polysilicon height in the peripheral area is less than or equal to 450 angstroms.
5. A computer readable storage medium for performing the steps in the NOR Flash Cell area control gate etch back method of any of claims 1-4.
6. A NOR Flash Cell area control grid back etching process control module can be integrated in a semiconductor machine and is characterized in that the control module controls the semiconductor machine to execute the following steps;
s1) controlling gate polysilicon deposition;
s2) defining a cell area graph by photoetching, opening the cell area, removing photoresist in the cell area, and reserving photoresist in a peripheral area;
s3) etching to remove part of the polysilicon and reduce the overall height of the polysilicon in the cell area;
s4) defining a Drain end and a GATE end of the cell area through photoetching and etching processes, and executing subsequent processes.
7. The NOR Flash Cell area control gate etch-back process control module of claim 6, wherein:
step S2) is carried out, anti-reflection coating is coated, negative photoresist is coated, and the first mask is used for exposure and development to define the pattern of the cell area.
8. The NOR Flash Cell area control gate etch-back process control module of claim 6, wherein:
step S2) is performed, the anti-reflective coating is applied, then the positive photoresist is applied, and the cell area pattern is defined by exposure and development using the second mask.
9. The NOR Flash Cell area control gate etch back process control module of any of claims 6-8, wherein: step S3), after the overall height of the polysilicon in the Cell area is reduced, the difference between the polysilicon height in the Cell area and the polysilicon height in the peripheral area is less than or equal to 450 angstroms.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116779431A (en) * | 2023-08-07 | 2023-09-19 | 杭州谱析光晶半导体科技有限公司 | Treatment method for rounding top corners of polycrystalline silicon |
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| CN106328656A (en) * | 2016-08-22 | 2017-01-11 | 上海华力微电子有限公司 | Process method for adding ILD (Inter Layer Deposition) filling window of adjustable control gate poly |
| CN112652626A (en) * | 2020-12-18 | 2021-04-13 | 华虹半导体(无锡)有限公司 | NORD flash manufacturing method, device and storage medium |
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- 2021-04-28 CN CN202110466875.0A patent/CN113224067B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106328656A (en) * | 2016-08-22 | 2017-01-11 | 上海华力微电子有限公司 | Process method for adding ILD (Inter Layer Deposition) filling window of adjustable control gate poly |
| CN112652626A (en) * | 2020-12-18 | 2021-04-13 | 华虹半导体(无锡)有限公司 | NORD flash manufacturing method, device and storage medium |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116779431A (en) * | 2023-08-07 | 2023-09-19 | 杭州谱析光晶半导体科技有限公司 | Treatment method for rounding top corners of polycrystalline silicon |
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