CN116507130A - Method for improving GIDL electric leakage of SONOS memory - Google Patents
Method for improving GIDL electric leakage of SONOS memory Download PDFInfo
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- CN116507130A CN116507130A CN202310539336.4A CN202310539336A CN116507130A CN 116507130 A CN116507130 A CN 116507130A CN 202310539336 A CN202310539336 A CN 202310539336A CN 116507130 A CN116507130 A CN 116507130A
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- 238000000034 method Methods 0.000 title claims abstract description 29
- 238000002347 injection Methods 0.000 claims abstract description 22
- 239000007924 injection Substances 0.000 claims abstract description 22
- 239000004065 semiconductor Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000002513 implantation Methods 0.000 claims abstract description 8
- 238000005468 ion implantation Methods 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims abstract description 4
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 2
- 238000000206 photolithography Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000671 immersion lithography Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0895—Tunnel injectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention provides a method for improving the leakage of a GIDL of a SONOS memory, which provides a semiconductor structure comprising: the regions on the substrate include SONOS device regions and Core device regions; a gate oxide layer on the substrate; grid structures are respectively formed on the grid oxide layers of the SONOS device region and the Core device region; an oxide layer covering the grid structure is formed on the semiconductor structure, and the oxide layer covers the grid oxide layer outside the grid structure; depositing a SiN layer on the oxide layer; defining an LDD injection region of the SONOS device region, removing the SiN layer except the side wall of the grid structure on the SONOS device region according to the LDD injection region, and forming the SiN layer attached to the side wall of the grid structure of the SONOS device region into a side wall; performing ion implantation in the LDD implantation region of the SONOS device region along the side wall; and removing the side wall, and then removing the SiN layer of the Core device region. And forming an SIN side wall in the SONOS device region, reducing the overlapping region of the SONOS LDD injection region and the gate oxide layer below the gate structure of the SONOS LDD injection region, and achieving the purpose of reducing the GIDL electric leakage.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for improving the leakage of a GIDL of a SONOS memory.
Background
SONOS memory relies on FN tunneling caused by a high voltage difference across the ONO structure to store electrons. Higher voltages (e.g., 6V or-3V, etc.) are required during Program or Erase, and are generated by means of charge pumps in the circuit. If the leakage of the SONOS device is too high, the working performance of the charge pump is affected, so that the voltage cannot be raised to a desired voltage value, and the operation of the SONOS device is affected. Because of the higher voltage difference, the GIDL leakage is one of the main leakage modes of the SONOS memory, and the control of the GIDL leakage can greatly improve the performance of the SONOS device.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a method for improving GIDL leakage of a SONOS memory device, which is used for solving the GIDL leakage problem of the SONOS memory device in the prior art.
To achieve the above and other related objects, the present invention provides a method for improving the leakage of a GIDL of a SONOS memory, at least comprising:
step one, providing a semiconductor structure, wherein the semiconductor structure comprises: a substrate; the region on the substrate comprises a SONOS device region and a Core device region; a gate oxide layer on the substrate; grid structures are respectively formed on the grid oxide layers of the SONOS device region and the Core device region; an oxide layer covering the grid structure is formed on the semiconductor structure, and the oxide layer covers the grid oxide layer outside the grid structure;
depositing a SiN layer on the oxide layer;
step three, defining an LDD injection region of the SONOS device region, removing the SiN layer except the side wall of the grid structure on the SONOS device region according to the LDD injection region, and forming the SiN layer attached to the side wall of the grid structure of the SONOS device region into a side wall;
step four, ion implantation is carried out in the LDD implantation region of the SONOS device region along the side wall;
and fifthly, removing the side wall, and then removing the SiN layer of the Core device region.
Preferably, in the second step, the SiN layer is deposited by adopting a CVD or furnace tube process, and the thickness of the deposited SiN layer is 10-1000 angstroms.
Preferably, in the third step, the LDD implantation region of the SONOS device region is defined by photoresist coating and developing by a photolithography process.
Preferably, in the third step, the LDD injection regions are distributed on two sides of the gate structure of the SONOS device region.
Preferably, in the fourth step, ion implantation is not performed in the region directly under the sidewall.
Preferably, in the fifth step, the side wall is removed by dry etching.
Preferably, in the fifth step, the SiN layer of the Core device region is removed by wet etching.
As described above, the method for improving the GIDL leakage of the SONOS memory device of the present invention has the following advantages: the method forms the SIN side wall in the SONOS device region by photoetching the LDD injection region of the SONOS device region, reduces the overlapping region of the SONOS LDD injection region and the grid oxide layer below the grid electrode structure of the SONOS device region, and achieves the purpose of reducing the GIDL electric leakage. And after the LDD injection is finished, removing SIN of other areas except the SONOS by etching, so that the SONOS side wall process is ensured not to introduce a new film layer into the logic area, and the influence on the logic device is small.
Drawings
Fig. 1 to fig. 4 are schematic structural views of process stages of a method for improving the GIDL leakage of a SONOS memory according to the present invention;
fig. 5 is a flowchart showing a method for improving the leakage of the GIDL of the SONOS memory.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1 to 5. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
The invention provides a method for improving the leakage of a SONOS memory GIDL, as shown in FIG. 5, FIG. 5 shows a flow chart of the method for improving the leakage of the SONOS memory GIDL, which at least comprises the following steps:
step one, providing a semiconductor structure, wherein the semiconductor structure comprises: a substrate; the region on the substrate comprises a SONOS device region and a Core device region; a gate oxide layer on the substrate; grid structures are respectively formed on the grid oxide layers of the SONOS device region and the Core device region; an oxide layer covering the grid structure is formed on the semiconductor structure, and the oxide layer covers the grid oxide layer outside the grid structure; as shown in fig. 1, the first step provides a semiconductor structure, which includes: a substrate 01; the regions on the substrate 01 include a SONOS Device region (SONOS Device) and a Core Device region (Core Device); a gate oxide layer on the substrate 01; gate structures (a gate structure 02 of the SONOS device region and a gate structure 03 of the Core device region) are respectively formed on the gate oxide layers of the SONOS device region and the Core device region; an oxide layer is formed on the semiconductor structure to cover the gate structure, and the oxide layer covers a gate oxide layer outside the gate structure, and the gate oxide layer and the oxide layer in fig. 1 are collectively denoted by 04.
Depositing a SiN layer on the oxide layer; as shown in fig. 1, this step two deposits a SiN layer 05 on the oxide layer.
In the second step of the embodiment, the SiN layer is deposited by CVD or furnace tube process, and the thickness of the deposited SiN layer is 10-1000 angstroms.
Step three, defining an LDD injection region of the SONOS device region, removing the SiN layer except the side wall of the grid structure on the SONOS device region according to the LDD injection region, and forming the SiN layer attached to the side wall of the grid structure of the SONOS device region into a side wall;
in the third step of the present embodiment, the LDD implantation region of the SONOS device region is defined by photoresist coating and developing by a photolithography process.
In the third step of this embodiment, the LDD implant regions are distributed on two sides of the gate structure of the SONOS device region.
As shown in fig. 3, the LDD implantation region of the SONOS device region is defined in the third step of the present embodiment by photoresist coating and developing the LDD implantation region of the SONOS device region. Including but not limited to, gumming and developing using an Iline, KRF, or Immersion lithography machine. Removing the SiN layer except the side wall of the grid structure 02 on the SONOS device region according to the LDD injection region, and forming the SiN layer attached to the side wall of the grid structure of the SONOS device region into a side wall 06; the area pointed by the arrow in fig. 3 is the LDD injection area, and is distributed on two sides of the gate structure of the SONOS device area.
Step four, ion implantation is carried out in the LDD implantation region of the SONOS device region along the side wall; as shown in fig. 3, in the fourth embodiment, the region directly under the sidewall is not implanted. The overlapped area between the SONOS LDD injection area and the lower part of the grid oxide layer is reduced, and the purpose of reducing the GIDL electric leakage is achieved.
And fifthly, removing the side wall, and then removing the SiN layer of the Core device region.
In the fifth step of the present embodiment, the side wall is removed by dry etching. And fifthly, removing the SiN layer of the Core device region by adopting a wet etching mode. As shown in fig. 4, fig. 4 is a schematic structural diagram of the SiN layer removed from the side wall and the Core device region according to the present invention.
In summary, the method forms the SIN sidewall in the SONOS device region by photolithography of the LDD injection region of the SONOS device region, so as to reduce the overlapping region of the SONOS LDD injection region and the gate oxide layer below the gate structure, thereby achieving the purpose of reducing GIDL leakage. And after the LDD injection is finished, removing SIN of other areas except the SONOS by etching, so that the SONOS side wall process is ensured not to introduce a new film layer into the logic area, and the influence on the logic device is small. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (7)
1. A method for improving the leakage of a SONOS memory GIDL, comprising at least:
step one, providing a semiconductor structure, wherein the semiconductor structure comprises: a substrate; the region on the substrate comprises a SONOS device region and a Core device region; a gate oxide layer on the substrate; grid structures are respectively formed on the grid oxide layers of the SONOS device region and the Core device region; an oxide layer covering the grid structure is formed on the semiconductor structure, and the oxide layer covers the grid oxide layer outside the grid structure;
depositing a SiN layer on the oxide layer;
step three, defining an LDD injection region of the SONOS device region, removing the SiN layer except the side wall of the grid structure on the SONOS device region according to the LDD injection region, and forming the SiN layer attached to the side wall of the grid structure of the SONOS device region into a side wall;
step four, ion implantation is carried out in the LDD implantation region of the SONOS device region along the side wall;
and fifthly, removing the side wall, and then removing the SiN layer of the Core device region.
2. The method of improving the SONOS memory GIDL-leakage of claim 1, characterized by: and in the second step, the SiN layer is deposited by adopting a CVD or furnace tube process, and the thickness of the deposited SiN layer is 10-1000 angstroms.
3. The method of improving the SONOS memory GIDL-leakage of claim 1, characterized by: and step three, defining an LDD injection region of the SONOS device region through photoresist coating and developing of a photoetching process.
4. The method of improving the SONOS memory GIDL-leakage of claim 1, characterized by: and in the third step, the LDD injection regions are distributed on two sides of the grid structure of the SONOS device region.
5. The method of improving the SONOS memory GIDL-leakage of claim 1, characterized by: and in the fourth step, ion implantation is not carried out in the region right below the side wall.
6. The method of improving the SONOS memory GIDL-leakage of claim 1, characterized by: and step five, removing the side wall in a dry etching mode.
7. The method of improving the SONOS memory GIDL-leakage of claim 1, characterized by: and fifthly, removing the SiN layer of the Core device region by adopting a wet etching mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310539336.4A CN116507130A (en) | 2023-05-12 | 2023-05-12 | Method for improving GIDL electric leakage of SONOS memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310539336.4A CN116507130A (en) | 2023-05-12 | 2023-05-12 | Method for improving GIDL electric leakage of SONOS memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116507130A true CN116507130A (en) | 2023-07-28 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310539336.4A Pending CN116507130A (en) | 2023-05-12 | 2023-05-12 | Method for improving GIDL electric leakage of SONOS memory |
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| Country | Link |
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| CN (1) | CN116507130A (en) |
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- 2023-05-12 CN CN202310539336.4A patent/CN116507130A/en active Pending
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