CN116033755A

CN116033755A - Method for optimizing uniformity of oxide layer blocked by ONO gate dielectric of SONOS memory

Info

Publication number: CN116033755A
Application number: CN202310150280.3A
Authority: CN
Inventors: 周家民; 齐瑞生; 黄冠群; 陈昊瑜
Original assignee: Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Current assignee: Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Priority date: 2023-02-21
Filing date: 2023-02-21
Publication date: 2023-04-28

Abstract

The invention provides a method for optimizing the uniformity of an ONO gate dielectric barrier oxide layer of a SONOS memory, wherein a semiconductor structure comprises a semiconductor substrate, and a SONOS region and a selection gate region are defined on the semiconductor substrate; the upper surface of the semiconductor structure is provided with a sacrificial oxide layer covering the selection gate region; a first oxide layer is arranged on the SONOS region and the sacrificial oxide layer, and an ONO layer is arranged on the first oxide layer; photoresist is formed on the SONOS region; removing the photoresist on the SONOS region, and exposing the ONO layer on the SONOS region; forming a second oxide layer on the ONO layer on the exposed SONOS region; removing the second oxide layer; coating photoresist on the semiconductor structure, opening a selection gate region after exposure and development, and reserving the photoresist on the SONOS region; etching to remove the ONO layer and the first oxide layer on the selection gate region; removing the exposed sacrificial oxide layer on the selection gate region; removing the residual photoresist on the semiconductor structure; a barrier oxide layer is formed on the upper surface of the semiconductor structure.

Description

Method for optimizing uniformity of oxide layer blocked by ONO gate dielectric of SONOS memory

Technical Field

The invention relates to the technical field of semiconductors, in particular to a method for optimizing uniformity of an ONO gate dielectric barrier oxide layer of a SONOS memory.

Background

Flash memory (Flash memory) is a new type of nonvolatile semiconductor memory. A typical SONOS memory cell structure consists of a silicon substrate (S) -a tunnel oxide (O) -a charge storage layer silicon nitride (N) -a blocking oxide (O) -a polysilicon gate (S). It uses tunneling of electrons (Fowler-Nordheim tunneling, FN tunneling) for data writing and storage, and injection of holes for data erasing. Unlike the floating gate technology, in which electrons are stored in the floating gate, SONOS is a memory cell that stores charge based on discrete traps in an insulating medium (Si 3N 4), and a silicon dioxide dielectric layer is respectively disposed between the insulating medium layer and the substrate and gate electrode. With the continuous reduction of design dimensions, the requirements for the film quality of the barrier oxide layer are also increasing. Under the existing ONO photoetching reworking process conditions, a byproduct oxide layer with rough surface and poor film quality is easy to grow in the dry etching and wet etching cleaning processes, and a little acid residue is carried out, so that a non-uniform blocking oxide layer grows in the subsequent ISSG, the problem of charge leakage and the like stored in silicon nitride is caused, the problem of coupling between a point and a drift position and a floating gate is caused, and the problems of reliability, low quality and the like of a device are finally caused.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, the present invention is directed to a method for optimizing uniformity of an ONO gate dielectric barrier oxide layer of a SONOS memory, so as to solve the problem that in the prior art, if an ONO lithography process is reworked, an oxide layer or acid residue is easily generated in a control gate region in the process, thereby affecting uniformity of a subsequently deposited barrier oxide layer of the SONOS memory.

To achieve the above and other related objects, the present invention provides a method for optimizing uniformity of an ONO dielectric barrier oxide layer of a SONOS memory, at least comprising:

step one, a semiconductor structure, wherein the semiconductor structure comprises: a semiconductor substrate, wherein a SONOS region and a selection gate region are defined on the semiconductor substrate; the upper surface of the semiconductor structure is provided with a sacrificial oxide layer covering the selection gate region; a first oxide layer is arranged on the SONOS region and the sacrificial oxide layer, and an ONO layer is arranged on the first oxide layer; photoresist is formed on the SONOS region;

step two, removing photoresist on the SONOS region, and exposing the ONO layer on the SONOS region; forming a second oxide layer on the ONO layer on the exposed SONOS region;

step three, removing the second oxide layer;

step four, photoresist is coated on the semiconductor structure, the selection gate region is opened after exposure and development, and the photoresist is reserved on the SONOS region;

step five, etching to remove the ONO layer and the first oxide layer on the selection gate region;

step six, removing the exposed sacrificial oxide layer on the selective gate region;

step seven, removing the residual photoresist on the semiconductor structure;

and step eight, forming a barrier oxide layer on the upper surface of the semiconductor structure.

Preferably, in the first step, an STI region is further disposed on the semiconductor substrate at a side of the select gate region away from the SONOS, and a peripheral logic circuit region is further defined on the semiconductor substrate.

Preferably, the surface of the semiconductor structure in the first step is further formed with a polymer.

Preferably, in the second step, the photoresist on the SONOS region is removed by dry etching and wet etching, and the polymer is removed at the same time.

Preferably, in the third step, the second oxide layer is removed by an acid solution, and the acid solution residue is removed.

Preferably, the second oxide layer is removed in step three using an HF solution.

Preferably, in the fourth step, the peripheral logic circuit region is opened at the same time as the selection gate region is opened after exposure and development.

Preferably, in the fifth step, the ONO layer and the first oxide layer on the select gate region are removed at the same time as the ONO layer and the first oxide layer on the peripheral logic circuit region are also removed.

Preferably, the sacrificial oxide layer on the peripheral logic circuit region is also removed in step six.

Preferably, in the sixth step, the sacrificial oxide layer is removed by wet etching.

Preferably, in the seventh step, the photoresist remaining on the semiconductor structure is removed by wet etching or dry etching, and the polymer generated in the fifth to sixth steps is removed.

Preferably, in the eighth step, the blocking oxide layer is formed by an ISSG method.

As described above, the method for optimizing the uniformity of the ONO grid dielectric barrier oxide layer of the SONOS memory has the following beneficial effects: the invention aims at the SONOS memory, and removes the oxide layer and acid residue generated by the selection gate region in the ONO reworking process by utilizing a wet cleaning method, thereby improving the uniformity of the oxide layer blocking of the SONOS memory. Cleaning is carried out after dry etching and wet etching of the ONO photoetching reworking, and a byproduct oxide layer and acid residues on the surface are removed, so that a better growth environment is provided for the subsequent ISSG growth blocking oxide layer, a film with uniform quality is grown, and the data retention capacity and the product reliability of the SONOS memory are effectively improved.

Drawings

Fig. 1 to 8 are schematic structural views showing steps in a method for optimizing uniformity of an ONO dielectric barrier oxide layer of a SONOS memory according to the present invention;

fig. 9 is a flowchart of a method for optimizing ONO gate dielectric blocking oxide uniformity in SONOS memory devices according to the present invention.

Detailed Description

Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.

Please refer to fig. 1 to 9. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.

The invention provides a method for optimizing the uniformity of an ONO grid dielectric barrier oxide layer of a SONOS memory, as shown in FIG. 9, FIG. 9 shows a flow chart of the method for optimizing the uniformity of the ONO grid dielectric barrier oxide layer of the SONOS memory, which at least comprises the following steps:

step one, a semiconductor structure, wherein the semiconductor structure comprises: a semiconductor substrate, wherein a SONOS region and a selection gate region are defined on the semiconductor substrate; the upper surface of the semiconductor structure is provided with a sacrificial oxide layer covering the selection gate region; a first oxide layer is arranged on the SONOS region and the sacrificial oxide layer, and an ONO layer is arranged on the oxide layer; photoresist is formed on the SONOS region; as shown in fig. 1, the semiconductor structure in the first step includes: a semiconductor substrate 200, wherein a SONOS region (SONOS) and a select gate region (SG) are defined on the semiconductor substrate 200; a sacrificial oxide layer 201 covering the selection gate region is arranged on the upper surface of the semiconductor structure; a first oxide layer a is disposed on the SONOS region and the sacrificial oxide layer 201, and an ONO layer 202 is disposed on the first oxide layer a; a Photoresist (PR) is formed on the SONOS region.

In a further aspect of the present invention, in the first step of the present embodiment, an STI region (STI) is further disposed on the semiconductor substrate at a side of the select gate region away from the SONOS, and a peripheral logic circuit region is further defined on the semiconductor substrate, and is not shown in fig. 1.

Further, the surface of the semiconductor structure in the first step of this embodiment is further formed with a polymer, which is not shown in fig. 1.

Step two, removing photoresist on the SONOS region, and exposing the ONO layer on the SONOS region; forming a second oxide layer on the ONO layer on the exposed SONOS region; as shown in fig. 2, the photoresist on the SONOS region is removed in the second step, and the ONO layer on the SONOS region is exposed; a second oxide layer 203 is then formed over the ONO layer over the exposed SONOS regions.

In the second step of this embodiment, the photoresist on the SONOS region is removed by dry etching and wet etching, and the polymer is removed at the same time.

Step three, removing the second oxide layer; as shown in fig. 3, this step three removes the second oxide layer 203.

Further, in the third step of the present embodiment, the second oxide layer 203 is removed by an acid solution, and the acid solution residue is removed.

The present invention further provides for removing the second oxide layer 203 using an HF solution in step three of the present embodiment.

Step four, photoresist is coated on the semiconductor structure, the selection gate region is opened after exposure and development, and the photoresist is reserved on the SONOS region; as shown in fig. 4, the fourth step is to coat the semiconductor structure with photoresist, expose and develop the select gate region and leave Photoresist (PR) on the SONOS region.

Further, in the fourth step of the present embodiment, the peripheral logic circuit region is opened at the same time as the selection gate region is opened after exposure and development.

And fifthly, etching to remove the ONO layer and the first oxide layer on the selection gate region, and forming the structure shown in figure 5.

In the fifth embodiment, the ONO layer and the first oxide layer on the select gate region are removed at the same time as the ONO layer and the first oxide layer on the peripheral logic circuit region are removed.

And step six, removing the exposed sacrificial oxide layer on the selection gate region to form the structure shown in fig. 6.

Further, the sacrificial oxide layer on the peripheral logic circuit region is removed in step six of the present embodiment.

In the sixth step of this embodiment, the sacrificial oxide layer is further removed by wet etching.

And step seven, removing the residual photoresist on the semiconductor structure to form the structure shown in fig. 7.

In the seventh step of the present embodiment, the photoresist remaining on the semiconductor structure is removed by wet etching or dry etching, and the polymer generated in the fifth to sixth steps is removed.

And step eight, forming a barrier oxide layer on the upper surface of the semiconductor structure. As shown in fig. 8, a barrier oxide layer 204 is formed on the upper surface of the semiconductor structure in this step eight.

Further, in the step eight of the present embodiment, the blocking oxide layer 204 is formed by the ISSG method.

The invention eliminates the by-product oxide layer and provides a better growth environment for ISSG growth blocking oxide layer; acid residues are removed, and photoresist damage is avoided; the barrier oxide layer has improved film quality, and can effectively prevent charge tunneling of silicon nitride, thereby improving device reliability and wafer yield.

In summary, the oxide layer and acid residue generated in the selection gate region during the ONO reworking process are removed by wet cleaning method for the SONOS memory, so as to improve the uniformity of the oxide layer blocking of the SONOS memory. Cleaning is carried out after dry etching and wet etching of the ONO photoetching reworking, and a byproduct oxide layer and acid residues on the surface are removed, so that a better growth environment is provided for the subsequent ISSG growth blocking oxide layer, a film with uniform quality is grown, and the data retention capacity and the product reliability of the SONOS memory are effectively improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims

1. A method for optimizing ONO gate dielectric barrier oxide uniformity in a SONOS memory comprising:

step three, removing the second oxide layer;

step seven, removing the residual photoresist on the semiconductor structure;

2. The method for optimizing ONO gate dielectric barrier oxide uniformity of a SONOS memory device of claim 1, wherein: and in the first step, an STI region is further arranged on the side, away from the SONOS, of the selective gate region on the semiconductor substrate, and a peripheral logic circuit region is further defined on the semiconductor substrate.

3. The method for optimizing ONO gate dielectric barrier oxide uniformity of a SONOS memory device of claim 1, wherein: the surface of the semiconductor structure in the first step is also formed with a polymer.

4. The method for optimizing ONO gate dielectric barrier oxide uniformity of a SONOS memory device of claim 3, wherein: and step two, removing the photoresist on the SONOS region through dry etching and wet etching, and simultaneously removing the polymer.

5. The method for optimizing ONO gate dielectric barrier oxide uniformity of a SONOS memory device of claim 1, wherein: and step three, removing the second oxide layer through an acid solution, and simultaneously removing the acid solution residue.

6. The method for optimizing ONO gate dielectric barrier oxide uniformity of a SONOS memory device of claim 1, wherein: and step three, removing the second oxide layer by using an HF solution.

7. The method for optimizing ONO gate dielectric barrier oxide uniformity of a SONOS memory device of claim 2, wherein: in the fourth step, the peripheral logic circuit region is opened at the same time as the selection gate region is opened after exposure and development.

8. The method for optimizing ONO gate dielectric barrier oxide uniformity of a SONOS memory device of claim 7, wherein: and step five, removing the ONO layer and the first oxide layer on the selection gate region, and simultaneously removing the ONO layer and the first oxide layer on the peripheral logic circuit region.

9. The method for optimizing ONO gate dielectric barrier oxide uniformity of a SONOS memory device of claim 8, wherein: the sacrificial oxide layer on the peripheral logic circuit region is also removed in step six.

10. The method for optimizing ONO gate dielectric barrier oxide uniformity in a SONOS memory according to claim 1 or 9, wherein: and step six, removing the sacrificial oxide layer through wet etching.

11. The method for optimizing ONO gate dielectric barrier oxide uniformity of a SONOS memory device of claim 1, wherein: and step seven, removing the polymer generated in the steps five to six while removing the residual photoresist on the semiconductor structure through wet etching or dry etching.

12. The method for optimizing ONO gate dielectric barrier oxide uniformity of a SONOS memory device of claim 1, wherein: and in the eighth step, the blocking oxide layer is formed by an ISSG method.