CN114999999A - Method for improving medium material residue in NAND flash air gap - Google Patents
Method for improving medium material residue in NAND flash air gap Download PDFInfo
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- CN114999999A CN114999999A CN202210702808.9A CN202210702808A CN114999999A CN 114999999 A CN114999999 A CN 114999999A CN 202210702808 A CN202210702808 A CN 202210702808A CN 114999999 A CN114999999 A CN 114999999A
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- word line
- air gap
- nand flash
- improving
- dielectric layer
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- 238000000034 method Methods 0.000 title claims abstract description 38
- 239000000463 material Substances 0.000 title claims description 12
- 239000003989 dielectric material Substances 0.000 claims abstract description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 15
- 230000002093 peripheral effect Effects 0.000 claims abstract description 14
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910021334 nickel silicide Inorganic materials 0.000 claims abstract description 10
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 claims abstract description 10
- 238000011049 filling Methods 0.000 claims abstract description 8
- 238000000137 annealing Methods 0.000 claims abstract description 5
- 230000004888 barrier function Effects 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims abstract description 5
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 5
- 238000004528 spin coating Methods 0.000 claims abstract description 4
- 239000004065 semiconductor Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 230000008569 process Effects 0.000 abstract description 10
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000007667 floating Methods 0.000 description 3
- 230000001808 coupling effect Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/764—Air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The invention provides a method for improving the residual of a dielectric material in an air gap of a NAND flash, wherein a unit area is provided with a plurality of word line structures which are arranged at intervals; filling a dielectric layer between the word line structures; covering an oxide layer on the fully filled dielectric layer and the top of the word line structure; spin-coating photoresist, exposing the unit area through exposure and development, covering the peripheral device area with the photoresist, taking the photoresist on the peripheral device area as a barrier layer, etching the unit area to remove the dielectric layer and the oxide layer on the upper half part of the word line structure, and exposing the upper half part of the word line structure; covering a layer of nickel on the exposed word line structure, and then carrying out annealing treatment to form the exposed word line structure into nickel silicide; and removing the residual dielectric layer between the word line structures. According to the method for improving the dielectric material residue in the air gap of the NANDflash, the SiN removing process is moved to the position after the nickel silicide, so that the influence caused by the high aspect ratio can be removed, and the final residue is avoided.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for improving medium material residue in an NAND flash air gap.
Background
NAND flash is an important flash memory device, and because the structure has a very high cell density, a high storage density can be achieved, and the writing and erasing speeds are very high, the NAND flash is widely applied to various memory cards, and is gradually replacing solid state disks of mechanical hard disks.
As device dimensions shrink, the word line pitch of the NAND device block area also decreases, which causes serious inter-cell coupling interference problems in the floating gate type memory, thereby affecting the size of the cell threshold voltage, and the programming and reading speed of the memory array. To solve this problem, a process of air gap (Airgap) isolation technology is introduced into the fabrication of NAND flash, and the capacitive coupling effect between the word lines and the floating gates of the device is improved by introducing the substance with the lowest dielectric constant, i.e., air (Airgap), between the floating gates.
In the airgap formation process, the distance and the topography of the word lines from one pitch to the next is affected. In order to ensure the protection of the word line, the condition of high selection ratio of SiN is adopted, but after the SiN removal process, a high aspect ratio (more than 10) exists between the word line WL and the word line WL, and the high aspect ratio easily causes NiPt residues in the subsequent nickel silicide forming process. The presence of the residue can cause capacitive coupling effects in the final device at the corresponding location, as well as leakage between the word lines WL and WL.
Disclosure of Invention
In view of the above-mentioned shortcomings in the prior art, the present invention provides a method for improving the material residue in NAND flash air gap, which is used to solve the problem of material residue in NAND flash air gap in the prior art.
To achieve the above and other related objects, the present invention provides a method for improving dielectric material residue in an air gap of a NAND flash, comprising the steps of:
providing a semiconductor structure, wherein the semiconductor structure comprises a substrate, a unit area and a peripheral device area are arranged on the substrate, and the unit area is provided with a plurality of word line structures which are arranged at intervals; filling a dielectric layer between the word line structures; then covering an oxide layer on the fully filled dielectric layer and the top of the word line;
step two, spin-coating photoresist on the semiconductor structure, exposing the unit area through exposure and development, covering the peripheral device area with the photoresist, taking the photoresist on the peripheral device area as a barrier layer, etching the unit area to remove the dielectric layer and the oxide layer on the upper half part of the word line structure, and exposing the upper half part of the word line structure;
step three, covering a layer of nickel on the exposed word line structure, and then carrying out annealing treatment to form the exposed word line structure into nickel silicide;
and step four, removing the residual dielectric layer between the word line structures.
Preferably, the material of the dielectric layer in the first step is SiN.
Preferably, the method for filling the dielectric layer in the first step is a deposition method.
Preferably, the thickness of the dielectric layer filled in the first step is 50 angstroms.
Preferably, the thickness of the oxide layer in the first step is 100 angstroms.
Preferably, a side wall is arranged on the side wall of the word line structure in the first step.
Preferably, the material of the sidewall in the first step is an oxide layer.
Preferably, in the first step, the plurality of word line structures are arranged at intervals along the bit line direction.
Preferably, the material of the word line structure in the first step includes polysilicon.
Preferably, the dielectric layer is removed in the fourth step, and NiPt residues between the word line structures are removed at the same time.
As described above, the method for improving the dielectric material residue in the air gap of the NAND flash according to the present invention has the following advantages: according to the method for improving the dielectric material residue in the NAND flash air gap, the SiN removing process is moved to the position after nickel silicide, so that the influence caused by the high aspect ratio can be removed, and the final residue is avoided.
Drawings
FIGS. 1 to 4 are schematic structural diagrams illustrating processes of the method for improving the dielectric material residue in the NAND flash air gap according to the present invention;
FIG. 5 is a flow chart of a method for improving dielectric material residue in an air gap of a NAND flash according to the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 5. It should be noted that the drawings provided in this embodiment are only for schematically illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings and not drawn according to the number, shape and size of the components in actual implementation, and the form, quantity and proportion of each component in actual implementation may be arbitrarily changed, and the component layout may be more complicated.
The present invention provides a method for improving the residue of a dielectric material in a NAND flash air gap, as shown in fig. 5, fig. 5 is a flowchart of the method for improving the residue of a dielectric material in a NAND flash air gap according to the present invention, and the method at least comprises the following steps:
providing a semiconductor structure, wherein the semiconductor structure comprises a substrate, a unit area and a peripheral device area are arranged on the substrate, and the unit area is provided with a plurality of word line structures which are arranged at intervals; filling a dielectric layer between the word line structures; then covering an oxide layer on the fully filled dielectric layer and the top of the word line;
further, in the present invention, in the first step of this embodiment, the dielectric layer is made of SiN. Furthermore, the method for filling the dielectric layer in the first step is a deposition method. Still further, the thickness of the dielectric layer filled in the first step of this embodiment is 50 angstroms.
Further, the thickness of the oxide layer in the first step of this embodiment is 100 angstroms.
Further, as shown in fig. 4, a sidewall 05 is disposed on a sidewall of the word line structure in the first step of this embodiment. Further, in the present invention, in the first step of this embodiment, the material of the sidewall is an oxide layer.
Further, in the first step of this embodiment, the plurality of word line structures are arranged at intervals along the bit line direction. Further, the material of the word line structure in the first step of this embodiment includes polysilicon.
As shown in fig. 1, in the first step of this embodiment, the semiconductor structure includes a substrate, a cell region and a peripheral device region are disposed on the substrate, and the cell region is provided with a plurality of word line structures 01 arranged at intervals; in this embodiment, the plurality of word line structures 01 are arranged at intervals along the bit line direction. Filling a dielectric layer 02 between the word line structures; and then covering an oxide layer 03 on the fully filled dielectric layer 02 and the top of the word line structure 01.
Step two, spin-coating photoresist on the semiconductor structure, exposing the unit area through exposure and development, covering the peripheral device area with the photoresist, taking the photoresist on the peripheral device area as a barrier layer, etching the unit area to remove the dielectric layer and the oxide layer on the upper half part of the word line structure, and exposing the upper half part of the word line structure; as shown in fig. 2, a photoresist is spin-coated on the semiconductor structure, and then the cell region is exposed through exposure and development, the peripheral device region is still covered by the photoresist, the photoresist on the peripheral device region is used as a barrier layer, the cell region is etched to remove the dielectric layer 02 and the oxide layer on the upper half portion of the word line structure 01, and the upper half portion of the word line structure 01 is exposed. Further, in the second step of this embodiment, the dielectric layer and the oxide layer are removed in the unit region by etching, and simultaneously, the sidewall of the upper half sidewall of the word line structure is also removed, so as to form the structure shown in fig. 2.
Step three, covering a layer of nickel on the exposed word line structure, and then carrying out annealing treatment to form the exposed word line structure into nickel silicide; as shown in fig. 3, in the third step, a layer of nickel is covered on the exposed word line structure, and then an annealing process is performed, so that the exposed word line structure is formed as nickel silicide 04.
And step four, removing the residual dielectric layer between the word line structures. As shown in fig. 4, in this step four, after removing the residual dielectric layer 02 between the word line structures, the structure shown in fig. 4 is formed.
Further, in the fourth step of this embodiment, the dielectric layer is removed and at the same time the NiPt residues between the word line structures are removed. The NiPt residue is a residue formed during the formation of nickel silicide in step three.
In summary, the method for improving the dielectric material residue in the NAND flash air gap of the present invention can remove the influence of the aspect ratio by moving the SiN removal process to the nickel silicide process, thereby avoiding the final formation of residue. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A method for improving dielectric material residue in an air gap of a NAND flash, comprising the steps of:
providing a semiconductor structure, wherein the semiconductor structure comprises a substrate, a unit area and a peripheral device area are arranged on the substrate, and the unit area is provided with a plurality of word line structures which are arranged at intervals; filling a dielectric layer between the word line structures; then covering an oxide layer on the fully filled dielectric layer and the top of the word line structure;
step two, spin-coating photoresist on the semiconductor structure, exposing the unit area through exposure and development, covering the peripheral device area with the photoresist, taking the photoresist on the peripheral device area as a barrier layer, etching the unit area to remove the dielectric layer and the oxide layer on the upper half part of the word line structure, and exposing the upper half part of the word line structure;
step three, covering a layer of nickel on the exposed word line structure, and then carrying out annealing treatment to form the exposed word line structure into nickel silicide;
and step four, removing the residual dielectric layer between the word line structures.
2. The method of claim 1, wherein the step of improving the dielectric material residue in the NAND flash air gap comprises: the dielectric layer in the first step is made of SiN.
3. The method of claim 1, wherein the step of improving the dielectric material residue in the NAND flash air gap comprises: and the method for filling the dielectric layer in the first step is a deposition method.
4. The method of claim 1, wherein the step of improving the dielectric material residue in the NAND flash air gap comprises: the thickness of the dielectric layer filled in the first step is 50 angstroms.
5. The method of claim 1, wherein the step of improving the dielectric material residue in the NAND flash air gap comprises: the thickness of the oxide layer in the first step is 100 angstroms.
6. The method of claim 1, wherein the step of improving the residue of the dielectric material in the air gap of the NAND flash memory further comprises: and a side wall is arranged on the side wall of the word line structure in the first step.
7. The method of claim 6, wherein the step of improving the dielectric material residue in the NAND flash air gap comprises: and the material of the side wall in the first step is an oxide layer.
8. The method of claim 1, wherein the step of improving the dielectric material residue in the NAND flash air gap comprises: in the first step, the plurality of word line structures are arranged at intervals along the bit line direction.
9. The method of claim 1, wherein the step of improving the dielectric material residue in the NAND flash air gap comprises: the material of the word line structure in the first step comprises polysilicon.
10. The method of claim 1, wherein the step of improving the dielectric material residue in the NAND flash air gap comprises: and removing the dielectric layer and NiPt residues between the word line structures in the fourth step.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210702808.9A CN114999999A (en) | 2022-06-21 | 2022-06-21 | Method for improving medium material residue in NAND flash air gap |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210702808.9A CN114999999A (en) | 2022-06-21 | 2022-06-21 | Method for improving medium material residue in NAND flash air gap |
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| Publication Number | Publication Date |
|---|---|
| CN114999999A true CN114999999A (en) | 2022-09-02 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210702808.9A Pending CN114999999A (en) | 2022-06-21 | 2022-06-21 | Method for improving medium material residue in NAND flash air gap |
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| CN (1) | CN114999999A (en) |
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- 2022-06-21 CN CN202210702808.9A patent/CN114999999A/en active Pending
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