CN102956553A - Split gate flash memory embedded in logical circuit and method for manufacturing memory set - Google Patents
Split gate flash memory embedded in logical circuit and method for manufacturing memory set Download PDFInfo
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- CN102956553A CN102956553A CN2011102477666A CN201110247766A CN102956553A CN 102956553 A CN102956553 A CN 102956553A CN 2011102477666 A CN2011102477666 A CN 2011102477666A CN 201110247766 A CN201110247766 A CN 201110247766A CN 102956553 A CN102956553 A CN 102956553A
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Abstract
The invention provides a method for manufacturing a split gate flash memory embedded in a logical circuit. Compared with a method for forming a single split gate flash memory, the method for manufacturing the split gate flash memory embedded in the logical circuit includes the steps of precipitating polycrystalline silicon once, precipitating silicon oxide once, etching twice, and covering with fluid material once. The invention further provides a method for manufacturing a split gate flash memory set embedded in the logical circuit. According to the technical scheme of the method, the split gate flash memory, a high voltage transistor and a logic transistor can be manufactured on one integrated circuit. The split gate flash memory, the high voltage transistor and the logic transistor manufactured by the method are high in density, integration degree and running speed, and meanwhile, integrated chips are smaller, thus cost for each integrated chip is lowered, and application range is wider. In addition, during the manufacturing of the split gate flash memory, gates of the high voltage transistor and the logic transistor are not subjected to etching, so that the high voltage transistor and the logic transistor have fewer defects, and requirements on gate quality can be met.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of manufacture method that embeds the separated grid electrode type quick flashing storage of logical circuit and embed the separated grid electrode type quick flashing storage group of logical circuit.
Background technology
Random asccess memory, in use there are the problem of the loss of data of storing after the power down in for example DRAM and SRAM.In order to overcome this problem, people have designed and have developed multiple nonvolatile memory.Recently, based on the flash memory of floating boom concept because it has little cell size and good service behaviour has become the most general nonvolatile memory.Nonvolatile memory mainly comprises two kinds of basic structures: piled grids (stack gate) structure and separate grid type (split gate) structure.The stacked gate architectures memory comprises the control gate polysilicon layer (ploy 2) of the floating grid polysilicon layer (ploy 1) of satisfying punchthrough oxide layer, store electrons, oxide/nitride/oxide (oxide-nitride-oxide, ONO) lamination and control Electronic saving and the release that sequentially are formed on the substrate.The separate grid type structure memory also comprises then punchthrough oxide layer, the floating grid polysilicon layer (ploy 1) of store electrons, the oxide/nitride/oxide (oxide-nitride-oxide that is formed on the substrate, ONO) the control gate polysilicon layer (ploy 2) of lamination and control Electronic saving and release, but different from the stacked gate architectures memory is that the separate grid type structure also forms as wiping grid (erase gate) polysilicon layer (ploy 3) in a side of stacked gate architectures.On storage and wiping/writing performance, the separate grid type structure memory is avoided the excessive erasable problem of stacked gate architectures memory.
Writing to separated grid electrode type quick flashing storage and/or during obliterated data, usually use the high voltage with respect to power source voltage Vcc, source-drain area forms the hot carrier passage, and electronic carrier then passes the oxide layer injection floating boom of isolated floating boom and source-drain area or extracts out from floating boom.
Usually, can there be peripheral circuit (Periphery Circuit) on every side in separated grid electrode type quick flashing storage for realizing certain function, is mainly logical circuit, comprising: high voltage transistor and logic transistor.The control grid of separated grid electrode type quick flashing storage is electrically connected to the word line, and the source/drain region of separated grid electrode type quick flashing storage is electrically connected to bit line.This word line is electrically connected to row decoder and bit line is electrically connected to read/write circuit.Row decoder is used for selecting in the multi-word-line one and apply word line voltage to selected word line.This word line voltage is to be applied to the voltage that the word line is used for carrying out reading and writing and/or erase operation.Read/write circuit is used for selecting in the multiple bit lines one and apply bit-line voltage to selected bit line.This bit-line voltage is to be applied to bit line be used for to carry out and to write, to wipe and/or the voltage of read operation.In addition, read/write circuit also is electrically connected to selected word line and selected bit line, can be by the data of selected bit line output memory cell.This row decoder typically comprises at least one high voltage transistor, and it is configured to the voltage of control word line, and read/write circuit typically comprises at least one high voltage transistor, and it is configured to control the voltage of bit line.Therefore, the breakdown characteristics of high voltage transistor should have and can bear this word line voltage and bit-line voltage.
If separated grid electrode type quick flashing storage, high voltage transistor, logic transistor all are made on the discrete integrated chip, the speed of service of whole memory can be subject to the signal limit on transmission bandwidth between flash memory and peripheral circuit.At present, the integrated circuit that separated grid electrode type quick flashing storage is embedded high voltage transistor is arranged also in the prior art, the integrated circuit that separated grid electrode type quick flashing storage is embedded logic transistor is also arranged.Ripe gradually in the separated grid electrode type quick flashing storage technology that embeds logical circuit, in the evolution that storage speed is constantly accelerated, cost descends gradually, people begin its manufacture method has been proposed Secretary.
Described Secretary comprises: the separated grid electrode type quick flashing storage way that a kind of new embedding logical circuit need to be provided, so that the density of separated grid electrode type quick flashing storage, high voltage transistor, logic transistor increases, integrated degree is high, the speed of service is faster, integrated chip is less simultaneously, thereby reduced the cost of each integrated chip, and used more extensive.
Summary of the invention
The purpose that the present invention realizes provides a kind of manufacture method of separated grid electrode type quick flashing storage of new embedding logical circuit, so that the density of separated grid electrode type quick flashing storage, high voltage transistor, logic transistor increases, integrated degree is high, the speed of service is faster, integrated chip is less simultaneously, thereby reduced the cost of each integrated chip, and used more extensive.
For achieving the above object, the invention provides a kind of manufacture method that embeds the separated grid electrode type quick flashing storage of logical circuit, described manufacture method comprises:
Semiconductor base is provided, and described semiconductor base comprises Three regions: in order to form the first area of separated grid electrode type quick flashing storage, in order to form the second area of high voltage transistor, be used to form the 3rd zone of logic transistor;
Form the first insulating barrier at described semiconductor base;
Form successively floating grid, the second insulating barrier, control grid, hard mask layer on the first insulating barrier of first area, described floating grid, the second insulating barrier, control grid, hard mask layer side cover side wall;
Deposit the first polysilicon layer on first insulating barrier in second area and the 3rd zone and first area, described the first polysilicon layer thickness is logic transistor grid desired thickness;
Silicon oxide deposition layer on the first polysilicon layer, described silicon oxide layer thickness is less than logic transistor grid desired thickness;
Keep the silicon oxide layer on the 3rd zone, get rid of the silicon oxide layer of first area and second area;
Deposit the second polysilicon layer on described the first polysilicon layer and silicon oxide layer, described the second polysilicon layer thickness are the difference of high-pressure crystal tube grid desired thickness and logic transistor grid desired thickness;
Form fluid material layer at described the second polysilicon layer;
Adopt the second polysilicon layer of photoresist protection second area and second polysilicon layer in the 3rd zone, utilize dry etching to exposing hard mask layer;
Remove photoetching glue residue and fluent material residue;
Hard mask layer on the employing photoresist protection first area and the second polysilicon layer of the second polysilicon layer and second area utilize dry etching to the silicon oxide layer that exposes the 3rd zone;
Remove the silicon oxide layer in photoetching glue residue and the 3rd zone;
Etching forms required grid and the required grid of logic transistor of word wiregrating, high voltage transistor of separated grid electrode type quick flashing storage.
Alternatively, described fluid material layer is the organic bottom antireflective material.
Alternatively, utilize dry etching to exposing in the hard mask layer step, the etching gas that described dry etching adopts is fluid materials with the etching polysilicon ratio is 5: 4 etching gas.
Alternatively, the main etching gas of described etching gas is: Cl
2, HBr, SF
6, CF
4, CHF
3, CH
2F
2In at least two kinds, auxiliary etch gas is Ar, O
2In at least a.
The present invention also provides a kind of manufacture method that embeds the separated grid electrode type quick flashing storage group of logical circuit, the separated grid electrode type quick flashing storage group of described embedding logical circuit comprises the separated grid electrode type quick flashing storage of the embedding logical circuit that contains a pair of same size, and described manufacture method comprises:
Semiconductor base is provided, described semiconductor base comprises six zones: in order to first area and the 4th zone that forms respectively a separated grid electrode type quick flashing storage, in order to second area and the 5th zone that forms respectively a high voltage transistor, be used for forming respectively the 3rd zone and the 6th zone of a logic transistor; Described first area is adjacent with the 4th zone;
Form the first insulating barrier at described semiconductor base;
Respectively form floating grid, the second insulating barrier, control grid, the hard mask layer of a pair of successively stack on first area and four-range the first insulating barrier, described floating grid, the second insulating barrier, control grid, hard mask layer side cover side wall;
Deposit the first polysilicon layer on second area and the 3rd zone and the 5th zone and first insulating barrier in the 6th zone and first area and the 4th zone, described the first polysilicon layer thickness is logic transistor grid desired thickness;
Silicon oxide deposition layer on the first polysilicon layer, described silicon oxide layer thickness is less than logic transistor grid desired thickness;
Keep the silicon oxide layer on the 3rd zone and the 6th zone, get rid of the silicon oxide layer in first area and second area and the 4th zone and the 5th zone;
Deposit the second polysilicon layer on described the first polysilicon layer and silicon oxide layer, described the second polysilicon layer thickness are the difference of high-pressure crystal tube grid desired thickness and logic transistor grid desired thickness;
Form fluent material at the second polysilicon layer, the thickness of the fluent material of the lowest part of the second polysilicon layer between the floating grid of adjacent successively stack, the second insulating barrier, control grid, hard mask layer is not less than the floating grid of described successively stack, the second insulating barrier, control grid, the height sum of hard mask layer and the difference of the first polysilicon layer and the second polysilicon layer thickness sum;
Adopt second polysilicon layer in photoresist protection second area and the 5th zone and second polysilicon layer in the 3rd zone and the 6th zone, utilize dry etching to exposing hard mask layer;
Remove photoetching glue residue and fluent material residue;
Hard mask layer on employing photoresist protection first area and the 4th zone and second polysilicon layer in the second polysilicon layer and second area and the 5th zone utilize dry etching to exposing the silicon oxide layer of the 3rd zone with the 6th zone;
Remove the silicon oxide layer in photoetching glue residue and the 3rd zone and the 6th zone;
Etching forms required grid and the required grid of logic transistor of word wiregrating, high voltage transistor of separated grid electrode type quick flashing storage.
Alternatively, described fluid material layer is the organic bottom antireflective material.
Alternatively, utilize dry etching to exposing in the hard mask layer step, the etching gas that described dry etching adopts is fluid materials with the etching polysilicon ratio is 5: 4 etching gas.
Alternatively, the main etching gas of described etching gas is: Cl
2, HBr, SF
6, CF
4, CHF
3, CH
2F
2In at least two kinds, auxiliary etch gas is Ar, O
2In at least a.
Compared with prior art, the present invention has the following advantages:
Adopt the separated grid electrode type quick flashing storage of the embedding logical circuit that way provided by the invention completes, separated grid electrode type quick flashing storage is embedded in the peripheral circuit of high voltage transistor and logic transistor, can make separated grid electrode type quick flashing storage, high voltage transistor, logic transistor at an integrated circuit, only need carry out a polysilicon deposit, once oxidation silicon deposit, second etch, a fluent material covering five steps than independent making separated grid electrode type quick flashing storage more; So that the density of the separated grid electrode type quick flashing storage that forms, high voltage transistor, logic transistor increases, the speed of service is faster, and integrated chip is less, thereby has reduced the cost of each integrated chip simultaneously.
The present invention has adopted the characteristics of the good fluidity of fluent material, can filling groove, and especially dark groove is avoided in etching process, etches into the zone that needs protection.
In addition, because the performance of described high voltage transistor and logic transistor is very responsive to the formation quality condition of grid, in the separated grid electrode type quick flashing storage forming process of above-mentioned embedding logical circuit, the grid of high voltage transistor and logic transistor does not pass through etching processing, therefore defective is few, can satisfy both to the requirement of gate quality.
Description of drawings
Fig. 1 is the manufacture method schematic flow sheet of the separated grid electrode type quick flashing storage of embedding logical circuit provided by the invention;
Fig. 2-Figure 14 is the structural representation that the manufacture method intermediate steps of the separated grid electrode type quick flashing storage of the embedding logical circuit that provides of embodiment one forms;
Figure 15 is the separated grid electrode type quick flashing storage structural representation of the final embedding logical circuit that forms of the manufacture method that provides of embodiment one;
Figure 16 is the manufacture method schematic flow sheet of the separated grid electrode type quick flashing storage group of the embedding logical circuit that provides of the embodiment of the invention two;
Figure 17-Figure 29 is the structural representation that the manufacture method intermediate steps of the separated grid electrode type quick flashing storage group of the embedding logical circuit that provides of embodiment two forms;
Figure 30 is the separated grid electrode type quick flashing storage group structural representation of the final embedding logical circuit that forms of the manufacture method that provides of embodiment two;
Figure 31 adopts the BARC material to form the yields test result figure of independent separated grid electrode type quick flashing storage.
Embodiment
Be illustrated in figure 1 as the manufacture method flow chart of the separated grid electrode type quick flashing storage of embedding logical circuit provided by the invention.Particularly, execution in step S11 provides semiconductor base, and semiconductor base is divided into Three regions, be respectively: in order to form the first area of separated grid electrode type quick flashing storage, in order to form the second area of high voltage transistor, be used to form the 3rd zone of logic transistor.
Execution in step S12 forms the first insulating barrier at described semiconductor base, in order to the floating grid of isolated separated grid electrode type quick flashing storage, the grid of high voltage transistor, grid and the semiconductor base of logic transistor.
Execution in step S13, the first insulating barrier in the first area form floating grid, the second insulating barrier, control grid, the hard mask layer of a pair of successively stack, and described floating grid, the second insulating barrier, control grid, hard mask layer side cover side wall.
Execution in step S14, then deposit the first polysilicon layer (ploy 1) on first insulating barrier in second area and the 3rd zone and first area, described the first polysilicon layer thickness is the logic transistor gate, and this step has formed the required thickness of logic transistor grid.
Execution in step S15, silicon oxide deposition layer on the first polysilicon layer (oxide 1), described silicon oxide layer thickness is less than the logic transistor gate.
Execution in step S16, get rid of the silicon oxide layer (etch 1) except (that is: first polysilicon layer in the 3rd zone) on the logic transistor grid, this step removes for wet method, because logic transistor is low voltage transistor, required gate is less than high voltage transistor gate, therefore before next step forms the gate of high voltage transistor, fill silicon oxide layer at the area of grid of logic transistor, sneak into the area of grid of logic transistor to avoid follow-up polysilicon layer.
Execution in step S17, deposit the second polysilicon layer (ploy 2) on described the first polysilicon layer and silicon oxide layer, described the second polysilicon layer thickness is the difference of high-pressure crystal tube grid desired thickness and logic transistor grid desired thickness, and this step forms the gate of high voltage transistor.
Execution in step S18 forms fluid material layer (fluid 1) at described the second polysilicon layer, and the good fluidity of described fluid material layer can be filled dark groove.
After above-mentioned steps is finished, the thickness sum of the first polysilicon layer on the hard mask layer of described first area, the second polysilicon layer, fluid material layer greater than with the grid of logic transistor on silicon oxide layer, the second polysilicon layer, the thickness sum of fluid material layer, and the latter is greater than the fluent material layer thickness on the high-pressure crystal tube grid.
The grinding agent that produces for fear of cmp is blocked in the clean problem of cleaning in the groove, and the present invention has adopted dry etching.Execution in step S19, adopt the area of grid of photoresist protection high voltage transistor and the area of grid (that is: second polysilicon layer in second area and the 3rd zone) of logic transistor, utilize dry etching to the hard mask layer that exposes the first area (etch 2); So-called dry etching, i.e. downwards " eating up " first polysilicon layer, the second polysilicon layer, fluid material layer expose the hard mask layer of first area.As noted earlier; the thickness sum of the first polysilicon layer on the hard mask layer of first area, the second polysilicon layer, fluid material layer is greater than the thickness sum of the silicon oxide layer on volume transistorized grid, the second polysilicon layer, fluid material layer; and the latter is greater than the fluent material layer thickness on the high-pressure crystal tube grid; therefore; in the process of downward " eating "; for " not eating up " gate height of high voltage transistor, need protect the area of grid of high voltage transistor.
Execution in step S20, photoetching glue residue and the fluent material residue of the area of grid of removal high voltage transistor and the area of grid (that is: second area and the 3rd zone) of logic transistor.
Owing to also being coated with the second polysilicon layer on the grid of logic transistor at this moment; logic transistor will define the position of its grid; need execution in step S21 this moment; adopt area of grid (that is: second area) and the first area of photoresist protection high voltage transistor, utilize dry etching to the silicon oxide layer (etch 3) of the area of grid that exposes logic transistor (that is: the 3rd zone).
Follow execution in step S22, remove the silicon oxide layer of the area of grid (that is: the 3rd zone) of photoetching glue residue and logic transistor.
Execution in step S23, etching forms required grid and the required grid (etch 4) of logic transistor of word wiregrating, high voltage transistor of separated grid electrode type quick flashing storage, and this step is dry etching.The separated grid electrode type quick flashing storage of the embedding logical circuit that above-mentioned steps completes, separated grid electrode type quick flashing storage is embedded in the peripheral circuit of high voltage transistor and logic transistor, can makes separated grid electrode type quick flashing storage, high voltage transistor, logic transistor at an integrated circuit; This is so that the density of separated grid electrode type quick flashing storage, high voltage transistor, logic transistor increases, and the speed of service is faster, and integrated chip is less simultaneously, thereby has reduced the cost of each integrated chip.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail, owing to focus on illustrating manufacture method provided by the invention, thereby the size of device not drawing to scale.
The first embodiment
With reference to flow process shown in Figure 1, specifically introduce the manufacture method of the separated grid electrode type quick flashing storage of the embedding logical circuit that the specific embodiment of the invention provides, the separated grid electrode type quick flashing storage of described embedding logical circuit comprises Three regions, the first area is separated grid electrode type quick flashing storage, second area is high voltage transistor, and the 3rd zone is logic transistor.Need to prove, the 3rd zone at the second area at high voltage transistor place and logic transistor place all is to be positioned at peripheral circuit region in true layout, therefore, high voltage transistor and logic transistor position relationship are not subjected to the restriction of the figure that the present embodiment one provides.
Execution in step S11 at first, semiconductor base 11 is provided, structural section figure as shown in Figure 2, semiconductor base 11 is divided into Three regions, be respectively: in order to form the first area I of separated grid electrode type quick flashing storage, in order to form the second area II of high voltage transistor, be used to form the 3rd regional III of logic transistor.
Follow execution in step S12, form the first insulating barrier 12 at described semiconductor base 11, in order to the floating grid of isolated separated grid electrode type quick flashing storage, the grid of high voltage transistor, grid and the source in the substrate 11/drain electrode or other device of logic transistor, structural section figure as shown in Figure 3.The material of described the first insulating barrier 12 is silica, and the formation method can be chemical vapor deposition (CVD) or thermal oxidation method.
Then execution in step S13 forms a pair of floating grid 101, the second insulating barrier 102, control grid 103 and hard mask layer 107 successively on the first insulating barrier 12 of first area I, and structural section figure as shown in Figure 4.The second insulating barrier 102 can be oxide 1021, nitride 1022, oxide 1,023 three layers ONO sandwich structure altogether, the art personnel should be understood that, the second insulating barrier 102 also can be the insulation systems such as one deck nitride or one deck oxide, or one deck nitride one deck oxide.Floating grid 101, the second insulating barrier 102, control grid 103 and hard mask layer 107 sides have been formed with the side wall 106 of insulating effect.
Follow execution in step S14, deposit the first polysilicon layer 13 on the first insulating barrier 12 of first area I and second area II and the 3rd regional III, structural section figure is as shown in Figure 5.The thickness of described the first polysilicon layer 13 just is the gate of logic transistor, and this step has formed the required thickness of logic transistor grid.This step can adopt chemical vapor deposition.This step is called for short ground floor polysilicon deposit (poly1).
Then execution in step S15, silicon oxide deposition layer 14 on the first polysilicon layer 13, structural section figure is as shown in Figure 6.Described silicon oxide layer 14 thickness are less than the required gate of logic transistor, i.e. the thickness of the first polysilicon layer 13, and described silicon oxide layer 14 is sacrifice layer.This step can adopt chemical vapor deposition.This step is called for short silicon oxide deposition (oxide 1).
Execution in step S16 gets rid of except the silicon oxide layer 14 on the logic transistor grid, structural section figure as shown in Figure 7, this step removes for wet method, for example adopts HF sour.Because logic transistor is low voltage transistor, required gate is less than high voltage transistor gate, therefore before next step forms the gate of high voltage transistor, fills silicon oxide layer 14 at the area of grid of logic transistor.This step is called for short for the first time etching (etch 1).
Follow execution in step S17, deposit the second polysilicon layer 15 on described the first polysilicon layer 13 and silicon oxide layer 14, structural section figure is as shown in Figure 8.Described the second polysilicon layer 15 thickness are the difference of high-pressure crystal tube grid desired thickness and logic transistor grid desired thickness, and this step forms the gate of high voltage transistor.This step can adopt chemical vapor deposition.This step is called for short second layer polysilicon deposit (poly2).
Then execution in step S18 forms fluid material layer 16 at described the second polysilicon layer 15, and structural section figure as shown in Figure 9.The good fluidity of described fluid material layer 16 can be filled dark groove; Described fluent material can be organic bottom antireflective material (Organic BARC).Fluid material layer 16 can adopt spin coating method to form.In the first embodiment, owing to separated grid electrode type quick flashing storage, high voltage transistor, logic transistor three close together, thereby in deposit the first polysilicon layer 13, the second polysilicon layers 15 processes, generally can not form significantly dark groove.Fluid material layer 16 is substantially impartial at the regional upper surface thickness of the second polysilicon layer 15.This step is called for short fluid layer and forms (fluid 1).
After above-mentioned steps is finished, the thickness sum of the first polysilicon layer 13 on the hard mask layer 107 of described first area I, the second polysilicon layer 15, fluid material layer 16 is greater than the thickness sum of the silicon oxide layer 14 on the grid of logic transistor, the second polysilicon layer 15, fluid material layer 16, and greater than fluid material layer 16 thickness on the high-pressure crystal tube grid.
The grinding agent that produces for fear of cmp is blocked in the problem that can't remove in the narrow groove, the present invention has adopted and has avoided, particularly, execution in step S19, adopt the area of grid of photoresist 17 protection high voltage transistors and the area of grid of logic transistor, as shown in figure 10, utilize dry etching to the hard mask layer 107 that exposes first area I; So-called dry etching, i.e. downwards " eating up " first polysilicon layer 13, the second polysilicon layer 15, fluid material layer 16 expose the hard mask layer 107 of first area I.As noted earlier; the first polysilicon layer 13 on the hard mask layer 107 of first area I; the second polysilicon layer 15; the thickness sum of fluid material layer 16 is greater than the silicon oxide layer 14 on the grid of logic transistor; the second polysilicon layer 15; the thickness sum of fluid material layer 16; and greater than fluid material layer 16 thickness on the high-pressure crystal tube grid; therefore; in the process of downward " eating "; for " not eating up " gate height of logic transistor and the gate height of high voltage transistor, need protect the area of grid of high voltage transistor and the area of grid of logic transistor.In specific implementation process, remove fully for guaranteeing the conductive material on the hard mask layer 107, generally expose answer mask layer 107 after, also carry out hard mask layer 107 is carried out overetch, when the amount of described photoresist 17 also will guarantee to expose hard mask layer 107, the area of grid of high voltage transistor was not etched to.This step is called for short for the second time etching (etch 2).
In the dry etching process, not only to " eat up " fluent material, also to " eat up " the first polysilicon layer 13 and the second polysilicon layer 15, in order to be easy to control the thickness of fluid material layer, so being fluid materials, compares preferably near identical with etching polysilicon the etching gas that described dry etching adopts, but the etch rate of fluid materials is slightly higher than the etch rate to polysilicon, in the present embodiment, is 5: 4 to the etch rate of BARC material with etch rate to polysilicon.For example, the main etching gas of described etching gas is: Cl
2, HBr, SF
6, CF
4, CHF
3, CH
2F
2In at least two kinds, auxiliary etch gas is Ar, O
2In at least a.
Follow execution in step S20, photoetching glue residue and the fluent material residue of the area of grid of removal high voltage transistor and the area of grid of logic transistor.In the present embodiment one, fluent material is the organic BARC material, therefore remove photoetching glue residue and organic BARC material residue and can select standard degumming process of the prior art and remove BARC technique, can adopt afterwards washed with de-ionized water to remove, obtain structural representation as shown in figure 11.Need to prove, if fluent material adopts non-BARC material, then can adopt corresponding material removal method.Obtained the erase gate 104 in order to form separated grid electrode type quick flashing storage this moment, described erase gate 104 is between a pair of floating grid 101, the second insulating barrier 102, control grid 103 and the hard mask layer 107 of successively stack.Because the erase gate 104 final metal interconnecting layers (not shown) that pass through are electrically connected with peripheral circuit, the metal interconnecting layer that extended meeting formation links to each other with the external world behind control grid 103 tops, for the metal interconnecting wires and 103 conductings of control grid that prevents that erase gate 104 is electrically connected, so the thickness of erase gate 104 is less than the thickness sum of floating grid 101, the second insulating barrier 102, control grid 103 and hard mask layer 107 4.
Owing to also being coated with the second polysilicon layer 15 on the grid of logic transistor at this moment; logic transistor will define the position of its grid; therefore need then execution in step S21; adopt the area of grid of photoresist 19 protection first area I and high voltage transistor; structural section figure utilizes dry etching to the silicon oxide layer 14 of the area of grid that exposes logic transistor as shown in figure 12.Described protection first area I refers to protect whole separated grid electrode type quick flashing storage zone to be formed, reaches the polysilicon on both sides between the side wall 106 of the present embodiment one middle finger floating grid 101, the second insulating barrier 102, control grid 103, hard mask layer 107, above-mentioned each layer side, side wall.This step is called for short for the third time etching (etch 3).
Follow execution in step S22, remove the silicon oxide layer 14 of the area of grid of photoetching glue residue and logic transistor, obtain structural representation as shown in figure 13.Described silicon oxide layer 14 is removed and is adopted HF acid.Described photoetching glue residue removal method is identical with step S20.The silicon oxide layer 14 of the area of grid of removal photoetching glue residue and logic transistor is without sequencing in this step, carrying out first silicon oxide layer 14 removes and need clean together with photoetching glue residue, what use is band photoresistance manufacturing process for cleaning, and then removes photoetching glue residue; Remove first photoetching glue residue, carry out again silicon oxide layer 14 and remove, use be without the photoresistance processing procedure, in implementation process, the preferred latter's scheme.
Execution in step S23, form spin coating one deck photoresist on the structure at step S22, stay part photoresist 20 after the selectivity exposure, structural section figure as shown in figure 14, dry etching defines to form required gate location and the required gate location of logic transistor of word wiregrating 105 positions, high voltage transistor of separated grid electrode type quick flashing storage, obtains embedding the separated grid electrode type quick flashing storage structural representation of logical circuit as shown in figure 15.Described dry etch process can adopt technique of the prior art.This step is called for short the 4th etching (etch 4).Similar with erase gate 104, because the word wiregrating 105 final metal interconnecting layers (not shown) that pass through are electrically connected with peripheral circuit, therefore metal interconnecting wires and 103 conductings of control grid in order to prevent that word wiregrating 105 is electrically connected, so the thickness of word wiregrating 105 is less than the thickness sum of floating grid 101, the second insulating barrier 102, control grid 103 and hard mask layer 107 4.
Separated grid electrode type quick flashing storage in the background technology, in forming process deposit wipe grid (erase gate) polysilicon layer (ploy 3) in two steps selective etch can finish the making of independent separated grid electrode type quick flashing storage to form respectively erase gate and word wiregrating.Wherein, wipe the deposit of grid (erasegate) polysilicon layer (ploy 3), be equivalent to the poly1 step in the present embodiment one; Etching forms erase gate, is equivalent to the etch 2 in the present embodiment one; Etching forms the word wiregrating, is equivalent to the etch 4 in the present embodiment one.To sum up, compare with independent separated grid electrode type quick flashing storage formation method, cover through a polysilicon deposit, once oxidation silicon deposit, second etch, first BA RC material again, can form the separated grid electrode type quick flashing storage that embeds logical circuit, separated grid electrode type quick flashing storage is embedded in the peripheral circuit of high voltage transistor and logic transistor, as shown in figure 15, realize making separated grid electrode type quick flashing storage, high voltage transistor, logic transistor at an integrated circuit; This is so that the density of separated grid electrode type quick flashing storage, high voltage transistor, logic transistor increases, and the speed of service is faster, and integrated chip is less simultaneously, thereby has reduced the cost of each integrated chip.
In order to verify at dry etching to hard mask layer 107 processes that expose first area I, the yields of the device that the organic bottom antireflective material forms satisfies the semicon industry requirement, the present inventor forms the motor spindle antireflection material at the second polysilicon layer 25, utilize afterwards dry etching to the hard mask layer 107 that exposes first area I to form separated grid electrode type quick flashing storage, test afterwards gained yields result as shown in figure 31.Left figure is first wafer, is formed with 169 memories, and right figure is second wafer, is formed with 168 memories; Wherein, test result be 2,6,7,8 all be qualified product, therefore, the yields of left figure is 74.4%, the yields of right figure is 81.0%.
The second embodiment
Figure 16 shows that the manufacture method flow chart of the separated grid electrode type quick flashing storage group of the embedding logical circuit that second embodiment of the invention provides.The separated grid electrode type quick flashing storage group of described embedding logical circuit comprises the separated grid electrode type quick flashing storage of the embedding logical circuit of a pair of same size, and described every pair of separated grid electrode type quick flashing storage that embeds logical circuit comprises: separated grid electrode type quick flashing storage, high voltage transistor, logic transistor.Following manufacture method is take the separated grid electrode type quick flashing storage of a pair of embedding logical circuit as example.Identical with embodiment one, still take with the separated grid electrode type quick flashing storage of erase gate, word wiregrating as example.
Execution in step S11 ', semiconductor base 11 ' is provided, described semiconductor base comprises six zones, in order to form the separated grid electrode type quick flashing storage of a pair of identical embedding logical circuit, as shown in figure 17, six zones are specially: in order to first area I and the 4th regional IV that forms respectively a separated grid electrode type quick flashing storage, in order to second area II and the 5th regional V that forms respectively a high voltage transistor, be used for forming respectively the 3rd regional III and the 6th regional VI of a logic transistor; Described first area I is adjacent with the 4th regional IV.
Execution in step S12 ' forms the first insulating barrier 12 at described semiconductor base 11 ', as shown in figure 18; This step is identical with the first embodiment S12.
Execution in step S13 ' forms floating grid 101, the second insulating barrier 102, control grid 103, the hard mask layer 107 of a pair of successively stack, the side wall 106 of above-mentioned each layer side at the first insulating barrier 12 of first area I and the 4th regional IV.Structural section figure as shown in figure 19.
Need to prove, because the word wiregrating of separated grid electrode type quick flashing storage extremely generally need to be increased the write/read of voltage control separated grid electrode type quick flashing storage, therefore, the separated grid electrode type quick flashing storage of the embedding logical circuit of being made by embodiment one of a pair of same size, when forming the separated grid electrode type quick flashing storage group that embeds logical circuit, in order to prevent this group memory of high-voltage breakdown, this will be every certain thickness insulating barrier to memory, in other words, the pair of separated gate type flash memory distance of being separated by is greater than the distances between two control grids 103 of single separated grid electrode type quick flashing storage.In the present embodiment two, the separated grid electrode type quick flashing storage of formation is identical with embodiment one.But be pointed out that, since this to separated grid electrode type quick flashing storage be separated by distant, greater than the distance between two control grids 103 of single separated grid electrode type quick flashing storage, therefore when depositing polysilicon forms erase gate 104, the erase gate 104 between two control grids 103 of single separated grid electrode type quick flashing storage is can deposit very thick; Yet, this to separated grid electrode type quick flashing storage be separated by distant, between the thickness of polysilicon deposit less.
Execution in step S14 ', deposit the first polysilicon layer 13 on the first insulating barrier 12 of second area II and the 3rd regional III and the 5th regional V and the 6th regional VI and first area I and the 4th regional IV, structural section figure is as shown in figure 20.Described the first polysilicon layer 13 thickness are the logic transistor gate.
Execution in step S15 ', silicon oxide deposition layer 14 on the first polysilicon layer 13, structural section figure is as shown in figure 21.Described silicon oxide layer 14 thickness are less than the logic transistor gate.This step is identical with the first embodiment S15.
Execution in step S16 ' gets rid of except the silicon oxide layer 14 on the logic transistor grid, and structural section figure as shown in figure 22.This step is identical with the first embodiment S16.
Execution in step S17 ', deposit the second polysilicon layer 15 on described the first polysilicon layer 13 and silicon oxide layer 14, structural section figure is as shown in figure 23.Described the second polysilicon layer 15 thickness are the difference of high-pressure crystal tube grid desired thickness and logic transistor grid desired thickness.This step is identical with the first embodiment S17.
Execution in step S18 ' forms fluid material layer 16 at the second polysilicon layer 15, and structural section figure as shown in figure 24.Because it is good that the fillibility of fluent material is compared than the bedded substance in the deposit, thereby the thickness of the fluid material layer 16 of the lowest part of the second polysilicon layer 15 between adjacent separated grid electrode type quick flashing storage is not less than other regional fluid material layer 16, the first polysilicon layer 13, the second polysilicon layer 15 three's thickness sums.When S19 ' the step after this step has also guaranteed is carried out, can " not eat up " this to the polysilicon between the separated grid electrode type quick flashing storage.
Execution in step S19 ' adopts the area of grid of photoresist 17 protection high voltage transistors and the area of grid of logic transistor, and structural section figure utilizes dry etching to exposing hard mask layer 107 as shown in figure 25.The implementation method of this step is identical with the first embodiment S19.
Execution in step S20 ', photoetching glue residue and the fluent material residue of the area of grid of removal high voltage transistor and the area of grid of logic transistor obtain structural representation as shown in figure 26.This step is identical with the first embodiment S20.
Then execution in step S21 ' adopts photoresist to protect the area of grid of first area I, the 4th regional IV and high voltage transistor, as shown in figure 27, utilizes dry etching to the silicon oxide layer 14 of the area of grid that exposes logic transistor.
Follow execution in step S22 ', remove the silicon oxide layer 14 of the area of grid of photoetching glue residue and logic transistor, obtain structural representation as shown in figure 28.
Execution in step S23 ' forms spin coating one deck photoresist on the structure at step S22 ', stays part photoresist 20 after the selectivity exposure, and structural section figure as shown in figure 29; Dry etching defines to form required gate location and the required gate location of logic transistor of word wiregrating, high voltage transistor of separated grid electrode type quick flashing storage, obtain embedding logical circuit the separated grid electrode type quick flashing storage group structural representation as shown in figure 30.This step is identical with the first embodiment S23.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.Any those of ordinary skill in the art are not breaking away from the technical solution of the present invention scope situation, all can utilize the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention according to any simple modification, equivalent variations and the modification that technical spirit of the present invention is done above embodiment, all still belongs in the scope of technical solution of the present invention protection.
Claims (8)
1. a manufacture method that embeds the separated grid electrode type quick flashing storage of logical circuit is characterized in that, described manufacture method comprises:
Semiconductor base is provided, and described semiconductor base comprises Three regions: in order to form the first area of separated grid electrode type quick flashing storage, in order to form the second area of high voltage transistor, be used to form the 3rd zone of logic transistor;
Form the first insulating barrier at described semiconductor base;
Form successively floating grid, the second insulating barrier, control grid, hard mask layer on the first insulating barrier of first area, described floating grid, the second insulating barrier, control grid, hard mask layer side cover side wall;
Deposit the first polysilicon layer on first insulating barrier in second area and the 3rd zone and first area, the thickness of described the first polysilicon layer is logic transistor grid desired thickness;
Silicon oxide deposition layer on the first polysilicon layer, described silicon oxide layer thickness is less than logic transistor grid desired thickness;
Keep the silicon oxide layer on the 3rd zone, get rid of the silicon oxide layer of first area and second area;
Deposit the second polysilicon layer on described the first polysilicon layer and silicon oxide layer, described the second polysilicon layer thickness are the difference of high-pressure crystal tube grid desired thickness and logic transistor grid desired thickness;
Form fluid material layer at described the second polysilicon layer;
Adopt the second polysilicon layer of photoresist protection second area and second polysilicon layer in the 3rd zone, utilize dry etching to exposing hard mask layer;
Remove photoetching glue residue and fluent material residue;
Hard mask layer on the employing photoresist protection first area and the second polysilicon layer of the second polysilicon layer and second area utilize dry etching to the silicon oxide layer that exposes the 3rd zone;
Remove the silicon oxide layer in photoetching glue residue and the 3rd zone;
Etching forms required grid and the required grid of logic transistor of word wiregrating, high voltage transistor of separated grid electrode type quick flashing storage.
2. manufacture method according to claim 1 is characterized in that, described fluid material layer material is the organic bottom antireflective material.
3. manufacture method according to claim 1 is characterized in that, utilizes dry etching to exposing in the hard mask layer step, and the etching gas that described dry etching adopts is fluid materials with the etching polysilicon ratio is 5: 4 etching gas.
4. manufacture method according to claim 3 is characterized in that, the main etching gas of described etching gas is: Cl
2, HBr, SF
6, CF
4, CHF
3, CH
2F
2In at least two kinds, auxiliary etch gas is Ar, O
2In at least a.
5. manufacture method that embeds the separated grid electrode type quick flashing storage group of logical circuit, the separated grid electrode type quick flashing storage group of described embedding logical circuit comprises the separated grid electrode type quick flashing storage of the embedding logical circuit of a pair of same size, it is characterized in that, described manufacture method comprises:
Semiconductor base is provided, described semiconductor base comprises six zones: in order to first area and the 4th zone that forms respectively a separated grid electrode type quick flashing storage, in order to second area and the 5th zone that forms respectively a high voltage transistor, be used for forming respectively the 3rd zone and the 6th zone of a logic transistor; Described first area is adjacent with the 4th zone;
Form the first insulating barrier at described semiconductor base;
Respectively form floating grid, the second insulating barrier, control grid, the hard mask layer of a pair of successively stack on first area and four-range the first insulating barrier, described floating grid, the second insulating barrier, control grid, hard mask layer side cover side wall;
Deposit the first polysilicon layer on second area and the 3rd zone and the 5th zone and first insulating barrier in the 6th zone and first area and the 4th zone, the thickness of described the first polysilicon layer is logic transistor grid desired thickness;
Silicon oxide deposition layer on the first polysilicon layer, described silicon oxide layer thickness is less than logic transistor grid desired thickness;
Keep the silicon oxide layer on the 3rd zone and the 6th zone, get rid of the silicon oxide layer in first area and second area and the 4th zone and the 5th zone;
Deposit the second polysilicon layer on described the first polysilicon layer and silicon oxide layer, described the second polysilicon layer thickness are the difference of high-pressure crystal tube grid desired thickness and logic transistor grid desired thickness;
Form fluent material at the second polysilicon layer, the thickness of the fluent material of the lowest part of the second polysilicon layer between the floating grid of adjacent successively stack, the second insulating barrier, control grid, hard mask layer is not less than the floating grid of described successively stack, the second insulating barrier, control grid, the height sum of hard mask layer and the difference of the first polysilicon layer and the second polysilicon layer thickness sum;
Adopt second polysilicon layer in photoresist protection second area and the 5th zone and second polysilicon layer in the 3rd zone and the 6th zone, utilize dry etching to exposing hard mask layer;
Remove photoetching glue residue and fluent material residue;
Hard mask layer on employing photoresist protection first area and the 4th zone and second polysilicon layer in the second polysilicon layer and second area and the 5th zone utilize dry etching to exposing the silicon oxide layer of the 3rd zone with the 6th zone;
Remove the silicon oxide layer in photoetching glue residue and the 3rd zone and the 6th zone;
Etching forms required grid and the required grid of logic transistor of word wiregrating, high voltage transistor of separated grid electrode type quick flashing storage.
6. manufacture method according to claim 5 is characterized in that, described fluid material layer material is the organic bottom antireflective material.
7. manufacture method according to claim 6 is characterized in that, utilizes dry etching to exposing in the hard mask layer step, and the etching gas that described dry etching adopts is fluid materials with the etching polysilicon ratio is 5: 4 etching gas.
8. manufacture method according to claim 7 is characterized in that, the main etching gas of described etching gas is: Cl
2, HBr, SF
6, CF
4, CHF
3, CH
2F
2In at least two kinds, auxiliary etch gas is Ar, O
2In at least a.
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| CN106876399A (en) * | 2017-02-14 | 2017-06-20 | 上海华虹宏力半导体制造有限公司 | A kind of method for preventing Split-gate flash memory floating boom and wordline residual polycrystalline silicon |
| CN106876399B (en) * | 2017-02-14 | 2020-06-16 | 上海华虹宏力半导体制造有限公司 | Method for preventing floating gate of split-gate flash memory and word line polysilicon residue |
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