JPH11186415A - Non-volatile semiconductor storage device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor storage device in which the faced areas of a floating gate electrode and a control gate electrode are made large, and a high speed operation can be attained. SOLUTION: A non-volatile semiconductor storage device is provided with an isolated oxide film 53 formed in a groove 10. The surface of the isolated oxide film 53 is arranged at a lower position than that of the main surface of a silicon substrate 1. A floating gate electrode 4 and a control gate electrode 6 are formed so as to be extended from the main surface of the silicon substrate 1 to the surface of the isolated oxide film 53.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same, and more particularly, to an electrically erasable and writable EEPROM (Electrically Erasable).
and more specifically, to a so-called flash memory and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, as one of nonvolatile semiconductor memory devices, an EEPROM capable of freely programming data and electrically writing and erasing information.
It has been known.

As one type, a memory cell has one type.
2. Description of the Related Art A flash memory including one transistor and capable of electrically erasing written information charges in a batch is known.

FIG. 8 is a partial plan view of a conventional flash memory. 9A and 9B are cross-sectional views of one memory cell of a conventional flash memory, in which FIG. 9A is a cross-sectional view taken along line AA in FIG. 8, and FIG. B-
It is a figure showing the section seen along the B line.

Referring to FIGS. 8 and 9, an isolation oxide film 117 is formed on the surface of silicon substrate 111. Referring to FIG. A floating gate electrode 113a is formed on a portion of the surface of silicon substrate 111 surrounded by isolation oxide film 117 with tunnel oxide film 112 interposed. ONO as a dielectric film is formed on the floating gate electrode 113a.
A film 118 is formed. The ONO film 118 has a three-layer structure of a silicon oxide film, a silicon nitride film, and a silicon oxide film. A control gate electrode 119 is formed to cover the ONO film 118.

When operating the flash memory configured as described above, a voltage is applied to the control gate electrode 119. Then, the control gate electrode 119
Since a capacitor is formed between the floating gate electrode 113a and the floating gate electrode 113a.
A voltage is applied to a. Thereby, the silicon substrate 11
Electrons are injected from 1 into the floating gate electrode 113a, and the charge is held.

[0007]

In the flash memory as described above, in order to increase the operation speed, that is, the operation such as writing, the floating gate electrode 1 is required.
It is necessary to apply a large voltage to 13a. To this end, it is conceivable to increase the voltage applied to the control gate electrode 119 or to increase the capacitance between the floating gate electrode 113a and the control gate electrode 119.

However, in order to increase the voltage applied to the control gate electrode 119, a circuit for generating a high voltage is required, and the size of the flash memory itself increases, which is not preferable.

Therefore, the floating gate electrode 11
It is preferable to increase the capacitance between 3a and control gate electrode 119. Here, the capacitance C between the floating gate electrode 113a and the control gate electrode 119 is represented by the following equation.

[0010]

(Equation 1)

Here, ε ₀ : dielectric constant of vacuum, ε: ONO
The dielectric constant of the film 118, d: the thickness of the ONO film 118, and S: the facing area between the floating gate electrode 113a and the control gate electrode 119. To increase the capacitance C, it is conceivable to reduce the film thickness and increase the facing area.

S is obtained by the following equation.

[0013]

(Equation 2)

Here, x ₀ is the length of the ONO film 118 on the tunnel oxide film 112 in FIG.
y ₀ is the length of the ONO film 118 in the side surface of the floating gate electrode 113a in (A) of FIG. 9, z ₀
Represents the width of the ONO film 118 in FIG.

Since there is a limit in reducing d, it is necessary to increase the facing area S in order to increase the capacitance C.

A flash memory having a relatively large facing area S is described in Japanese Patent Application Laid-Open No. 9-116035.
FIGS. 10A and 10B are cross-sectional views of a memory cell of a flash memory described in the above publication, where FIG. 10A corresponds to FIG. 9A and FIG. 10B corresponds to FIG. 9B.

In the memory cell shown in FIG. 9, an isolation oxide film 117 is formed on the surface of silicon substrate 111, whereas in the memory cell shown in FIG.
A groove 111a is formed on the surface of the substrate 1 and an isolation oxide film 117 is formed in the groove 111a. In other respects, the structure shown in FIG. 10 is similar to the structure shown in FIG. Further, x ₁ is the length of the ONO film 118 on the tunnel oxide film 112 in FIG. 10 (A), y ₁ is the floating gate electrode 113 in FIG. 10 (A)
the length of the ONO film 118 in the sides of a, z ₁ Figure 1
This is the width of the ONO film 118 in FIG. The facing area S between the floating gate electrode 113a and the control gate electrode 119 is expressed by the following equation.

[0018]

(Equation 3)

[0019] In such a configuration memory cell, since the height of the surface of the isolation oxide film 117a is lower than that shown in Figure 9, a y ₀ <y _1.

Here, since the size of the memory cell itself is the same as that shown in FIG. 9 and that shown in FIG. 10, x ₀ =
x ₁ , z ₀ = z ₁ . Therefore, in the memory cell shown in FIG. 10 y ₁ is larger by min than y _0, the facing area S of the floating gate electrode 113 and the control gate 119 is larger than the memory cell shown in Figure 9, the capacitance C is increased . .

In recent years, however, flash memories have been required to operate at higher speeds, and it is necessary to further increase the capacitance between the floating gate electrode and the control gate electrode.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above-described problem, and has an object to provide a nonvolatile semiconductor memory device having a large opposing area between a floating gate electrode and a control gate electrode and capable of high-speed operation. It is intended to provide.

[0023]

A nonvolatile semiconductor memory device according to the present invention has a semiconductor substrate having a main surface and a floating substrate formed on the main surface of the semiconductor substrate with a first dielectric film interposed therebetween. A gate electrode; and a control gate electrode formed on the floating gate electrode with a second dielectric film interposed therebetween. The semiconductor substrate has a groove formed in a portion adjacent to the floating gate electrode. The non-volatile semiconductor storage device further includes an isolation insulating film formed in the groove. The surface of the isolation insulating film has a position lower than the main surface of the semiconductor substrate. The floating gate electrode and the control gate electrode are formed to extend from above the main surface of the semiconductor substrate to above the surface of the isolation insulating film.

In the nonvolatile semiconductor memory device thus configured, since the surface of the isolation insulating film has a position lower than the main surface of the semiconductor substrate, the gap between the main surface of the semiconductor substrate and the surface of the isolation insulating film is reduced. Has a step. Since the floating gate electrode and the control gate electrode extend from the main surface of the semiconductor substrate to the surface of the isolation insulating film, the control gate electrode is formed on the floating gate electrode even at a portion along the step. Therefore, the facing area between the floating gate electrode and the control gate electrode can be increased as compared with the case where there is no step, and high-speed operation can be performed.

A method for manufacturing a nonvolatile semiconductor memory device according to the present invention includes the following steps. (1) A step of forming a groove in a part of a main surface of a semiconductor substrate.

(2) A step of forming an isolation insulating film having a surface at a position lower than the main surface of the semiconductor substrate in the groove.

(3) A step of forming a first dielectric film, a floating gate electrode, a second dielectric film, and a control gate electrode in order to cover the main surface of the semiconductor substrate and the surface of the isolation insulating film.

In the method of manufacturing a nonvolatile semiconductor memory device having such steps, since the floating gate electrode and the control gate electrode are formed after forming the isolation insulating film, the floating gate electrode and the control gate electrode are oxidized. As a result, the area of the floating gate electrode and the control gate electrode facing each other is increased. Therefore, a nonvolatile semiconductor memory device that can operate at high speed can be provided.

The step of forming a groove in a part of the main surface of the semiconductor substrate includes forming an insulating film containing silicon and oxygen on the main surface of the semiconductor substrate, and forming a silicon nitride film on the insulating film. And selectively removing the insulating film, the silicon nitride film, and a portion near the main surface of the semiconductor substrate. The step of forming the isolation insulating film in the trench involves oxidizing the surface of the semiconductor substrate. It is preferable to include forming an isolation insulating film by the following method. In this case, when forming the isolation insulating film, an insulating film containing silicon and oxygen is formed on the main surface of the semiconductor substrate. Therefore, even when the surface of the semiconductor substrate which is not in contact with the insulating film is oxidized, no distortion occurs on the main surface of the semiconductor substrate which is in contact with the insulating film, so that a high quality nonvolatile semiconductor memory device can be provided.

[0030]

(First Embodiment) FIG. 1 is a plan view of a nonvolatile semiconductor memory device (flash memory) according to a first embodiment of the present invention. Referring to FIG. 1, a plurality of word lines (control gate electrodes) 6 and a plurality of bit lines 52 are arranged to be orthogonal to each other.
At the intersection of the word line 6 and the bit line 52, a floating gate electrode 4 is formed below the word line 6. The floating gate electrode 4 is adjacent to the word line 6 in the extending direction, and an isolation oxide film 53 as an isolation insulating film is formed therebetween. On both sides of the word line 6, a drain region 12 and a source region 13 are formed. The drain region 12 has a bit line 52
Is electrically connected to

FIG. 2 is a cross-sectional view of the nonvolatile semiconductor memory device shown in FIG. 1, (A) is a cross-sectional view taken along line AA in FIG. 1, and (B) is a cross-sectional view. FIG. 2 is a diagram showing a cross section viewed along line BB in FIG. 1. Referring to FIG. 2, a groove 10 having a depth h of about 1500 ° is formed in silicon substrate 1. In the groove 10, an isolation oxide film 53 having a height H from the bottom surface of the groove 10 of about 1000 ° is formed. On the surface of the silicon substrate 1, a tunnel oxide film 3 having a thickness of about 130 ° as a first dielectric film is formed. On tunnel oxide film 3, floating gate electrode 4 having a thickness of 500-1500 ° and made of doped polysilicon is formed. On the floating gate electrode 4, a silicon oxide film, a silicon nitride film and a silicon oxide film
An ONO film 5 is formed as a second dielectric film having a thickness of 150 to 250 °. On ONO film 5, control gate electrode 6 having a thickness of 500-1500 ° and made of doped polysilicon is formed.

The surface of the isolation oxide film 53 is
Is formed at a position lower than the surface 1a of the silicon substrate 1 on which the isolation oxide film 53 is formed.
There is a step 53a between itself and a. The floating gate electrode 4 and the ONO film 5 extend along the step 53a.
And the control gate electrode 6 extend, so that the floating gate electrode 4 and the control gate electrode 6 face each other even on the step 53a.

In FIG. 2A, the tunnel oxide film 3
The ONO film 5 above has a length of x ₂ and ON on the step 53a.
The length of the O film 5 is w ₂ , the length of the ONO film 5 on the side surface of the floating gate electrode 4 is y ₂ , and ON in FIG.
The width of the O film 5 is z ₂ and the floating gate electrode 4
And the control gate electrode 6 have an area S facing each other.

[0034]

(Equation 4)

A silicon oxide film 8 is formed on silicon substrate 1 so as to cover control gate electrode 6, and contact hole 9 reaching drain region 12 is formed in silicon oxide film 8. Bit line 52 is formed to fill contact hole 9 and on the surface of silicon oxide film 8.

In the flash memory of the present invention thus configured, the facing area between the floating gate electrode 4 and the control gate electrode 6 is given by the above equation. As a result, the facing area S increases by an amount represented by 2w ₂ z ₂ , so that the capacity increases and high-speed operation becomes possible.

(Embodiment 2) FIGS. 3 to 7 are sectional views showing a method of manufacturing the nonvolatile semiconductor memory device shown in FIG. 3A to 7, (A) is a diagram corresponding to (A) in FIG. 2, and (B) is a diagram corresponding to the cross section illustrated in (B) of FIG. 2.

Referring to FIG. 3, CV is formed on silicon substrate 1.
A silicon oxynitride (SiON) film 61 having a thickness of 100 ° is formed by the method D. A silicon nitride film 62 having a thickness of 600 ° is formed on silicon oxynitride film 61 by a CVD method.

Referring to FIG. 4, a resist on silicon nitride film 62 is applied, and the resist is patterned into a predetermined shape to form a resist pattern (not shown).
The groove 10 is formed by etching the silicon nitride film 62, the silicon oxynitride film 61, and the silicon substrate 1 according to the resist pattern. At this time, the silicon substrate 1
The depth from the surface 1a to the bottom of the groove 10 is about 1500 mm.
And

Referring to FIG. 5, by keeping silicon substrate 1 in an oxidizing atmosphere, portions of silicon substrate 1 not covered with silicon oxynitride film 61 are oxidized. As a result, an isolation oxide film 53 having a height from the bottom surface to the surface (H in FIG. 5A) of about 1000 ° is formed. At this time, the silicon oxynitride film 6
The part covered with 1 is also slightly oxidized.

Referring to FIG. 6, silicon nitride film 62 and silicon oxynitride film 61 are etched with a high-temperature phosphoric acid aqueous solution. At this time, the isolation oxide film 53 is also slightly etched, and the surface 1a of the silicon substrate 1 is exposed.

Referring to FIG. 7, after a thermal oxide film having a thickness of 130.degree. And a doped polysilicon having a thickness of 500-1500.degree. Are formed on the surface of silicon substrate 1, the doped polysilicon and the thermal oxide film are etched. Thereby, a floating gate electrode 4 and a tunnel oxide film 3 are formed. By implanting impurity ions into the silicon substrate 1 using the floating gate electrode 4 as a mask, a drain region 12 and a source region 13 are formed.

Referring to FIG. 2, a three-layer film having a thickness of 150 to 250 and a thickness of 500 to 1500 made of a silicon oxide film, a silicon nitride film and a silicon oxide film are formed on a silicon substrate 1.
After the doped polysilicon is formed, the control gate electrode 6 and the ONO film 5 are formed by etching the doped polysilicon and the three-layer film.

A silicon oxide film 8 is formed on silicon substrate 1 so as to cover control gate electrode 6. By etching the silicon oxide film 8, a contact hole 9 reaching the drain region 12 is formed. By forming bit lines 52 made of doped polysilicon on the surface of silicon oxide film 8 so as to fill contact holes 9, the nonvolatile semiconductor memory device (flash memory) shown in FIG. 2 is completed.

In such a manufacturing method, a non-volatile semiconductor memory device having a large opposing area between floating gate electrode 4 and control gate electrode 6 and capable of high-speed operation as shown in FIG. 2 is manufactured according to a normal process. be able to. Further, since the floating gate electrode 4 and the control gate electrode 6 are formed after the formation of the isolation oxide film 53, these electrodes are not oxidized.
Furthermore, when the isolation oxide film 53 is formed, the surface of the silicon substrate 1 is covered with the silicon oxynitride film 61, and thus, in the portion covered with the silicon oxynitride film 6, distortion occurs on the surface of the silicon substrate 1. It does not occur.

Although the embodiment of the present invention has been described above, the embodiment shown here can be variously modified. First, the silicon oxynitride film 61 shown in FIG. 3 can be replaced with a silicon oxide film. Further, the film thickness, the depth of the groove, and the like can be appropriately changed as needed.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0048]

According to the first or second aspect of the present invention, it is possible to provide a nonvolatile semiconductor memory device having a large opposing area between the floating gate electrode and the control gate electrode and capable of high-speed operation.

According to the third aspect of the present invention, it is possible to provide a nonvolatile semiconductor memory device capable of operating at high speed without causing distortion on the surface of the silicon substrate when forming the isolation oxide film.

[Brief description of the drawings]

FIG. 1 is a plan view of a nonvolatile semiconductor memory device according to the present invention.

FIGS. 2A and 2B are cross-sectional views of the nonvolatile semiconductor memory device shown in FIG. 1, in which FIG. 1A is a cross-sectional view taken along line AA in FIG. 1, and FIG. It is a figure showing the section seen along the BB line in the inside.

3A and 3B are cross-sectional views showing a first step of the method for manufacturing the nonvolatile semiconductor memory device shown in FIG. 2, wherein FIG. 3A is a view corresponding to FIG. 2A, and FIG. It is a figure corresponding to (B) of FIG.

4A and 4B are cross-sectional views showing a second step of the method for manufacturing the nonvolatile semiconductor memory device shown in FIG. 2, wherein FIG. 4A is a view corresponding to FIG. 2A, and FIG. It is a figure corresponding to (B) of FIG.

5A and 5B are cross-sectional views showing a third step of the method for manufacturing the nonvolatile semiconductor memory device shown in FIG. 2, wherein FIG. 5A is a view corresponding to FIG. 2A, and FIG. It is a figure corresponding to (B) of FIG.

6A and 6B are cross-sectional views showing a fourth step of the method for manufacturing the nonvolatile semiconductor memory device shown in FIG. 2, wherein FIG. 6A is a view corresponding to FIG. 2A, and FIG. It is a figure corresponding to (B) of FIG.

FIGS. 7A and 7B are cross-sectional views showing a fifth step of the method for manufacturing the nonvolatile semiconductor memory device shown in FIG. 2; FIG. 7A is a view corresponding to FIG. It is a figure corresponding to (B) of FIG.

FIG. 8 is a plan view of a conventional nonvolatile semiconductor memory device.

9A and 9B are cross-sectional views of the nonvolatile semiconductor memory device shown in FIG. 8, in which FIG. 9A is a cross-sectional view taken along line AA in FIG. 8, and FIG. It is a figure showing the section seen along the BB line in the inside.

FIGS. 10A and 10B are cross-sectional views of an improved conventional nonvolatile semiconductor memory device, where FIG. 10A is a diagram corresponding to FIG. 9A and FIG. 10B is a diagram corresponding to FIG. 9B; FIG.

[Explanation of symbols]

Reference Signs List 1 silicon substrate, 3 tunnel oxide film, 4 floating gate electrode, 5 ONO film, 6 control gate electrode, 10 groove, 53 isolation oxide film, 61 silicon oxynitride film, 62 silicon nitride film.

Claims (3)

[Claims] A semiconductor substrate having a main surface; a floating gate electrode formed on the main surface of the semiconductor substrate with a first dielectric film interposed therebetween; and a second dielectric on the floating gate electrode. A control gate electrode formed with a film interposed therebetween, wherein the semiconductor substrate has a groove formed in a portion adjacent to the floating gate electrode, and further includes an isolation insulating film formed in the groove. The surface of the isolation insulating film has a position lower than the main surface of the semiconductor substrate, and the floating gate electrode and the control gate electrode are on the surface of the isolation insulating film from above the main surface of the semiconductor substrate. A nonvolatile semiconductor memory device formed to extend. A step of forming a groove in a part of a main surface of the semiconductor substrate; a step of forming an isolation insulating film having a surface at a position lower than the main surface of the semiconductor substrate in the groove; A step of sequentially forming a first dielectric film, a floating gate electrode, a second dielectric film, and a control gate electrode so as to cover a main surface of the semiconductor device and a surface of the isolation insulating film, Device manufacturing method. 3. The step of forming the trench includes: forming an insulating film containing silicon and oxygen on a main surface of the semiconductor substrate; forming a silicon nitride film on the insulating film; Selectively removing an insulating film, the silicon nitride film, and a portion near a main surface of the semiconductor substrate, wherein the step of forming the isolation insulating film in the trench includes oxidizing a surface of the semiconductor substrate. The method for manufacturing a nonvolatile semiconductor memory device according to claim 2, further comprising forming the isolation insulating film by the following method.