JP2002006340A - Liquid crystal device and manufacturing method therefor, and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal device having MOS type storage capacitance permitting to improve a yield and reliability by effectively reducing a voltage to be applied to a dielectric film. SOLUTION: In the liquid crystal device of this invention, a liquid crystal 16 is held between a TFT array substrate 7 and a counter substrate 15 faced to each other; a TFT array substrate 7 is provided thereon with plural scanning lines 4 and plural data lines crossing each other, plural pixel electrodes 1 arranged in a matrix form, plural TFTs 2, and a storage capacitance part 5; impurity ions for decreasing a threshold voltage of a MOS transistor are injected into the channel area of the MOS transistor forming the storage capacitance part 5; and thereby the MOS transistor forming the storage capacitance becomes the one of depression type.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal device, a method of manufacturing the same, and electronic equipment, and more particularly to a structure of a MOS type storage capacitor used in a liquid crystal device.

[0002]

2. Description of the Related Art For example, a thin film transistor (Thin Film)
Transistor (hereinafter sometimes abbreviated as TFT) as a switching element in an active matrix drive type liquid crystal display device, a large number of scanning lines and data lines are arranged in a matrix in a matrix, and at each intersection thereof. Correspondingly, a large number of TFTs are provided on the TFT array substrate. In each TFT, a gate electrode is connected to a scanning line, a source region of a semiconductor layer is connected to a data line, and a drain region of the semiconductor layer is connected to a pixel electrode. When a scanning signal is supplied to the gate electrode of the TFT via the scanning line, the channel region between the source region and the drain region of the TFT is inverted, the TFT is turned on, and the semiconductor layer is connected via the data line. Is supplied to the pixel electrode via the channel region.

[0003] However, the supply of such an image signal is as follows.
Only a very short time is carried out for each pixel electrode via each TFT. Therefore, the TF which is turned on only for a very short time
In order to hold the voltage of the image signal supplied via T for a much longer time than the on state, a storage capacitor is generally formed in each pixel electrode in parallel with the liquid crystal capacitor. It is a target.

In order to form a storage capacitor, a method of forming a capacitor by partially arranging a pixel electrode of an arbitrary pixel and a scanning line in the preceding stage of the pixel, or a method of forming a dedicated capacitor line using a TFT, for example,
And a method of providing a capacitor by overlapping the semiconductor layer. The former can increase the aperture ratio, but has the disadvantage that the parasitic capacitance connected to the scanning line increases and the wiring delay increases. on the other hand,
The latter have a lower aperture ratio, but do not affect the scanning lines,
There is an advantage that uniformity of display is easily ensured.

In the latter case, that is, when a capacitance is formed by a capacitance line and a semiconductor layer, an impurity is usually introduced into a portion of the semiconductor layer overlapping the capacitance line to cause the semiconductor layer to have a sufficiently low resistance. It is a very common configuration to use a capacitor instead of a conductor. On the other hand, there has been proposed a configuration in which an impurity is not introduced into a portion of the semiconductor layer overlapping the capacitor line, and the portion of the semiconductor layer is used as it is as a semiconductor to form a capacitor having a so-called MOS structure.

FIG. 11 shows an example of the configuration of a pixel having a MOS-type capacitor as a storage capacitor, which is described in the literature ("A 10.4-in. XG
A Low-Temperature Poly-Si TFT-LCD for Mobile PC Ap
replications ", Y.Aoki et al., p.176-179, SID'99 DIGE
ST, 1998).

In the pixel shown in FIG.
Is a dual-gate n-channel TFT in which two gate electrodes 101 are provided on one semiconductor layer 102,
An n-channel MOS storage capacitor 103 is provided using the semiconductor layer 102. As described above, in the case where a MOS capacitor is used as the storage capacitor, an ion implantation step for introducing an impurity into a portion of the semiconductor layer overlapping the capacitor line is not necessary, and thus the number of steps in the manufacturing process can be reduced. can get.

[0008]

SUMMARY OF THE INVENTION However, MOS
There are the following problems in a liquid crystal device using a type storage capacitor. In the case of a normal storage capacitor in which impurities are sufficiently introduced into the semiconductor layer and used as a conductor, the applied voltage (for example, the potential on the capacitor line side when the semiconductor layer side is set as the reference potential) is plotted on the horizontal axis, and the capacitance is plotted on the vertical axis. The capacitance (CV) characteristic at the time of application shows linearity, and the capacitance is formed regardless of whether the applied voltage is positive or negative. Therefore, for example, if the image signal is
Assuming that a pulse waveform P as shown in (a) is shown, the potential on the semiconductor layer side fluctuates according to this pulse waveform, so that the potential level Vc on the capacitor line side can be set at the center of the pulse amplitude.

On the other hand, in a MOS type storage capacitor,
When the MOS transistor is turned on, a capacitance is formed. That is, in the case of an n-channel MOS type storage capacitor, CV characteristics as shown in FIG.
A capacitance is formed when the applied voltage exceeds a threshold value V _{th1 of} , for example, about 1 to 2 V. As described above, in the MOS storage capacitor, a capacitance is formed only in one of the positive and negative applied voltages. Therefore, the potential level on the capacitance line side cannot be set at the center of the pulse amplitude as shown in FIG. 9A, and a certain margin (for example, switching) is applied to the pulse amplitude as shown in FIG. 9B. _Assuming that the threshold value of the TFT for use is V _th2 , the potential level Vc ′ on the capacitance line side must be set to a value that allows for V _th2 × 2 + α).

Due to such a difference, the voltage effectively applied to the dielectric film (the gate insulating film of the TFT corresponds to this film) interposed between the semiconductor layer and the capacitance line is different from that of a normal storage capacitor. Is about half the amplitude of the image signal pulse, whereas in the case of the MOS type storage capacitor, the value exceeds the pulse amplitude of the image signal, which is considerably larger than that of a normal storage capacitor. As a result, insulation failure may occur due to a defect in the dielectric film and the like, which may cause a problem such as a decrease in product yield and a decrease in reliability due to aging of the dielectric film.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to effectively reduce the voltage applied to a dielectric film so as to improve the yield and reliability. It is an object to provide a liquid crystal device having a capacitance, a method of manufacturing the same, and an electronic device using the same.

[0012]

In order to achieve the above object, a liquid crystal device according to the present invention comprises a liquid crystal interposed between a pair of substrates facing each other, and a liquid crystal device is provided on one of the pair of substrates. A plurality of scanning lines and a plurality of data lines provided to intersect with each other, and a plurality of pixel electrodes arranged in a matrix corresponding to the intersection of the scanning line and the data line,
A liquid crystal device having a plurality of thin film transistors serving as switching elements of the pixel electrodes and a plurality of MOS storage capacitors, wherein the MOS transistor forming the MOS storage capacitor is a depletion type MOS transistor. Things.

In the case of a conventional MOS storage capacitor, FIG.
As shown in (a), the capacitance is formed only when the applied voltage is either positive or negative, and the capacitance is formed when the applied voltage exceeds a predetermined threshold. The potential of one conductor layer corresponding to the gate electrode of the MOS transistor must be set to a value exceeding the amplitude of the image signal pulse. On the other hand, if the MOS transistor forming the storage capacitor is of the depletion type as in the present invention, the threshold voltage of the transistor is lower than the original threshold voltage of the MOS transistor before conversion to the depletion type. To do so, C
The -V characteristic is also changed from the state shown in FIG.
State changes shown in (i.e., if the n-channel type, the threshold voltage changes from V _th1 to V _th1 'C-V curve from the right to move parallel to the left). In other words, the same capacitance can be formed without increasing the potential of one conductor layer corresponding to the gate electrode of the MOS transistor forming the storage capacitor as compared with the conventional case.

As a result, the voltage effectively applied to the dielectric film interposed between the semiconductor layer and the capacitance line is reduced by the conventional MOS.
Since it can be reduced as compared with the case of the type storage capacitor, the probability of occurrence of insulation failure due to a defect or the like of the dielectric film can be reduced, and the yield of products can be improved. In addition, the reduction in the effective applied voltage to the dielectric film reduces the deterioration with time of the dielectric film, so that the reliability can be improved.

More specifically, the depletion type MOS transistor is formed by introducing an impurity which lowers the threshold voltage of the MOS transistor into at least a channel region of the MOS transistor forming the MOS type storage capacitor. be able to. For example, when using an n-channel type MOS storage capacitor,
Depletion of the transistor may be achieved by introducing a Group V impurity such as phosphorus into the channel region. Conversely, in the case of a p-channel type, a group III impurity such as boron may be introduced.

[0016] Even if it is simply called a depletion type MOS transistor, there are various degrees of depletion. In the present invention, if the threshold voltage of the original MOS transistor before conversion to the depletion type is slightly depleted, there is a certain effect, but the threshold of the original MOS transistor before conversion to the depletion type is obtained. It is more preferable to deplete the voltage from the polarity of the value voltage to the level of the threshold voltage having the opposite polarity.

With this configuration, the voltage applied to the conductor layer corresponding to the gate electrode of the depletion type MOS transistor can be set within the range of the amplitude of the image signal pulse in the liquid crystal device. That is, since the capacitance in this case exhibits almost the same behavior as that of a conventional general storage capacitor having no MOS structure, the potential of one conductor layer corresponding to the gate electrode of the MOS transistor is set at the center of the pulse amplitude. And the effective applied voltage to the dielectric film can be reduced more sufficiently.

As a specific configuration of the depletion type MOS transistor, a switching element T
A semiconductor layer which is integrated with a semiconductor layer constituting the FT, has a channel region of the MOS transistor, and is formed so as to at least partially overlap the semiconductor layer;
It can be constituted by a capacitor line serving as a gate electrode of an OS transistor, and a dielectric film interposed between the semiconductor layer and the capacitor line. According to this configuration, the MOS-type storage capacitor can be formed simultaneously with the formation of the TFT, and a rational manufacturing process can be achieved.

In the method of manufacturing a liquid crystal device according to the present invention, a liquid crystal is sandwiched between a pair of substrates opposed to each other, and a plurality of scanning lines provided crossing each other on one of the pair of substrates. And a plurality of data lines, a plurality of pixel electrodes arranged in a matrix corresponding to intersections of the scanning lines and the data lines, a plurality of thin film transistors as switching elements of the pixel electrodes, and a plurality of MOS type storage devices. A method of manufacturing a liquid crystal device having a capacitance,
Implanting impurity ions for lowering the threshold voltage of the MOS transistor into at least a channel region of a semiconductor layer forming a MOS transistor forming a MOS storage capacitor.
It is characterized by depletion of a MOS transistor forming a type storage capacitor. According to the method for manufacturing a liquid crystal device of the present invention, the liquid crystal device of the present invention can be easily realized.

The implantation of the impurity ions into the semiconductor layer may be performed before the formation of the dielectric film covering the semiconductor layer, or may be performed through the dielectric film after the formation of the dielectric film.

An electronic apparatus according to the present invention includes the liquid crystal device according to the present invention. According to this, an electronic device having a highly reliable liquid crystal display unit can be realized.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is an equivalent circuit of various elements, wiring, and the like in a plurality of pixels forming an image display area of the liquid crystal device of the present embodiment. FIG. 2 shows a data line,
FIG. 4 is a plan view of a plurality of adjacent pixel groups on a TFT array substrate on which scanning lines, pixel electrodes, and the like are formed. FIG. 3 is a cross-sectional view taken along line AA ′ in FIG.
The left side is a cross-sectional view taken along the line BB 'of FIG. 2 showing the TFT portion. FIG. 4 is a process cross-sectional view for explaining the manufacturing process of the TFT array substrate. FIG. 5 is a plan view showing the overall configuration of the liquid crystal device. In particular, in FIG.
In order to make each layer and each member a size recognizable in the drawings, the scale of each layer and each member is different.

[Structure of Main Parts of Liquid Crystal Device] As shown in FIG. 1, in the liquid crystal device according to the present embodiment, a plurality of pixels formed in a matrix forming an image display area are composed of a pixel electrode 1 and the pixel. A plurality of TFTs 2 for controlling the electrodes 1 are formed in a matrix, and a data line 3 for supplying an image signal is electrically connected to a source region of the TFT 2. Image signals S1 and S written to data line 3
,..., Sn may be supplied line-sequentially in this order, or may be supplied to a plurality of adjacent data lines 3 for each group. Further, the scanning line 4 is electrically connected to the gate electrode of the TFT 2, and the scanning signal G is pulsed to the scanning line 4 at a predetermined timing.
, Gm are applied line-sequentially in this order. The pixel electrode 1 is electrically connected to the drain region of the TFT 2. By closing the switch of the TFT 2 serving as a switching element for a certain period, the image signals S 1, S 2,
..., Sn is written at a predetermined timing.

The image signals S1, S2,..., Sn of a predetermined level written in the liquid crystal via the pixel electrode 1 are exchanged with a counter electrode (described later) formed on a counter substrate (described later) for a certain period. Will be retained. Here, in order to prevent the held image signal from leaking, a storage capacitor unit 5 is added in parallel with a liquid crystal capacitor formed between the pixel electrode 1 and the counter electrode. In the present embodiment, the storage capacitor section 5 is a storage capacitor having a MOS structure. Reference numeral 6 denotes an MO that forms a storage capacity.
This is a capacitance line corresponding to the gate line of the S transistor. Due to this storage capacitance, the voltage of the pixel electrode 1 is held for a time three orders of magnitude longer than the time during which the source voltage is applied. Thereby, the holding characteristics are further improved, and a liquid crystal device having a high contrast ratio can be realized.

As shown in FIG. 2, a plurality of transparent conductive films such as indium tin oxide (hereinafter abbreviated as ITO) are formed on a TFT array substrate 7 which is one of the substrates of the liquid crystal device. Are arranged in a matrix, and data lines 3 (contours are shown by two-dot chain lines) are provided along the sides of the pixel electrodes 1 extending in the vertical direction on the paper surface. The scanning lines 4 and the capacitance lines 6 (both are indicated by solid lines) are provided along the sides extending in the horizontal direction. In the present embodiment, the semiconductor layer 8 made of a polysilicon film (the outline is shown by a dashed line) is formed in a U-shape near the intersection of the data line 3 and the scanning line 4, and the U-shaped portion 8a Is extended in the direction of the adjacent data line 3 (rightward on the paper) and in the direction along the data line 3 (upward on the paper). U-shaped portion 8 of semiconductor layer 8
Contact holes 9 and 10 are formed at both ends of a. One contact hole 9 serves as a source contact hole for electrically connecting the data line 3 and the source region of the semiconductor layer 8, and the other contact hole 10 serves as a source contact hole. The drain contact hole electrically connects the drain electrode 11 (the outline is indicated by a two-dot chain line) and the drain region of the semiconductor layer 8. A pixel contact hole 12 for electrically connecting the drain electrode 11 and the pixel electrode 1 is formed at an end of the drain electrode 11 opposite to the side where the drain contact hole 10 is provided.

The TFT 2 in the present embodiment is an n-channel TFT, in which the U-shaped portion 8a of the semiconductor layer 8 intersects the scanning line 4, and the semiconductor layer 8 intersects the scanning line 4 twice. , A TFT having two gates on one semiconductor layer, a so-called dual gate type TF
T. The capacitance line 6 extends along the scanning line 4 so as to penetrate the pixels arranged in the horizontal direction on the paper, and a branched part 6a extends along the data line 3 in the vertical direction on the paper. Therefore, the storage capacitor section 5 is formed by the semiconductor layer 8 and the capacitor line 6 that both extend long along the data line 3.

In the present embodiment, the storage capacitor 5 has an n-channel MOS structure, and is provided in the semiconductor layer 8 (channel region) of the storage capacitor 5 which overlaps the capacitor line 6 in a plane. The original threshold voltage is 2 V due to the doping of phosphorus, which is an impurity ion for adjusting the value voltage.
A depletion type MOS transistor whose level is changed to about -5V is formed.

As shown in FIG. 3, the liquid crystal device of the present embodiment has a pair of transparent substrates 13 and 14, one of which is a TFT array substrate 7 and the other is opposed to the TFT array substrate 7. And a counter substrate 15 serving as the other substrate. A liquid crystal 16 is sandwiched between the substrates 7 and 15. The transparent substrates 13 and 14 are made of, for example, a glass substrate or a quartz substrate.

In the TFT section shown on the left side of FIG.
A base insulating film 17 is provided on the FT array substrate 7, and a semiconductor layer 8 made of, for example, a polysilicon film having a thickness of about 50 nm is provided on the base insulating film 17. An insulating thin film 18 serving as a gate insulating film of about 150 nm is formed on the entire surface. A TFT for controlling switching of each pixel electrode 1 is provided on the base insulating film 17.
The TFT 2 is provided with a scanning line 4 made of a metal such as tantalum, a channel region 19 of the semiconductor layer 8 in which a channel is formed by an electric field from the scanning line 4, and an insulation between the scanning line 4 and the semiconductor layer 8. Insulating thin film 1 forming gate insulating film
8, a data line 3 made of a metal such as aluminum, a source region 20 and a drain region 21 of the semiconductor layer 8.

On the TFT array substrate 7 including the scanning line 4 and the insulating thin film 18, a source contact hole 9 leading to a source region 20 and a drain contact hole 10 leading to a drain region 21 (shown in FIG. 3). 1) is formed on each of the first interlayer insulating films 22. That is, the data line 3 is electrically connected to the source region 20 via the source contact hole 9 penetrating the first interlayer insulating film 22.

Further, as shown on the right side of FIG. 3, a drain electrode 11 made of metal of the same layer as the data line 3 is formed on the first interlayer insulating film 22.
A second interlayer insulating film 23 in which the pixel contact hole 12 leading to the contact hole 12 is formed. That is, the drain region 21 is electrically connected to the pixel electrode 1 via the drain electrode 11. Although not shown in the cross section of FIG. 3, the drain region 21 of the semiconductor layer 8 and the drain electrode 11
Are electrically connected via the drain contact hole 10 formed in the first interlayer insulating film 22.

In the storage capacitor section 5 shown on the right side of FIG. 3, a base insulating film 17 is provided on the TFT array substrate 7, and phosphorus is doped on the base insulating film 17 integrally with the semiconductor layer 8 of the TFT 2. A semiconductor layer 8 is provided, and an insulating thin film 18 (dielectric film) is formed on the entire surface so as to cover the semiconductor layer 8. On the insulating thin film 18, the capacitance line 6 made of metal on the same layer as the scanning line 4 is formed.
A first interlayer insulating film 22 is formed on the entire surface so as to cover. The drain electrode 11 is formed on the first interlayer insulating film 22. Then, a pixel contact hole 12 penetrating through the second interlayer insulating film 23 and reaching the surface of the drain electrode 11 is provided, and a transparent conductive film such as ITO electrically connected to the drain electrode 11 at the pixel contact hole 12 portion. Pixel electrode 1 is provided. The second interlayer insulating film 23 is used as a flattening film. For example, an acrylic film, which is a kind of resin film having high flatness, has a thickness of 2.
It is formed to a thickness of about μm.

On the other hand, a first light-shielding film 24 (black matrix) made of, for example, a metal film such as chromium, a resin black resist or the like is formed on the counter substrate 15 in a grid pattern.
Color filter layers 25 corresponding to the three primary colors R (red), G (green), and B (blue) are formed between the first light-shielding films 24. An overcoat film 26 is formed so as to cover the color filter layer 25. On the overcoat film 26,
Like the pixel electrode 1, a counter electrode 27 made of a transparent conductive film such as ITO is formed on the entire surface. Note that both the TFT array substrate 7 and the opposing substrate 15 are provided with alignment films 28 and 29 made of polyimide or the like on the surfaces in contact with the liquid crystal 16.

In the liquid crystal device of the present embodiment, the MOS transistor forming the storage capacitor section 5 is a depletion type MOS transistor, and the threshold voltage of the MOS transistor is equal to that of the original MOS transistor before being converted to the depletion type. It changes from the threshold voltage of about 2V to about -5V. Therefore, a desired storage capacitor can be formed without making the MOS transistor before converting the potential of the capacitor line 6 into a depletion type as high as the storage capacitor.

As a result, the voltage effectively applied to the insulating thin film 18 interposed between the semiconductor layer 8 and the capacitance line 6 can be reduced as compared with the conventional MOS type storage capacitor. 18, it is possible to reduce the probability of occurrence of insulation failure due to defects or the like, and to improve the product yield. In addition, since the deterioration with time of the insulating thin film 18 is reduced by lowering the effective applied voltage to the insulating thin film, the reliability can be improved.

[Manufacturing Process of Liquid Crystal Device] Next, a manufacturing process of the liquid crystal device having the above configuration will be described with reference to FIG. FIG. 4 is a process cross-sectional view particularly showing a manufacturing process of the TFT array substrate 7. First, as shown in step (1) of FIG. 4, a base insulating film 17 is formed on a transparent substrate 13 such as a glass substrate, and an amorphous silicon layer is stacked thereon. Thereafter, the amorphous silicon layer is recrystallized by subjecting the amorphous silicon layer to a heat treatment such as a laser annealing process, for example, to form a crystalline polysilicon layer 30 having a thickness of, for example, about 50 nm.

Next, as shown in step (2) of FIG. 4, the formed polysilicon layer 30 is patterned so as to have the pattern of the semiconductor layer 8 described above, and a film thickness of, for example, about 50 to 150 nm is formed thereon. An insulating thin film 18 serving as a gate insulating film is formed. Next, as shown in step (3) of FIG. 4, a resist pattern 31 is formed to cover the portion other than the portion of the semiconductor layer 8 of the storage capacitor portion 5 that will become the channel region, and the MOS transistor of the storage capacitor portion 5 is depleted. To this end, phosphorus ( ^49P ) is ion-implanted into the channel region of the semiconductor layer 8 of the storage capacitor unit 5 through the insulating thin film 18. The ion implantation conditions at this time include the original MO of the storage capacitor 5.
Assuming that the threshold voltage of the S transistor is changed from 2V to -5V, the ion dose required to change the threshold voltage by 1V is about 2.5 × 10 ¹¹ ions / cm ² , The dose may be about 2 × 10 ¹² ions / cm ² . The acceleration energy may be about 50 to 80 keV.

Alternatively, before forming the insulating thin film 18 on the semiconductor layer 8, for example, phosphorus ions may be directly implanted into the semiconductor layer 8 at about 10 to 30 keV.

Next, after removing the resist pattern 31,
As shown in step (4) of FIG.
The scanning line 4 and the capacitance line 6 of T2 are formed. The formation of the scanning lines 4 and the like is performed, for example, by forming a resist pattern of the scanning lines 4 and the like, sputtering or vacuum depositing a metal such as tantalum, and then removing the resist pattern. Then, after forming the scanning line 4 and the capacitance line 6, a resist pattern 32 covering the storage capacitance portion 5 is formed, and then PH ₃ / H ₂ ions are implanted. The ion implantation conditions at this time are, for example, an ion dose of ³¹ P of 5 × 10 ¹⁴ to 5 × 10 ¹⁴ .
It is about 7 × 10 ¹⁴ ions / cm ² and the acceleration energy is 80
It is about keV. Through the above step (4), the source region 20 and the drain region 21 of the TFT 2 are formed.

Next, after removing the resist pattern 32,
As shown in step (5) of FIG. 4, the first interlayer insulating film 22 is laminated, and then the positions to become the source contact hole 9 and the drain contact hole 10 are opened, and the shapes of the data line 3 and the drain electrode 11 are changed. After forming a resist pattern to be formed, the data line 3 and the drain electrode 11 are formed by sputtering or depositing a metal such as aluminum.

Thereafter, a second interlayer insulating film 23 is laminated, a position to be the pixel contact hole 12 is opened, and a transparent conductive thin film of ITO or the like having a film thickness of about 50 to 200 nm is formed in a predetermined region thereon. The pixel electrode 1 is formed. Finally, an alignment film is formed on the entire surface. Through the above steps, the TFT array substrate 7 of the present embodiment is completed.

On the other hand, for the counter substrate 15 shown in FIG. 3, a process diagram is omitted, but a transparent substrate 14 such as a glass substrate is first prepared, and a first light shielding film 24 and a second light shielding The film (see FIG. 5) is formed through, for example, a photolithography process and an etching process after sputtering metal chromium. These light-shielding films may be formed of a material such as resin black in which carbon or Ti is dispersed in a photoresist, in addition to a metal material such as Cr (chromium), Ni (nickel), or Al (aluminum).

Thereafter, after a color filter layer 25 and an overcoat film 26 are sequentially formed, a transparent conductive thin film of ITO or the like is deposited on the entire surface of the counter substrate 15 by sputtering or the like to a thickness of about 50 to 200 nm. The counter electrode 27 is formed. Further, an alignment film 29 is formed on the entire surface of the counter electrode 27.

Finally, the T on which each layer is formed as described above
The FT array substrate 7 and the opposing substrate 15 are arranged so as to face each other, and are bonded to each other with a sealing material so that the cell thickness becomes, for example, about 4 μm, thereby producing an empty panel. Then, the liquid crystal 1
If liquid crystal device 6 is sealed in an empty panel, the liquid crystal device of the present embodiment is manufactured.

According to the method of manufacturing the liquid crystal device of the present embodiment, although the ion implantation step for depleting the MOS transistor of the storage capacitor section 5 is increased by one step, the ion for adjusting the threshold voltage is increased. Since the dose of the implantation is not so large, on the order of 10 ¹¹ to 10 ¹² ions / cm ² , there is no problem such as deterioration of the resist at the time of the ion implantation, and the implantation time can be as short as ten and several seconds. There is no adverse effect of the implementation.

[Overall Configuration of Liquid Crystal Device] Next, the liquid crystal device 4
0 will be described with reference to FIG. In FIG. 5, a sealing material 34 is provided on the TFT array substrate 7 along its edge, and a second light-shielding film 35 as a frame is provided in parallel with the inside of the sealing material 34. Seal material 3
The data line drive circuit 36 and the external circuit connection terminal 37 are provided along one side of the TFT array substrate 7 in the area outside the scan line 4, and the scanning line drive circuit 38 is provided along two sides adjacent to this one side. Is provided. If the delay of the scanning signal supplied to the scanning line 4 does not matter, it goes without saying that the scanning line driving circuit 38 may be provided on only one side. Further, the data line driving circuits 36 may be arranged on both sides along the side of the image display area. For example, the odd-numbered data lines 3 supply an image signal from a data line driving circuit disposed along one side of the image display area, and the even-numbered data lines 3 are provided on the opposite side of the image display area. The image signal may be supplied from a data line driving circuit disposed along the line.
When the data lines 3 are driven in a comb-tooth shape in this manner, the area occupied by the data line driving circuit can be expanded, so that a complicated circuit can be formed. Further, on the remaining one side of the TFT array substrate 7, a plurality of wirings 39 for connecting between the scanning line driving circuits 38 provided on both sides of the image display area are provided. In addition, the counter substrate 1
A conductive material 41 for providing electrical continuity between the TFT array substrate 7 and the opposing substrate 15 is provided at at least one of the corners of the No. 5. The opposite substrate 15 having substantially the same contour as the sealing material 34 is fixed to the TFT array substrate 7 by the sealing material 34.

[Electronic Equipment] Hereinafter, specific examples of electronic equipment having the liquid crystal device of the present invention will be described. FIG. 6 is a perspective view showing an example of a mobile phone. In FIG. 6, reference numeral 1000 denotes a mobile phone main body, and reference numeral 1001 denotes a liquid crystal display unit using the above liquid crystal device.

FIG. 7 is a perspective view showing an example of a wristwatch type electronic device. 7, reference numeral 1100 denotes a watch main body, and reference numeral 1101 denotes a liquid crystal display unit using the above-described liquid crystal device.

FIG. 8 is a perspective view showing an example of a portable information processing device such as a word processor or a personal computer. 8, reference numeral 1200 denotes an information processing device, reference numeral 1202 denotes an input unit such as a keyboard, reference numeral 1204 denotes an information processing device main body, and reference numeral 1206 denotes a liquid crystal display unit using the above liquid crystal device.

Since the electronic devices shown in FIGS. 6 to 8 are provided with a liquid crystal display using the above-described liquid crystal device, it is possible to realize an electronic device having excellent reliability.

The technical scope of the present invention is not limited to the above embodiment, and various changes can be made without departing from the spirit of the present invention. For example, in the above embodiment, TF as a switching element
Although T is an n-channel type and a MOS transistor forming a storage capacitor is an n-channel type, any of these conductivity types may be used. In addition, materials of various films constituting the liquid crystal device,
The specific description of the film thickness, dimensions, manufacturing conditions, and the like is not limited to the above embodiment, and the design can be appropriately changed.

[0052]

As described above in detail, according to the present invention, the voltage effectively applied to the insulating film interposed between the semiconductor layer and the capacitor line in the storage capacitor portion is reduced by the conventional M
Since the storage capacity can be reduced as compared with the case of the OS-type storage capacitor, the probability of occurrence of insulation failure due to a defect or the like in the insulation film can be reduced, and the yield of products can be improved. In addition, the reduction in effective applied voltage to the insulating film reduces deterioration with time of the insulating film, so that reliability can be improved.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of a liquid crystal device according to an embodiment of the present invention.

FIG. 2 is an enlarged plan view showing a pixel configuration of the liquid crystal device.

FIG. 3 is a sectional view taken along lines AA ′ and BB ′ in FIG. 2;

FIG. 4 is a process cross-sectional view showing a manufacturing process of the liquid crystal device.

FIG. 5 is a plan view showing the entire configuration of the liquid crystal device.

FIG. 6 is a perspective view illustrating an example of an electronic apparatus including the liquid crystal device of the present invention.

FIG. 7 is a perspective view illustrating another example of the electronic apparatus.

FIG. 8 is a perspective view showing still another example of the electronic apparatus.

FIGS. 9A and 9B are diagrams showing the relationship between the waveform of an image signal and the potential of a capacitor line in a MOS storage capacitor, respectively showing (a) a conventional storage capacitor and (b) a MOS storage capacitor; .

10A and 10B are diagrams showing CV characteristics in a MOS storage capacitor, wherein FIG. 10A shows a normal MOS transistor, and FIG.
The cases of depleted MOS transistors are shown.

FIG. 11 is a diagram illustrating a configuration example of a conventional pixel using a MOS-type capacitor as a storage capacitor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Pixel electrode 2 Thin film transistor (TFT) 3 Data line 4 Scan line 5 Storage capacity part 6 Capacity line 7 TFT array substrate 8 Semiconductor layer 15 Counter substrate 16 Liquid crystal 18 Insulating thin film (dielectric film)

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/336 (72) Inventor Shoichi Takanabe 2-3-2 Marunouchi 2-chome, Chiyoda-ku, Tokyo Mitsubishi Electric Corporation F-term (for reference) 2H092 HA04 JA25 JA46 JB63 JB66 KA04 KB15 MA27 MA30 NA16 NA29 5C094 AA24 AA31 AA42 BA03 BA43 CA19 EA04 EA05 EB02 5F038 AC05 AC14 AC17 AV06 DF01 EZ13 EZ20 5F110 AA02 BB01 CC04 HL03 HL22 HL23 NN02 NN03 NN27 NN73 PP03

Claims (9)

[Claims] A plurality of scanning lines and a plurality of data lines provided intersecting each other on one of the pair of substrates, wherein the plurality of scanning lines and the plurality of data lines are interposed between the pair of substrates facing each other; A liquid crystal device having a plurality of pixel electrodes arranged in a matrix corresponding to intersections of scanning lines and the data lines, a plurality of thin film transistors which are switching elements of the pixel electrodes, and a plurality of MOS storage capacitors. Wherein the MOS transistor forming the MOS storage capacitor is a depression type MOS transistor. 2. The depletion type MOS transistor is formed by introducing an impurity for lowering a threshold voltage of the MOS transistor into at least a channel region of the MOS transistor forming the MOS type storage capacitor. The liquid crystal device according to claim 1. 3. The depletion type MOS transistor is an original MOS transistor before conversion into a depletion type.
3. The liquid crystal device according to claim 1, wherein the depletion is performed from the polarity of the threshold voltage of the transistor to the threshold voltage of the opposite polarity. 4. A voltage applied to a conductor layer corresponding to a gate electrode of the depletion type MOS transistor is set within a range of a pulse amplitude of an image signal in the liquid crystal device. Item 4. The liquid crystal device according to item 3. 5. The depletion type MOS transistor is formed so as to be integrated with a semiconductor layer constituting the thin film transistor and has a channel region of the MOS transistor and at least partially overlaps the semiconductor layer. 5. The liquid crystal device according to claim 1, comprising a capacitance line serving as a gate electrode of a MOS transistor, and a dielectric film interposed between the semiconductor layer and the capacitance line. 6. A liquid crystal is sandwiched between a pair of substrates facing each other, and a plurality of scanning lines and a plurality of data lines provided on one of the pair of substrates so as to intersect each other. Manufacturing of a liquid crystal device having a plurality of pixel electrodes arranged in a matrix corresponding to the intersection of a scanning line and the data line, a plurality of thin film transistors serving as switching elements of the pixel electrodes, and a plurality of MOS storage capacitors A method for implanting impurity ions for lowering a threshold voltage of the MOS transistor into at least a channel region of a semiconductor layer forming the MOS transistor forming the MOS storage capacitor, the method comprising: A method of manufacturing a liquid crystal device, comprising: depleting a MOS transistor forming the MOS storage capacitor by a process. 7. The method for manufacturing a liquid crystal device according to claim 6, wherein the implantation of the impurity ions into the semiconductor layer is performed before forming a dielectric film covering the semiconductor layer. 8. The liquid crystal device according to claim 6, wherein the implantation of the impurity ions into the semiconductor layer is performed via the dielectric film after forming a dielectric film covering the semiconductor layer. Production method. 9. An electronic apparatus comprising the liquid crystal device according to claim 1.