JP2001520812A - 組合されたプログラム可能論理アレーとアレー論理 - Google Patents

組合されたプログラム可能論理アレーとアレー論理

Info

Publication number
JP2001520812A
JP2001520812A JP51155396A JP51155396A JP2001520812A JP 2001520812 A JP2001520812 A JP 2001520812A JP 51155396 A JP51155396 A JP 51155396A JP 51155396 A JP51155396 A JP 51155396A JP 2001520812 A JP2001520812 A JP 2001520812A
Authority
JP
Japan
Prior art keywords
array
programmable
input
output
pld
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP51155396A
Other languages
English (en)
Japanese (ja)
Inventor
ロナルド リー クライン
Original Assignee
フィリップス エレクトロニクス ネムローゼ フェンノートシャップ
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by フィリップス エレクトロニクス ネムローゼ フェンノートシャップ filed Critical フィリップス エレクトロニクス ネムローゼ フェンノートシャップ
Publication of JP2001520812A publication Critical patent/JP2001520812A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP51155396A 1994-09-26 1995-08-30 組合されたプログラム可能論理アレーとアレー論理 Pending JP2001520812A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US31179394A 1994-09-26 1994-09-26
US08/311,793 1994-09-26
PCT/IB1995/000716 WO1996010295A1 (en) 1994-09-26 1995-08-30 Combined programmable logic array and array logic

Publications (1)

Publication Number Publication Date
JP2001520812A true JP2001520812A (ja) 2001-10-30

Family

ID=23208500

Family Applications (1)

Application Number Title Priority Date Filing Date
JP51155396A Pending JP2001520812A (ja) 1994-09-26 1995-08-30 組合されたプログラム可能論理アレーとアレー論理

Country Status (7)

Country Link
US (1) US5714890A (enExample)
EP (1) EP0733285B1 (enExample)
JP (1) JP2001520812A (enExample)
KR (1) KR960706227A (enExample)
DE (1) DE69513278T2 (enExample)
TW (1) TW311302B (enExample)
WO (1) WO1996010295A1 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5684413A (en) * 1996-03-28 1997-11-04 Philips Electronics North America Corp. Condensed single block PLA plus PAL architecture
US5824748A (en) * 1996-06-03 1998-10-20 Minnesota Mining And Manufacturing Company Composite pressure sensitive adhesive microspheres
US6066959A (en) * 1997-12-09 2000-05-23 Intel Corporation Logic array having multi-level logic planes
US6259273B1 (en) 1999-06-15 2001-07-10 Ict Acquisition Corp. Programmable logic device with mixed mode programmable logic array
US6369609B1 (en) 2000-05-08 2002-04-09 Cypress Semiconductor Corp. Degenerate network for PLD and plane
US6687864B1 (en) 2000-06-08 2004-02-03 Cypress Semiconductor Corp. Macro-cell flip-flop with scan-in input
US6353331B1 (en) 2000-07-10 2002-03-05 Xilinx, Inc. Complex programmable logic device with lookup table
JP6393513B2 (ja) * 2014-04-30 2018-09-19 パナソニック デバイスＳｕｎｘ株式会社 プログラマブルコントローラ及びプログラム開発支援装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4124899A (en) * 1977-05-23 1978-11-07 Monolithic Memories, Inc. Programmable array logic circuit
US4336468A (en) * 1979-11-15 1982-06-22 The Regents Of The University Of California Simplified combinational logic circuits and method of designing same
US4422072A (en) * 1981-07-30 1983-12-20 Signetics Corporation Field programmable logic array circuit
US4758746A (en) * 1985-08-12 1988-07-19 Monolithic Memories, Inc. Programmable logic array with added array of gates and added output routing flexibility
US4703206A (en) * 1985-11-19 1987-10-27 Signetics Corporation Field-programmable logic device with programmable foldback to control number of logic levels
US4942319A (en) * 1989-01-19 1990-07-17 National Semiconductor Corp. Multiple page programmable logic architecture
US5260610A (en) * 1991-09-03 1993-11-09 Altera Corporation Programmable logic element interconnections for programmable logic array integrated circuits
US5189320A (en) * 1991-09-23 1993-02-23 Atmel Corporation Programmable logic device with multiple shared logic arrays
US5235221A (en) * 1992-04-08 1993-08-10 Micron Technology, Inc. Field programmable logic array with speed optimized architecture

Also Published As

Publication number Publication date
DE69513278D1 (de) 1999-12-16
DE69513278T2 (de) 2000-05-11
TW311302B (enExample) 1997-07-21
US5714890A (en) 1998-02-03
EP0733285B1 (en) 1999-11-10
KR960706227A (ko) 1996-11-08
WO1996010295A1 (en) 1996-04-04
EP0733285A1 (en) 1996-09-25

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