JP2001516089A5 - - Google Patents

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Publication number
JP2001516089A5
JP2001516089A5 JP2000510102A JP2000510102A JP2001516089A5 JP 2001516089 A5 JP2001516089 A5 JP 2001516089A5 JP 2000510102 A JP2000510102 A JP 2000510102A JP 2000510102 A JP2000510102 A JP 2000510102A JP 2001516089 A5 JP2001516089 A5 JP 2001516089A5
Authority
JP
Japan
Prior art keywords
signal
attribute
memory
memory attribute
linear
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000510102A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001516089A (ja
JP4312952B2 (ja
Filing date
Publication date
Priority claimed from US08/914,578 external-priority patent/US5946713A/en
Application filed filed Critical
Publication of JP2001516089A publication Critical patent/JP2001516089A/ja
Publication of JP2001516089A5 publication Critical patent/JP2001516089A5/ja
Application granted granted Critical
Publication of JP4312952B2 publication Critical patent/JP4312952B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP2000510102A 1997-08-18 1998-07-21 メモリ属性パレット Expired - Fee Related JP4312952B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/914,578 1997-08-18
US08/914,578 US5946713A (en) 1997-08-18 1997-08-18 Memory attribute palette
PCT/US1998/015054 WO1999009510A2 (en) 1997-08-18 1998-07-21 Memory attribute palette

Publications (3)

Publication Number Publication Date
JP2001516089A JP2001516089A (ja) 2001-09-25
JP2001516089A5 true JP2001516089A5 (enExample) 2006-01-05
JP4312952B2 JP4312952B2 (ja) 2009-08-12

Family

ID=25434537

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000510102A Expired - Fee Related JP4312952B2 (ja) 1997-08-18 1998-07-21 メモリ属性パレット

Country Status (10)

Country Link
US (1) US5946713A (enExample)
JP (1) JP4312952B2 (enExample)
KR (1) KR100358601B1 (enExample)
CN (1) CN1149484C (enExample)
AU (1) AU8577298A (enExample)
BR (1) BR9811952B1 (enExample)
DE (1) DE19882617B4 (enExample)
GB (1) GB2343275B (enExample)
TW (1) TW501010B (enExample)
WO (1) WO1999009510A2 (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6694418B2 (en) * 2001-03-30 2004-02-17 Intel Corporation Memory hole modification and mixed technique arrangements for maximizing cacheable memory space
US6681311B2 (en) * 2001-07-18 2004-01-20 Ip-First, Llc Translation lookaside buffer that caches memory type information
KR100633144B1 (ko) 2004-11-09 2006-10-11 삼성전자주식회사 색 관리방법 및 이를 적용한 색 관리장치
JP4783163B2 (ja) * 2006-01-19 2011-09-28 Ｏｋｉセミコンダクタ株式会社 マイクロコントローラ
US7949834B2 (en) * 2007-01-24 2011-05-24 Qualcomm Incorporated Method and apparatus for setting cache policies in a processor
US8103816B2 (en) * 2008-10-28 2012-01-24 Intel Corporation Technique for communicating interrupts in a computer system
US9331855B2 (en) 2011-07-01 2016-05-03 Intel Corporation Apparatus, system, and method for providing attribute identity control associated with a processor
US20130111181A1 (en) * 2011-10-31 2013-05-02 Lsi Corporation Methods and apparatus for increasing device access performance in data processing systems
US11513779B2 (en) 2020-03-19 2022-11-29 Oracle International Corporation Modeling foreign functions using executable references
US11875168B2 (en) 2020-03-19 2024-01-16 Oracle International Corporation Optimizing execution of foreign method handles on a virtual machine
US11543976B2 (en) * 2020-04-01 2023-01-03 Oracle International Corporation Methods for reducing unsafe memory access when interacting with native libraries

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5668949A (en) * 1993-11-12 1997-09-16 Intel Corporation System utilizing multiple address decode resources and decoder receiving address determines address corresponding to resource based on select and ready signals by that particular resource
US5590289A (en) * 1993-11-12 1996-12-31 Intel Corporation Method and apparatus for initializing a computer system having central and distributed address decode memory bus resources
US5561814A (en) * 1993-12-22 1996-10-01 Intel Corporation Methods and apparatus for determining memory operating characteristics for given memory locations via assigned address ranges
US5819079A (en) * 1995-09-11 1998-10-06 Intel Corporation Instruction fetch on demand for uncacheable memory which avoids memory mapped I/O side effects in a processor with speculative instruction fetch

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