JP2001509291A - 多重プロセッサシステムにおけるプロセッサメンバーシップの分散形取り決め - Google Patents
多重プロセッサシステムにおけるプロセッサメンバーシップの分散形取り決めInfo
- Publication number
- JP2001509291A JP2001509291A JP53214598A JP53214598A JP2001509291A JP 2001509291 A JP2001509291 A JP 2001509291A JP 53214598 A JP53214598 A JP 53214598A JP 53214598 A JP53214598 A JP 53214598A JP 2001509291 A JP2001509291 A JP 2001509291A
- Authority
- JP
- Japan
- Prior art keywords
- processor
- processors
- stage
- multiprocessor system
- message
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
- G06F11/0724—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU] in a multiprocessor or a multi-core unit
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/142—Reconfiguring to eliminate the error
- G06F11/1425—Reconfiguring to eliminate the error by reconfiguration of node membership
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Hardware Redundancy (AREA)
- Multi Processors (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.複数のプロセッサを有している多重プロセッサシステムにおいて、各前記複 数のプロセッサは、それぞれメモリを有しており、前記多重プロセッサシステム におけるプロセッサメンバーシップに分散的に同意する方法であって、 前記複数のプロセッサを通信的に接続し; 次いで通信故障を検出し; 次いで前記複数のプロセッサのいずれがまだ動作しておりかつまだ通信的 に接続されているかをまだ動作している該複数のプロセッサのそれぞれで第1に 決定することを試みて、前記多重プロセッサシステムの前記各プロセッサのそれ ぞれのビューを決定し; 次いでまだ動作している前記各プロセッサが動作を継続するか又は動作を 停止するかをまだ動作している前記各プロセッサで第2に決定し、前記第2の決 定は、前記多重プロセッサシステムの前記各プロセッサのそれぞれのビューに基 づくものであり; 次いで前記第2の決定により前記各プロセッサの動作を継続又は停止し; 前記複数のプロセッサの第1のプロセッサの連結性情報を収集し;かつ 次いで収集した前記連結性情報に基づいて、動作を打ち切るべく前記複数 のプロセッサのあるものを前記第1のプロセッサで選択する段階を具備すること を特徴とする方法。 2.複数のプロセッサを有している多重プロセッサシステムにおいて、各前記複 数のプロセッサは、それぞれメモリを有しており、前記多重プロセッサシステム におけるプロセッサメンバーシップに分散的に同意する方法であって、 前記複数のプロセッサを通信的に接続し; 次いで通信故障を検出し; 次いで前記複数のプロセッサのいずれがまだ動作しておりかつまだ通信的 に接続されているかをまだ動作している該複数のプロセッサのそれぞれで第1に 決定することを試みて、前記各プロセッサを第1から第2のステージへのそれぞれ の進行を含んでいる方法の対象とし、前記各プロセッサを前記第1のステー ジに最初に配置することを含んでいる、前記多重プロセッサシステムの前記各プ ロセッサのそれぞれのビューを決定し; 次いで前記複数のプロセッサの一つのプロセッサの進行の状態を送り; 前記一つのプロセッサの前記進行の状態を前記複数のプロセッサの第2の プロセッサで受け取り; 前記受け取りの後、時間満了の通知が前記第2のプロセッサで発生したな らば当該第2のプロセッサの状態を更新し; その状態が更新された各プロセッサを前記第2のステージにそれぞれ進行 させ; 前記第2のプロセッサが前記第1のステージから進行することに失敗した場 合にタイマの時間満了が前記第2のプロセッサで故障したことそれゆえに前記第2 のプロセッサが動作することを効果的に打ち切ったことを決定し;かつ 次いでまだ動作している前記各プロセッサが動作を継続するか又は動作を 停止するかをまだ動作している前記各プロセッサで第2に決定し、前記第2の決 定は、前記多重プロセッサシステムの前記各プロセッサのそれぞれのビューに基 づくものであり; 次いで前記第2の決定により前記各プロセッサにおける動作を継続又は停 止する段階を具備することを特徴とする方法。 3.複数のプロセッサを有している多重プロセッサシステムにおいて、各前記複 数のプロセッサは、それぞれメモリを有しており、前記多重プロセッサシステム におけるプロセッサメンバーシップに分散的に同意する方法であって、 前記複数のプロセッサを通信的に接続し; 前記複数のプロセッサのそれぞれを第1から第2のステージへのそれぞれの 進行を含んでいる方法の対象とし、前記各プロセッサを前記第1のステージに最 初に配置し; 前記複数のプロセッサの第1のプロセッサの進行の状態を送り; 前記第1のプロセッサの前記進行の状態を前記複数のプロセッサの第2のプ ロセッサで受け取り; 前記受け取りの後、時間満了の通知が前記第2のプロセッサで発生したな らば当該第2のプロセッサの状態を更新し; その状態が更新された各プロセッサを前記第2のステージにそれぞれ進行 させ; 前記第2のプロセッサが前記第1のステージから進行することに失敗した場 合に連結性情報を送ることを失敗しかつ前記第2のプロセッサが動作することを 効果的に打ち切ったことを決定し; 前記複数のプロセッサの第3のプロセッサの連結性情報を収集し;かつ 収集した前記連結性情報に基づいて、動作を打ち切るべく前記複数のプロ セッサのあるものを前記第3のプロセッサで選択する段階を具備することを特徴 とする方法。 4.複数のプロセッサを有している多重プロセッサシステムにおいて、各前記複 数のプロセッサは、それぞれメモリを有しており、前記多重プロセッサシステム におけるプロセッサメンバーシップに分散的に同意する方法であって、 前記複数のプロセッサを通信的に接続し; 次いで通信故障を検出し; 次いで前記複数のプロセッサのいずれがまだ動作しておりかつまだ通信的 に接続されているかをまだ動作している該複数のプロセッサのそれぞれで第1に 決定することを試みて、前記各プロセッサを第1から第2のステージへのそれぞれ の進行を含んでいる方法の対象とすること、前記各プロセッサを前記第1のステ ージに最初に配置することを含んでいる、前記多重プロセッサシステムの前記各 プロセッサのそれぞれのビューを決定し、; 次いで前記複数のプロセッサの一つのプロセッサの進行の状態を送り; 前記一つのプロセッサの前記進行の状態を前記複数のプロセッサの第2の プロセッサで受け取り; 前記受け取りの後、時間満了の通知が前記第2のプロセッサで発生したな らば当該第2のプロセッサの状態を更新し; その状態が更新された各プロセッサを前記第2のステージにそれぞれ進行 させ; 前記第2のプロセッサが前記第1のステージから進行することに失敗した 場合にタイマの時間満了が前記第2のプロセッサで故障したことそれゆえに前記 第2のプロセッサが動作することを効果的に打ち切ったことを決定し;かつ 次いでまだ動作している前記各プロセッサが動作を継続するか又は動作を 停止するかをまだ動作している前記各プロセッサで第2に決定し、前記第2の決 定は、前記多重プロセッサシステムの前記各プロセッサのそれぞれのビューに基 づくものであり; 次いで前記第2の決定により前記各プロセッサにおける動作を継続又は停 止し; 前記複数のプロセッサの第3のプロセッサの連結性情報を収集し;かつ 収集した前記連結性情報に基づいて、動作を打ち切るべく前記複数のプロ セッサのあるものを前記第3のプロセッサで選択する段階を具備することを特徴 とする方法。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/790,030 US6002851A (en) | 1997-01-28 | 1997-01-28 | Method and apparatus for node pruning a multi-processor system for maximal, full connection during recovery |
US08/790,269 US5991518A (en) | 1997-01-28 | 1997-01-28 | Method and apparatus for split-brain avoidance in a multi-processor system |
US08/789,257 US5884018A (en) | 1997-01-28 | 1997-01-28 | Method and apparatus for distributed agreement on processor membership in a multi-processor system |
US08/789,257 | 1997-01-28 | ||
PCT/US1998/001311 WO1998033120A1 (en) | 1997-01-28 | 1998-01-23 | Distributed agreement on processor membership in a multi-processor system |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2001509291A true JP2001509291A (ja) | 2001-07-10 |
JP2001509291A5 JP2001509291A5 (ja) | 2005-09-08 |
Family
ID=25149431
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP53217098A Ceased JP2001511922A (ja) | 1997-01-28 | 1998-01-22 | 多重プロセッサシステムにおけるスプリット−ブレイン防止のための方法及び装置 |
JP53214598A Ceased JP2001509291A (ja) | 1997-01-28 | 1998-01-23 | 多重プロセッサシステムにおけるプロセッサメンバーシップの分散形取り決め |
JP53476398A Ceased JP2001511278A (ja) | 1997-01-28 | 1998-01-27 | 回復中に最大限の全接続に対しマルチプロセッサシステムをノード剪定する方法及び装置 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP53217098A Ceased JP2001511922A (ja) | 1997-01-28 | 1998-01-22 | 多重プロセッサシステムにおけるスプリット−ブレイン防止のための方法及び装置 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP53476398A Ceased JP2001511278A (ja) | 1997-01-28 | 1998-01-27 | 回復中に最大限の全接続に対しマルチプロセッサシステムをノード剪定する方法及び装置 |
Country Status (5)
Country | Link |
---|---|
US (3) | US5991518A (ja) |
EP (3) | EP1012717A4 (ja) |
JP (3) | JP2001511922A (ja) |
CA (3) | CA2279175A1 (ja) |
WO (3) | WO1998033121A1 (ja) |
Cited By (2)
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JP2019214353A (ja) * | 2018-06-08 | 2019-12-19 | 住友電装株式会社 | 通信装置及び制御方法 |
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JP2019214353A (ja) * | 2018-06-08 | 2019-12-19 | 住友電装株式会社 | 通信装置及び制御方法 |
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JP2001511922A (ja) | 2001-08-14 |
EP0954783A1 (en) | 1999-11-10 |
CA2275241A1 (en) | 1998-07-30 |
WO1998034457A3 (en) | 1998-11-19 |
CA2279175A1 (en) | 1998-07-30 |
EP0954783A4 (en) | 2005-10-26 |
EP1012728A4 (en) | 2005-07-20 |
EP1012728A2 (en) | 2000-06-28 |
EP1012717A4 (en) | 2005-07-06 |
US5884018A (en) | 1999-03-16 |
CA2279185A1 (en) | 1998-08-13 |
US5991518A (en) | 1999-11-23 |
EP1012717A1 (en) | 2000-06-28 |
WO1998034457A2 (en) | 1998-08-13 |
US6002851A (en) | 1999-12-14 |
WO1998033120A1 (en) | 1998-07-30 |
JP2001511278A (ja) | 2001-08-07 |
WO1998033121A1 (en) | 1998-07-30 |
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