JP2001358580A - Apparatus and method for regenerating period timing - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an apparatus and a method for regenerating period timing in which the phase of regeneration period timing can be followed up immediately for phase variation of receiving period timing through combination of easy-to- design small scale circuits. SOLUTION: Regeneration period timing is initialized depending on the time difference between the input time of receiving period timing and the generation time of regeneration period timing. More specifically, generation of the regeneration period timing at period T0, decision of the time difference between generated regeneration period timing and receiving period timing, and initialization of generation of the regeneration period timing depending on the decision results are combined.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in a communication system for transmitting a periodic signal during a period in which no data signal is communicated, and in particular, for removing jitter of a periodic signal caused by irregularity in a period in which a data signal is not communicated. The present invention relates to a technique for complementing a periodic signal lost due to a code error during transmission or a transmission line failure.

[0002]

2. Description of the Related Art FIG. 21 shows a conventional PLL (Phase Locked).
This is an example of a periodic timing reproduction device realized by the (Loop) technique. The periodic timing reproducing apparatus realized by the conventional technique includes a phase comparing section 30, a low frequency pass filter section 31, and a frequency variable control type oscillating section 32. The phase comparator 30 compares the phase of the reception cycle timing with the phase of the reproduction cycle timing, and outputs a phase comparison signal that is a signal corresponding to the phase difference. The low-frequency pass filter unit 31 passes only the low-frequency component of the phase comparison signal and outputs it as a frequency control signal. The variable frequency control type oscillating section 32 generates a reproduction cycle timing. Also,
The frequency of the reproduction cycle timing is changed according to the frequency control signal. Each part is required to be constituted by an analog circuit which is easily affected by noise from the surroundings and requires accuracy of components constituting each part, or an operation corresponding to the analog circuit is a complicated and large-scale digital circuit.

[0003]

The period timing reproducing apparatus realized by the prior art generally has a receiving period timing and a reproduction period timing by gradually changing the oscillation frequency of the frequency variable control type oscillator 32. The operation for reducing the phase difference between the two is performed. As a result, the phase of the reproduction cycle timing cannot immediately follow the phase fluctuation of the reception cycle timing. The low-frequency pass filter unit 31 can improve the response speed by passing the normally blocked high-frequency components, but cannot remove the jitter of the reception cycle timing. Therefore, the reproduction apparatus of the periodic timing realized by the conventional technique cannot be used when a high-speed response to the phase fluctuation of the reproduction cycle timing is required.

As described above, the conventional technique requires an analog circuit which is easily affected by noise and is difficult to design, or a complicated and large-scale digital circuit in order to realize a periodic timing reproducing apparatus. There was a problem that the design and manufacturing costs of the device were high. Further, when it is necessary to immediately follow the phase of the reproduction cycle timing with respect to the phase fluctuation of the reception cycle timing, this cannot be applied.

SUMMARY OF THE INVENTION The present invention has been made in such a background, and a combination of small-scale and easily designed circuits allows the phase of the reproduction cycle timing to immediately follow the phase fluctuation of the reception cycle timing. It is an object of the present invention to provide a periodic timing reproducing apparatus and method capable of removing the influence of jitter, which is possible.

[0006]

SUMMARY OF THE INVENTION A periodic timing reproducing apparatus of the present invention initializes a reproduction cycle timing in accordance with a time difference between an input time of a reception cycle timing and a generation time of the reproduction cycle timing. That is, it is realized by a combination of generation of the reproduction cycle timing in the cycle T0, determination of the time difference between the generated reproduction cycle timing and reception cycle timing, and initialization of generation of the reproduction cycle timing according to the determination result.

[0007] Each of these can be realized by a small-scale and easily designed digital circuit. In addition, it is possible to determine, based on the time difference between the reproduction cycle timing and the generation time, whether the phase fluctuation is caused by jitter or the original phase fluctuation that requires a high-speed response. Therefore, when it is determined from the time difference between the reproduction cycle timing and the generation time of the reproduction cycle timing that the phase fluctuation is an original phase, the generation of the reproduction cycle timing is initialized, thereby removing the jitter of the reception cycle timing and reducing the phase fluctuation. High-speed response can be achieved at the same time.

That is, a first aspect of the present invention is to reproduce the reception cycle timing of the input cycle Ti to obtain the cycle T0.
Is a cycle timing reproducing apparatus provided with a timing reproducing means for outputting as the reproduction cycle timing.

Here, the feature of the present invention is that the input time ti of the reception cycle timing of the cycle Ti and the cycle T0
Time difference (ti) from the output time t0 of the reproduction cycle timing
−t0) is divided into a plurality of possible value ranges,
The correction value of the reproduction cycle timing is set for each of the plurality of regions, and the timing reproduction unit includes: a unit for specifying the region including the value of the time difference; and the correction set for the specified region. Means for correcting the reproduction cycle timing in accordance with the value.

Thus, the phase of the reproduction cycle timing can immediately follow the phase fluctuation of the reception cycle timing by a combination of circuits that are small and easily designed.

An area where the correction value is “0” (no correction is performed) is provided in a part of the plurality of areas, and the value of the time difference corresponding to the jitter of the reception cycle timing is included in the area. It is desirable to be set so that.

As described above, when the value of the time difference caused by the phase fluctuation due to the jitter or the like always becomes almost constant, the value of the phase fluctuation due to the jitter or the like which is to be excluded from the correction target is set to the value. With respect to the included region, this can be a region where the correction value is “0” and a region where no correction is performed. As a result, unnecessary correction operation can be avoided, and efficient period timing reproduction can be performed.

Means for measuring the time during which the value of the time difference is continuously included in the same area, and means for instructing the correcting means to start the execution of the correction in accordance with the length of the measured time Can also.

In this manner, unnecessary correction or erroneous correction is avoided by performing correction when the value of the time difference keeps taking the same value for a predetermined time without performing correction immediately. You can also.

[0015] A second aspect of the present invention is that a computer device having predetermined hardware and predetermined basic software installed on the hardware is further installed on the computer device so that the computer device according to the present invention can be used in accordance with the present invention. This is a recording medium on which software is recorded as a device corresponding to the timing reproducing device.

A third aspect of the present invention is that the input period T
This is a period timing reproducing method of reproducing the reception period timing of i and outputting it as the reproduction period timing of period T0.

Here, the feature of the present invention is that the input time ti of the reception period timing of the period Ti and the period T0
Time difference (ti) from the output time t0 of the reproduction cycle timing
-T0) is divided into a plurality of regions, the correction value of the reproduction cycle timing is set for each of the plurality of regions, and the region including the value of the time difference is specified and specified. The reproduction cycle timing is to be corrected according to the correction value set in the specified area.

A region where the correction value is "0" is provided in a part of the plurality of regions, and the region is set so that the time difference corresponding to the jitter of the reception cycle timing is included in the region. desirable.

It is also possible to measure the time during which the value of the time difference is continuously included in the same area, and instruct the start of the correction according to the length of the measured time.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A periodic timing reproducing apparatus according to an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram of a periodic timing reproducing apparatus according to an embodiment of the present invention.

The present invention, as shown in FIG. 1, is a periodic timing reproducing apparatus provided with a periodic timing reproducing section 1 for reproducing the input receiving cycle timing of the period Ti and outputting it as the reproducing cycle timing of the period T0. .

Here, the feature of the present invention is that the input time ti of the reception period timing of the period Ti and the period T0
Time difference (ti) from the output time t0 of the reproduction cycle timing
−t0) is divided into a plurality of possible value ranges,
A correction value of the reproduction cycle timing is set for each of the plurality of areas, and the cycle timing reproduction unit 1 includes a clock 2 with a reset function provided for specifying the area including the value of the time difference. The reproduction cycle timing is corrected according to the correction value set in the specified area.

A continuation range in which the correction value is a region of “0” is provided in a part of the plurality of regions, and the value of the time difference corresponding to the jitter of the reception cycle timing is included in the continuation range. It is set as follows.

Further, as shown in FIG. 11, there is provided a protection stage number counter 16 for measuring a time during which the value of the time difference is continuously included in the same area, and a period timing reproducing unit according to the length of the measured time. 1 can be instructed to start the execution of the correction.

By further installing the computer in a computer having predetermined hardware and predetermined basic software installed in the hardware, the computer becomes a device corresponding to the periodic timing reproducing device of the present invention. By installing the software in a computer device using a recording medium on which the software is recorded, the periodic timing reproducing device of the present invention is realized. Hereinafter, embodiments of the present invention will be described in more detail.

(First Embodiment) FIGS. 1 to 3 show the first embodiment of the present invention.
This will be described with reference to FIG. FIG. 2 is a flowchart for explaining the operation of the first embodiment. FIG. 3 is a time chart for explaining the operation of the first embodiment. The periodic timing reproducing device according to the first embodiment includes a clock 2 with a reset function and a periodic timing reproducing unit 1. The clock 2 with a reset function measures and outputs the time from the last reset. Periodic timing reproduction unit 1
Operates the reset and time reading of the timepiece 2 with the reset function according to the flowchart shown in FIG. 2 to reproduce the reception cycle timing and output it as the reproduction cycle timing. FIG. 3 is an example of a time chart of the reception cycle timing and the reproduction cycle timing when operated according to the flowchart shown in FIG. 3 indicates that ti-t0 is in the continuation range.

The flowchart shown in FIG. 2 will be described. First, when the present apparatus is started, it starts from and resets the clock 2 with a reset function and outputs the reproduction cycle timing. Thereafter, the reproduction cycle timing is output in the cycle T0 until the reception cycle timing is input. Note that the period of the reception cycle timing is Ti, and it is desirable that T0 and Ti match in order to reproduce the reception cycle timing. However, in this case, when the time Ti is measured by the clock 2 with the reset function, an error occurs. , T0 is described as a period in which an error is allowed.

When the reception cycle timing is input, the time ti is read from the clock 2 with the reset function. Next, the time (ti-t0) from the time t0 at which the reproduction cycle timing was generated and output immediately before that is set to the initialization range #
It is determined whether or not 1 to #M applies. Since the clock 2 with the reset function is reset at the same time as generating and outputting the reproduction cycle timing, the clock 2 with the reset function is reset.
The time ti read from is equal to the time (ti-t0).

When the time (ti-t0) falls within the initialization range #j, the timer 2 with the reset function is reset after waiting for a predetermined time dj from the input of the reception cycle timing. If the time (ti-t0) does not correspond to any of the initialization ranges # 1 to #M, the time (t
It is determined that (i-t0) falls within the continuation range, and the reproduction cycle timing is continuously output at the cycle T0 until the next reception cycle timing is input. As described above, the present invention can be implemented with a simple device configuration and flow.

In FIG. 3, the time (ti-t0) falls within a predetermined initialization range # 1 after the reproduction cycle timing of the period T0 is continuously generated and output because the time (ti-t0) falls within the continuation range. An example of a time chart of the initialization # 1 in which the reproduction cycle timing of the cycle T0 is continuously generated and output with reference to the time (ti + d1) because it corresponds. The continuation range and the initialization range are not necessarily one continuous range. The continuation range in this embodiment is
As shown in FIG. 3, it is composed of two ranges.

If the coincidence between the reception cycle timing cycle Ti and the reproduction cycle timing cycle T0 is guaranteed, it is necessary to set the number M of initialization ranges to 1 or more. For example, when the time (ti-t0) falls within the initialization range # 1, it is determined that the original phase fluctuation has occurred.

If the coincidence between the reception cycle timing Ti and the reproduction cycle timing T0 is not guaranteed, and
When Ti ≦ T0 or Ti ≧ T0 is guaranteed, it is necessary to set the number M of initialization ranges to 2 or more. For example, when (ti-t0) falls within the initialization range # 1, the reception cycle timing Ti and the reproduction cycle timing T0
It is determined that a phase variation has occurred due to the difference between
If (0) becomes the initialization range # 2, it is determined that the original phase fluctuation has occurred.

Further, if the coincidence between Ti and T0 is not guaranteed, and if the magnitude relationship between Ti and T0 is not guaranteed, the number M of initialization ranges must be 3 or more. For example, when (ti-t0) becomes the initialization range # 1 or the initialization range # 2, the reception cycle timing Ti
It is determined that a phase change has occurred due to the difference between the timing and the reproduction cycle timing T0, and when (ti-t0) falls within the initialization range # 3, it is determined that the original phase change has occurred.

(Second Embodiment) The second embodiment of the present invention is shown in FIGS.
This will be described with reference to FIG. FIG. 4 is a block diagram of the periodic timing reproducing apparatus according to the second embodiment. FIG. 5 is a diagram illustrating a configuration example of the counter unit according to the second embodiment. FIG. 6 is a diagram illustrating a configuration example of the time difference determination unit according to the second embodiment. FIG.
Is a time chart showing the operation when the time difference is in the continuation range. FIG. 8 is a time chart showing the operation when the time difference is in the initialization range # 1. FIG. 9 is a time chart showing the operation when the time difference is in the initialization range # 2. FIG. 10 is a time chart showing the operation when the time difference is in the initialization range # 3.

In the second embodiment, the reception cycle timing Ti
And the reproduction cycle timing T0, Ti and T0
Is not guaranteed and the magnitude relationship between Ti and T0 is not guaranteed, and the number M of initialization ranges is set to 3.

As shown in FIG. 4, the cycle timing reproducing apparatus of the second embodiment comprises a clock generator 15, a counter 1
4, a counter initialization unit 12, a timing generation unit 13, and a time difference determination unit 11.

The clock generator 15 generates N clocks at time T0. The counter unit 14 counts the clock and outputs a count value from 0 to N-1.
If one clock is input when indicating the count value of N-1, the count value returns to 0. The counter initialization unit 12 receives the determination signals # 1 to # 3 and outputs an initialization signal to the counter unit 14. The counter value of the counter unit 14 is initialized to an initial value # 1 indicated by the initialization signal by input of the initialization signal. After the initialization to the initial value # 1, 1 + 1, 1+
The count value increases as 2,. Timing generator 1
3 receives the counter value and outputs a reproduction cycle timing and determination signals # 1 to # 3. If the reception cycle timing is input to the apparatus when the determination signal #j is H, (ti-t0) corresponds to the initialization range. This determination is made in the time difference determination unit 11, and the result is output as determination signals # 1 to # 3.

FIG. 5 shows an example of the configuration of the counter section 14, where n
(N = 2 ⁿ ) clear & preset T-FFs. By performing a predetermined input to the clear / preset terminal of each T-FF, the counter unit 14 can be initialized to a predetermined counter value.

FIG. 6 shows an example of the configuration of the time difference judging section 11. The determination signals # 1 to # 3 are generated by ANDing the reception cycle timing and the determination signals # 1 to # 3. As described above, the counter unit 14, the timing generation unit 13, and the time difference determination unit 11 can be realized by a simple circuit configuration. In addition, the timing generation unit 13 also determines the reproduction cycle timing and the determination signals # 1 to # 3 from the counter value.
Since only one signal is generated, it can be realized with a simple circuit configuration. The counter initialization unit 12 can also be realized with a small number of inverters. The clock generator 15 uses an oscillator having a frequency of N / T0. Thus, the present invention can be implemented with a simple device configuration.

FIG. 7 is a time chart of each signal when (ti-t0) is in the continuation range (which does not correspond to any of the initialization ranges # 1 to # 3). (1) of FIG. 7 indicates that “the time difference determination unit 11 determines that the signal does not correspond to any of the initialization ranges # 1 to # 3 and does not output the determination signals # 1 to # 3”, and (2) of FIG. Is "the counter initialization unit 12 does not output an initialization signal", and (3) of FIG.
4 is not initialized (operation is continued), and (4) of FIG. 7 shows each state of "continuously outputting the reproduction cycle timing at the cycle T0 because the counter unit 14 is not initialized". FIG. 8 is a time chart of each signal when it corresponds to the initialization range # 1. (1) of FIG. 8 indicates that “the time difference determination unit 11 determines that ti−t0 is in the initialization range # 1 because the reception cycle timing is input when the determination signal # 1 is H, and the determination signal 8 (2) of FIG. 8 shows that “the counter initialization unit 12 receives the determination signal # 1 and
An initialization signal is output for initializing the counter value of the counter unit 14 to A + α (initialization # 1) ”, and (3) of FIG. 8 illustrates that“ in the counter unit 14, the counter value is A + α.
8 (4), “the output of the determination signal # 1 changes due to the initialization of the counter unit 14”, and FIG. ti
+ D1 to output the reproduction cycle timing (if not initialized, output at time t0 + T0) ". FIG. 9 is a time chart of each signal when (ti-t0) corresponds to the initialization range # 2. FIG. 9 (1)
"Since the reception cycle timing is input when the determination signal # 2 is H in the time difference determination unit 11, ti-t
0 is within the initialization range # 2, and outputs the determination signal # 2. "(2) of FIG. 9 shows that" the counter initialization unit 12 receives the determination signal # 2, 9 is output to initialize to B-α (initialization # 2) ”, and (3) in FIG. 9 is“ the counter value is initialized to B-α in the counter unit 14 ”, FIG. (4) “the output of the determination signal # 2 changes due to the initialization of the counter unit 14”, and (5) of FIG. 9 “outputs the reproduction cycle timing at time ti + d2 due to the initialization of the counter unit 14 ( (If not initialized, it is output at time t0 + T0). " FIG. 10 is a time chart of each signal when (ti-t0) corresponds to the initialization range # 3. (1) of FIG. 10 indicates that “the time difference determination unit 11 determines that ti−t0 is in the initialization range # 3 because the reception cycle timing is input when the determination signal # 3 is H, and the determination signal Output # 3 ”and (2) of FIG. 10 show that“ the counter initialization unit 12 receives the determination signal # 3,
Outputs Initialization Signal for Initializing Counter Value of Counter Unit 14 to (A + B) / 2 (Initialization # 3), FIG.
(3) of 0 is "the counter value is initialized to (A + B) / 2 in the counter unit 14", and (4) of FIG. 10 is "the output of the determination signal # 3 is changed by the initialization of the counter unit 14". (5) in FIG. 10 indicates that “the reproduction cycle timing is output at time ti + d3 due to the initialization of the counter unit 14 (if not initialized, it is output at time t0 + T0”).
Each state is shown.

If (ti-t0) is in the continuation range,
The counter section is not initialized, and continuously outputs the reproduction cycle timing of the cycle T0. This state corresponds to the case where there is a phase change only due to the jitter of the reception cycle timing. By setting the continuation range to be larger than the time width of the jitter, the counter unit 14 is not initialized due to a small phase fluctuation caused by the jitter. Therefore, the reproduction cycle timing is not affected by the jitter of the reception cycle timing, Output at T0. This makes it possible to remove jitter.

When (ti-t0) is in the initialization range # 1, the counter unit 14 is initialized # 1. This state mainly occurs when Ti <T0. in this case,
The phase of the reproduction cycle timing is changed to correct the difference between Ti and T0. The case where (ti-t0) is in the initialization range # 2 mainly occurs when Ti> T0. Also in this case, the phase of the reproduction cycle timing is changed to correct the difference between Ti and T0. The state where (ti-t0) is in the initialization range # 3 is caused not by the jitter or the period difference but by the original phase fluctuation at the reception period timing. In this case, the phase of the reproduction cycle timing is changed so that the phase of the reproduction cycle timing immediately follows the phase fluctuation of the reception cycle timing. As described above, in the cycle timing reproducing apparatus to which the present invention is applied, it is possible to achieve both the removal of the jitter of the reception cycle timing and the high-speed response to the phase fluctuation.

(Third Embodiment) A periodic timing reproducing apparatus according to a third embodiment of the present invention will be described with reference to FIGS. FIG. 11 is a diagram illustrating a configuration example of a time difference determination unit according to the third embodiment. FIG. 12 is a time chart for explaining the operation of the periodic timing reproduction device of the third embodiment. (1) of FIG. 12 indicates that “in the time difference determination unit 11, the receiving cycle timing is input when the determination signal # 3 is H four times in a row, so that the determination signal # 3 is output”. 2) indicates that the counter initialization unit 12 determines that the determination signal #
3 outputs an initialization signal for initialization # 3 ", and (3) of FIG. 12 shows states of" implementation of initialization # 3 in counter unit 14 ".

In the initialization of the counter section 14 of the second embodiment, there is a possibility that an erroneous initialization of the reproduction cycle timing is performed due to an erroneous reception cycle timing input.
Therefore, in order to prevent such a problem from occurring, a protection function is provided in the third embodiment.

FIG. 11 shows an example of the configuration of the time difference judging section 11. The other device configuration is the same as that of the second embodiment. The difference from the time difference determination unit 11 of the second embodiment is that the initialization range # 3
Is that a circuit for performing four-stage protection is added to the above. FIG. 12 shows a time chart of the initialization range # 3 at this time. When (ti-t0) becomes the initialization range # 3 four times in a row, the initialization # 3 is performed.

(Fourth Embodiment) FIG. 13 shows a fourth embodiment of the present invention.
This will be described with reference to FIGS. FIG. 13 is an overall configuration diagram of a communication system to which the fourth embodiment is applied. In the fourth embodiment, as shown in FIG. 13, an example is shown in which the periodic timing reproducing apparatus of the present invention is applied to a communication system having a communication path from a transmitting node to a receiving node via one or more relay nodes. . The data signal is transmitted from the transmitting node to the receiving node through this communication path.

Further, the transmitting node transmits one periodic signal in each period of the period T to the receiving node through the communication channel during a period in which the data signal is not transmitted. Each relay node receives the periodic signal, reproduces the periodic signal reception cycle timing as a reproduction cycle timing, and, in accordance with the reproduction cycle timing, transmits a periodic signal during which a data signal is not transmitted during a period in which the periodic signal can be transmitted. The signal is transmitted to the receiving node via the communication path. The receiving node
Receive a periodic signal.

FIG. 14 shows a configuration example of the relay node. The relay node includes the periodic signal reading unit 17 and the periodic signal writing unit 1
8, a periodic signal processing unit 20, and a periodic timing reproducing device 19. The periodic signal reading unit 17 reads a periodic signal included in the received signal of the relay node, outputs a received cycle timing and a read signal, deletes the periodic signal from the received signal, and outputs the signal as a relay signal. The periodic signal writing unit 18 writes the periodic signal to the relay signal in accordance with the reproduction cycle timing. The periodic signal processing unit 20 processes various information (such as control information used for managing the communication system) included in the read periodic signal, and generates a periodic signal to be transmitted to the next-stage relay node. The periodic timing reproducing device 19 is the periodic timing reproducing device shown in the second embodiment.

FIG. 15 shows an example of a time chart of the reception signal of the relay node, the relay signal reproduction cycle timing, and the transmission signal. The relay signal is a signal in which the periodic signal is deleted from the received signal, and after the reproduction cycle timing is output, the periodic signal is written during a period in which the data signal is interrupted from the relay signal.

FIG. 16 shows a method of generating the determination signals # 1 to # 3 and the reproduction cycle timing performed by the cycle timing device. FIG. 17 is an example of a time chart illustrating the operation of the periodic timing reproduction device. As described above, the periodic timing reproducing apparatus to which the present invention is applied reproduces a periodic signal at a relay node of the communication system (complements a periodic signal that has been lost due to a code error during transmission or a transmission line failure) and has a temporal A function of removing temporal fluctuation (jitter) from the reception timing of a periodic signal having fluctuation is realized.

(Fifth Embodiment) FIG. 18 shows a fifth embodiment of the present invention.
This will be described with reference to FIG. The fifth embodiment is an example in which the communication system of the fourth embodiment is modified to communicate a control signal together with a periodic signal. In this communication system, like the periodic signal, the control signal is transmitted during a period in which the data signal is not periodically transmitted. FIG. 18 illustrates a configuration example of a relay node. FIG. 19 shows an example of a time chart of the sub signal in the relay node. A write-inhibition period for the control signal is provided in case the periodic signal disappears. By doing so, when the periodic signal is lost,
It is possible to determine to which cycle the control signal belongs. It is also possible to communicate a plurality of periodic signals during one cycle without providing a write prohibition period, thereby preventing the signals from being lost. FIG.
0 is an example of a time chart showing the operation of the periodic timing reproduction device.

[0052]

As described above, according to the present invention,
The periodic timing reproducing apparatus can be realized only by a small-scale and easily designed digital circuit. Also,
Based on the time difference between the reproduction cycle timing and the generation time, it is determined whether the phase fluctuation is caused by jitter or the original phase fluctuation that requires a high-speed response. When it is determined that the phase variation occurs, the generation of the reproduction cycle timing can be initialized.

Thus, the combination of small-scale and easy-to-design circuits can remove the jitter of the reception cycle timing and immediately follow the phase of the reproduction cycle timing with respect to the phase fluctuation of the reception cycle timing. A periodic timing reproducing apparatus and method capable of eliminating the influence can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram of a periodic timing reproducing apparatus according to a first embodiment of the present invention.

FIG. 2 is a flowchart for explaining the operation of the first embodiment of the present invention.

FIG. 3 is a time chart for explaining the operation of the first embodiment of the present invention.

FIG. 4 is a block diagram of a periodic timing reproducing apparatus according to a second embodiment of the present invention.

FIG. 5 is a diagram illustrating a configuration example of a counter unit according to a second embodiment of the present invention.

FIG. 6 is a diagram illustrating a configuration example of a time difference determination unit according to a second embodiment of the present invention.

FIG. 7 is a time chart showing the operation of the second embodiment of the present invention when the time difference is within the continuation range.

FIG. 8 is a time chart showing the operation of the second embodiment of the present invention when the time difference is within the initialization range # 1.

FIG. 9 is a time chart showing an operation of the second embodiment of the present invention when the time difference is within the initialization range # 2.

FIG. 10 shows that the time difference of the second embodiment of the present invention is the initialization range # 3.
4 is a time chart showing the operation when the operation is performed.

FIG. 11 is a diagram illustrating a configuration example of a time difference determination unit according to a third embodiment of the present invention.

FIG. 12 is a time chart for explaining the operation of the periodic timing reproduction device according to the third embodiment of the present invention.

FIG. 13 is an overall configuration diagram of a communication system to which a fourth embodiment of the present invention is applied.

FIG. 14 is a diagram illustrating a configuration example of a relay node according to a fourth embodiment of the present invention;

FIG. 15 shows a reception signal of the relay node according to the fourth embodiment of the present invention,
The figure which shows the example of a relay signal reproduction | regeneration period timing and the time chart of a transmission signal.

FIG. 16 is a diagram showing a method of generating determination signals # 1 to # 3 and a reproduction cycle timing performed by the cycle timing device according to the fourth embodiment of the present invention.

FIG. 17 is a diagram showing a time chart illustrating an operation of the periodic timing reproducing apparatus according to the fourth embodiment of the present invention.

FIG. 18 is a diagram illustrating a configuration example of a relay node according to a fifth embodiment of the present invention.

FIG. 19 is a diagram showing an example of a time chart of a sub signal in a relay node according to the fifth embodiment of the present invention.

FIG. 20 is a time chart showing the operation of the periodic timing reproduction device according to the fifth embodiment of the present invention.

FIG. 21 is a block diagram of a periodic timing reproducing apparatus realized by a conventional PLL technology.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Periodic timing reproduction part 2 Clock with reset function 11 Time difference judgment part 12 Counter initialization part 13 Timing generation part 14 Counter part 15 Clock generation part 16 Protection stage number counter 17 Periodic signal reading part 18 Periodic signal writing part 19 Periodic timing reproduction device 20 Periodic signal processing unit 21 Periodic signal / control signal reading unit 22 Periodic signal / control signal writing unit 23 Periodic signal / control signal processing unit 30 Phase comparison unit 31 Low frequency pass filter unit 32 Frequency variable control type oscillation unit

 ────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Haruhiko Ichino 2-3-1 Otemachi, Chiyoda-ku, Tokyo F-term within Nippon Telegraph and Telephone Corporation (reference) 5J106 AA04 BB02 CC15 DD17 DD43 DD48 GG13 HH09 KK03 KK25 KK38 5K047 AA02 AA13 AA16 BB15 GG11 MM53 MM56

Claims (7)

[Claims] 1. A cycle timing reproducing apparatus comprising a timing reproducing means for reproducing an input receiving cycle timing of a cycle Ti and outputting it as a reproducing cycle timing of a cycle T0, wherein an input time ti of the receiving cycle timing of the cycle Ti and Period T
0 and the time difference (t
i-t0) is divided into a plurality of regions, a correction value of the reproduction cycle timing is set for each of the plurality of regions, and the timing reproduction unit includes the value of the time difference. A cycle timing reproducing apparatus comprising: means for specifying an area; and means for correcting the reproduction cycle timing according to the correction value set for the specified area. 2. A region in which the correction value is “0” (no correction is performed) is provided in a part of the plurality of regions, and a value of the time difference corresponding to the jitter of the reception cycle timing is set in the region. The cycle timing reproducing device according to claim 1, wherein the periodic timing reproducing device is set so as to be included. 3. A means for measuring a time during which the value of the time difference is continuously included in the same area; and a means for instructing the means for correcting to start the execution of the correction in accordance with the length of the measured time. Claim 1 provided
The periodic timing reproduction device according to the above. 4. The computer device according to claim 1, wherein said computer device is further installed on a computer device having predetermined hardware and predetermined basic software installed on said hardware. A recording medium on which software is recorded which is a device corresponding to the periodic timing reproducing device. 5. A cycle timing reproducing method for regenerating an input reception cycle timing of a cycle Ti and outputting it as a reproduction cycle timing of a cycle T0, wherein the input time ti and the cycle T of the reception cycle timing of the cycle Ti are
0 and the time difference (t
(i-t0) is divided into a plurality of regions, a correction value of the reproduction cycle timing is set for each of the plurality of regions, and the region including the time difference value is specified. A cycle timing reproduction method, wherein the reproduction cycle timing is corrected according to the correction value set in a specified area. 6. A region where the correction value is “0” (no correction is performed) is provided in a part of the plurality of regions, and the value of the time difference corresponding to the jitter of the reception cycle timing is the region. 6. The periodic timing reproducing method according to claim 5, wherein the method is set so as to be included in the following. 7. The periodic timing reproducing method according to claim 5, wherein a time during which the value of the time difference is continuously included in the same area is measured, and the execution of the correction is instructed according to the length of the measured time.