JPH08249830A - Disk medium recording/reproducing method and clock signal generating device - Google Patents

Abstract

PURPOSE: To generate such reference clocks with simple control, in which the frequencies for reproducing the data are different for every track of a disk medium. CONSTITUTION: The repetitive pattern of the frequency corresponding to the reference clock signal of the digital data stored in the track is recorded on each track of the disk medium. A regenerative signal 61 regenerating the pattern is fetched to a counter 66 only for a section of a gate pulse 78 generated by a window generator 68 to be counted. A decoder 81 forms the frequency division value setting data 82 based on the count value, and a frequency synthesizer 29 forms the signal 30 of the frequency added or subtracted to/from a voltage control oscillator of a PLL circuit 64 based on the data 82 to supply it to a mixing circuit 88. The output of the PLL circuit 64 becomes the reference clock signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for recording / reproducing predetermined information to / from a disk medium such as an optical disk for setting the frequency of a reference clock signal for reproducing digital data, and a method for reproducing the recorded information. The present invention relates to a clock signal generator for reproducing a reference clock signal based on the above, and more specifically, a disk medium recording / reproducing method and a clock for generating a reference clock signal synchronized with reproduction data having different frequencies in each track of the disk medium. The present invention relates to a signal generator.

[0002]

2. Description of the Related Art The CAV system and the CLV system exist as basic systems for digitally recording on a disk medium. In the former CAV method, the disc is rotated at a constant angular velocity, and recording is performed with a constant reference clock signal on any track of the disc. On the other hand, in the latter CLV method, rotation control is performed so as to maintain a constant linear velocity, and recording is performed with a constant reference clock signal in this state. Therefore, the former CAV
The method is excellent in high-speed accessibility, and the latter CLV method has an advantage that the recording density can be increased as much as the recording density becomes uniform.

On the other hand, the CWL-CAV system is a system in which the reference clock frequency of digital data is changed according to the radius of each track so that the wavelength per bit on the disk becomes equal. . The CWL-CAV system is an excellent system that simultaneously realizes the high-speed accessibility of the CAV system and the recording density of the CLV system. In the CWL-CAV method, since the reference clock frequency changes, a PLL circuit is usually used as a reproduction reference clock signal generation circuit for reproducing a signal.

FIG. 4 shows such a reproduction reference clock signal generating PLL circuit disclosed in, for example, Japanese Patent Laid-Open No. 2-158966. A reproduction data signal 12 picked up from a reproduction head (not shown) and amplified by a reproduction amplifier (not shown) is input to the reproduction equalizer 11 of this circuit. The reproduction equalizer 11 improves the pulse characteristics of the reproduction data signal 12 and supplies its output to the AGC circuit 13. The AGC circuit 13 removes the low frequency part of the amplitude fluctuation. This output is input to both the A / D converter 14 and the comparator 15.

Of these, the A / D converter 14 quantizes the analog level input / output to obtain quantized data. This quantized data is input to the discriminator 16 and restored to the original recording digital data. This digital data is input to the reproduction signal processing unit 17. The reproduced signal processor 17 is actually composed of a plurality of circuits. Then, the input digital data is decoded and reproduced signal processing such as error correction is performed. The reproduced signal processing unit 17 reconstructs this signal into a format suitable for the user of the apparatus and outputs it to a circuit portion in the subsequent stage (not shown) in order to provide the signal for the user of the apparatus.

By the way, the A / D converter 14 and the discriminator 16
The reference clock signal 18 synchronized with the data is supplied from the buffer 19 to the reproduction signal processing section 17. The generation path of the reference clock signal 18 will be described next.

The signal supplied from the AGC circuit 13 to the comparator 15 is compared with a predetermined reference level (not shown) and binarized, and then the output signal is output from the PLL circuit section 21.
It is input to one input terminal of the phase comparator 22 inside. P
The LL circuit unit 21 includes the phase comparator 22, an error amplifier 23 that amplifies an error signal as a comparison result, a low-pass filter 24 that passes a low frequency component of the output of the error amplifier, and an output of the low-pass filter 24. A voltage controlled oscillator (VCO) 25 that emits at a frequency based on the voltage,
The bandpass filter 27 receives the transmitted output through the mixer 26 and passes a predetermined band component. The output of the band pass filter 27 is the phase comparator 2
2 and the buffer 19
To be sent.

The mixer 26 is supplied with a signal 30 of a predetermined frequency output from the frequency synthesizer 29. The decoding result 33 is supplied to the frequency synthesizer 29 from the decoder 32 which decodes the track address 31 of the disc, and the signal 30 having the frequency corresponding to this is generated.

In such a conventional PLL circuit for generating the reproduction reference clock signal, the sum component or the difference component of the voltage controlled oscillator 25 and the frequency synthesizer 29 is extracted through the band pass filter 27 in the PLL circuit section 21, and the phase comparator is obtained. 22. As a result, control is performed so that the sum or difference becomes equal to the reference clock frequency of the reproduction signal.

In the CWL-CAV system, the reference clock frequency changes over a wide range. Therefore, if the entire range of the clock frequency is covered by the variable range of the voltage controlled oscillator 25, even if a small amount of noise occurs, a large fluctuation of the reference clock signal will be caused, and it will take time to restore the original frequency. Or the output of the recording / reproducing apparatus is greatly disturbed while the reference clock frequency is fluctuating.

Therefore, this reproduction reference clock generating PL is used.
In the L circuit, the variable range of the voltage controlled oscillator 25 is limited, and the sum or difference with the stable frequency of the frequency synthesizer 29 is taken to synchronize this signal with the reproduced signal. That is, the obtained summed or subtracted signal 34 is passed through the buffer 19 to A /
The reference clock signal 18 is distributed to the D converter 14, the discriminator 16, and the reproduction signal processing unit 17.

FIG. 5 specifically shows the configuration of the frequency synthesizer shown in FIG. The frequency synthesizer 29 is composed of a stable oscillator such as a crystal oscillator, and is a reference frequency oscillator 41 that oscillates a reference frequency.
And a phase comparator 42 for inputting the reference frequency to be output to one of the input terminals, an error amplifier 45 for inputting the result of comparison between the reference frequency by the phase comparator 42 and the output of the programmable counter 44, and this error Amplifier 4
Low-pass filter 4 that passes the low-frequency component of the output of 5
6 and a voltage-controlled oscillator 47 that outputs a frequency corresponding to the output voltage of the low-pass filter 46, and the signal 30 of a predetermined frequency as the oscillation output of the voltage-controlled oscillator 47 is input to the programmable counter 44. The frequency is divided according to the control data input 48.

The output of the programmable counter 44 is compared by the phase comparator 42, and the frequency is controlled according to this value. That is, the oscillation output of the voltage controlled oscillator 47 is controlled to have a frequency N times the output of the reference frequency oscillator 41 when the frequency division ratio of the programmable counter 44 is “N”.

The reference clock frequency at the time of reproducing the disk uniquely corresponds to the position of the reproducing track. Therefore, in the past, in order to control the frequency division value of the programmable counter 44, one obtained by converting the position information of the track to be reproduced was used as the control data input 48. Examples of such items include a track address number and a decoded value thereof.

By the way, the track address number is originally used for controlling the head position for data access, and is required to have high accuracy and reliability. Therefore, a sync signal and a CRCC code, which is a kind of error detection code, are added to the address number of this track, and a process such as multiple writing is performed to make a majority decision and recording is performed. ing. Therefore,
Certain conversion operations are required to obtain such a control data input 48.

FIG. 6 shows a circuit portion for obtaining the control data input used in FIG. The reproduction signal 51 including the address of the corresponding track reproduced from the disc is input to the comparator 52, and compared with a predetermined reference level to be binarized. The output of the comparator 52 is input to the synchronization detection circuit 53, and the timing reference marker for synchronization detection is detected. Sync detection circuit 53
Is output to the error detection circuit 54, and the CRC
Inspection of C is performed. The output of the error detection circuit 54 is input to the discriminator 55, where the address number of the track is decoded. The decoded address is input to the next address calculator 56, and the address of the track to be accessed next is calculated. The calculated address is input to the decoder 57 and decoded to obtain the control data input 48 for supplying to the programmable counter 44 shown in FIG.

[0017]

As described above, in the conventional clock signal generator for reproducing the reference clock signal, the position information of the track used for the highly accurate and highly reliable detection system is shared. ing. Therefore, it takes time to detect necessary information.
Further, in the case of random access, the address number of the access destination track is required, not the track address number itself. Therefore, even when performing continuous reproduction, it is necessary to supply the address of the track at the next reproduction position in advance. As described above, it is necessary to supply the address number of the corresponding track through the control of the system of the apparatus according to the access condition, and there is a problem that the control system becomes complicated and large-scaled.

Therefore, it is an object of the present invention to make it possible to generate these reference clock signals by simple control even when the frequency of the reference clock signal for data reproduction differs for each track of the disc medium. A recording / reproducing method and a clock signal generator are provided.

[0019]

According to a first aspect of the present invention, in a reading area in front of the digital data recording area of each track of a disk medium for recording digital data for each track, A repetitive pattern of a frequency corresponding to the reference clock signal used for reproducing the digital data of the track is recorded, and when reproducing each track, from the recording area of the digital data in the track to be reproduced, Also reproduces the repetitive pattern recorded in the front reading area, creates a reference clock signal for the track based on this, and reproduces the digital data recorded in the digital data recording area. It is characterized by that.

That is, according to the disk medium recording / reproducing method of the first aspect, even if the frequency of the reference clock signal for reproducing the digital data recorded on each track of the digital medium is different, each track is reproduced. Record the repetitive pattern of the frequency corresponding to the reference clock signal used to reproduce the digital data in
Since this is reproduced, the reference clock signal can be reproduced based on this.

According to the second aspect of the invention, an address number indicating the address of the track is recorded between the recording area of the digital data and the recording area of the repeating pattern in the first aspect of the invention. Therefore, the reference clock signal for reproducing the digital data can be created during the reading of this section. Moreover, even if the data structure such as the address number is complicated, the reference clock signal can be reproduced regardless of the structure.

According to the third aspect of the invention, (a) the reproduced signal obtained by reading a digital medium in which a repeating pattern of a frequency corresponding to the reference clock signal used for reproducing the digital data is recorded for each track, The clock signal generator is provided with a counting means for counting the repeated pattern for a certain period of time, and (b) a reference clock signal generating means for generating a reference clock signal corresponding to the count value obtained by the counting means. I am trying.

That is, according to the third aspect of the invention, when the data is reproduced on the digital medium in which the repeating pattern of the frequency corresponding to the reference clock signal used for reproducing the digital data is recorded for each track,
By counting the repetitive pattern of the track to be reproduced for a certain period of time, we decided to generate a reference clock signal corresponding to the count value obtained as a result, and by using this for reproducing the digital data of that track. , A reference clock signal for reproducing the digital data of each track without performing complicated control.

According to a fourth aspect of the invention, the counting means in the third aspect of the invention is predetermined from the reference position of the track for reproducing the digital data in order to specify the reproduction timing of the repetitive pattern. It uses a counter that counts the playback signal for a certain time. For example, a digital rotation control servo reference signal can be used to determine the track reference position.

In a fifth aspect of the invention, the reference clock signal generating means in the third aspect of the invention is a decoder for converting the count value obtained by the counting means into data for setting a frequency division value, and a decoder for this decoder. A frequency synthesizer for generating a predetermined frequency by an output, a PLL circuit for outputting the reference clock signal described above, and a mix circuit for mixing the output of the frequency synthesizer with the output of the voltage controlled oscillator of the PLL circuit are provided. Is characterized by.

In this way, the reference clock signal is created by the two-stage configuration of the frequency synthesizer and the PLL circuit, and the data for setting the frequency division value is input to the frequency synthesizer side, whereby the reference clock signal greatly changes depending on the track. Even at any time, it is possible to create a highly reliable reference clock signal that is resistant to noise and the like.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to embodiments.

FIG. 1 shows the outline of the configuration of a clock signal generator according to an embodiment of the present invention. A reproduction signal 61, which is not shown in the figure, obtained by reading the disc is equalized as necessary and input to a comparator 62, and at the same time, a reference clock signal 63 is generated for use in reproducing the data recorded on the disc. PL
The L circuit 64 is also input.

Reproduction signal 6 input to the comparator 62
1 is binarized by being compared with a predetermined reference level. The counter 66 counts the binarized output 67 within a predetermined period in a state where the reproduction signal 61 corresponds to the repetitive pattern recorded in a predetermined area of the disc. Thus, the window generator 68 is provided to set the timing at which the counter 66 performs the counting operation. The window generator 68 is provided with a rotation control servo reference signal 69 for the disk for this purpose.

FIG. 2 shows the data structure of the tracks of the disc used for reproduction in this embodiment. Assuming that a disk 71 such as an optical disk rotates in the direction of arrow 72, only one track 7 is shown as a representative.
3 is composed of a repetitive pattern recordable area 74, a track address number area 75 following it, and a digital data area 76 following it. The distance between the track 73 and the center of the disk 71 is L.

Here, a repetitive pattern recordable area 74
A repetitive pattern of frequencies corresponding to the reference clock signal of the digital data stored in the digital data area 76 on the track is recorded in the track. For example, if the recording is performed by the (1,7) RLL (Run Length Limited) modulation digital recording method, it is possible to record a repeating pattern having a frequency of 1/16 of the clock having the lowest repeating frequency. Such a repetitive pattern may be created at the time of manufacturing the disk 71, or may be recorded by an apparatus for disk writing by the gate signal generated by the rotation control servo reference signal 69 shown in FIG. It may be performed.

Returning to FIG. 1, the description will be continued. The window generator 68, based on the rotation control servo reference signal 69,
The gate pulse 78 having a constant time width is generated regardless of the distance of the track 73 to be read from the center of the disc. The gate pulse 78 is supplied to the counter 66 as an enable signal. In this way, the binarized output 67 after being binarized by the comparator 62 is counted for a predetermined time when the gate pulse 78 is applied.

The count value data 79 representing the count value is supplied to the decoder 81 and converted into frequency division value setting data 82. The dividing value setting data 82 is shown in FIG.
Data for setting a frequency division value for generating a reference clock signal of digital data corresponding to a track 73 existing at a distance L from the center of the disk 71 shown in FIG. In this embodiment, the CWL-CAV described above is used.
The method is used to record and reproduce digital data.

The latch circuit 83 receives the frequency division value setting data 82 from the decoder 81, and latches it at the timing at which the latch pulse generator 84 sends a hold latch pulse 85. Latch pulse generator 84
The hold latch pulse 85 is created based on the rotation control servo reference signal 69. After that, the latch circuit 83 latches the frequency division value setting data 82 over the section in which the digital data area 76 shown in FIG. 2 is being reproduced, and the latch output 87 is used as the latch output 87.
Supply to 9.

Here, the frequency synthesizer 29 is a circuit having the configuration shown in FIG.
The latch output 87 is input to the same as the conventional control data input 48, and is used for setting the frequency division number.

FIG. 3 shows various signals used for setting the division ratio of the programmable counter in the clock signal generator shown in FIG. Of these, FIG. 9A shows the timing of generation of the rotation control servo reference signal 69. A gate pulse 78 shown in FIG. 7C is supplied from the window generator 68 to the counter 66 as an enable signal with reference to the time when the rotation control servo reference signal 69 is generated. The counter 66 counts the pulsed binarized output 67 shown in FIG. 3B only in the section where the gate pulse 78 falls, and supplies the result to the decoder 81 as the count value data 79. The decoding result of the decoder 81 is latched in the latch circuit 83 by the hold latch pulse 85 shown in FIG. The frequency synthesizer 29 shown in FIG.
The signal 30 having a predetermined frequency is supplied to the mix circuit 88 based on the latch output 87.

The mix circuit 88 is similar to the mixer 26 shown in FIG. 4, and the voltage control oscillator 2 of the PLL circuit 64 is used.
The transmission output 89 obtained from the signal No. 5 (see FIG. 4) is input to the mix circuit 88 so as to take the sum or the difference with the signal 30 having a predetermined frequency. The mix circuit output 91 thus obtained is supplied to the bandpass filter 27 (see FIG. 4) of the PLL circuit 64, and the summed or subtracted signal 63 (see the signal 34 in FIG. 4) is obtained, for example, in FIG. Through the buffer 19 in the same circuit portion, the reference clock signal 18 is distributed to the A / D converter 14, the discriminator 16, and the reproduction signal processing unit 17.

By the way, the clock signal generator according to the present embodiment reproduces a predetermined portion of time from the reproduction of the repeated pattern portion to the addition of the output of the latch circuit 83 to the control input of the programmable counter 44 (see FIG. 5) of the frequency synthesizer 29. Delay time occurs. However, this time delay element is the gate portion of each circuit of the counter 66, the decoder 81 and the latch circuit 83, and the delay due to these is in the range of 100 nS.

Therefore, the control of the programmable counter 44 for the PLL circuit 64 which generates the reference clock signal 18 for the digital data in the arbitrary track 73 starts the reproduction of the digital data area 76 shown in FIG. Can be terminated before Further, since the latch output 87 is held by the latch circuit 83, the value is held until the reference clock signal 18 having a new frequency is created in the next track.

[0040]

As described above, according to the inventions of claims 1 and 2, the frequency of the reference clock signal for reproducing the digital data recorded in each track of the digital medium is different. Even in such a case, the repetitive pattern of the frequency corresponding to the reference clock signal used for reproducing the digital data is recorded on each track and is reproduced. Therefore, the reference clock signal is reproduced based on this pattern. Easy to do. Moreover, it is possible to record and reproduce the disc data using the reference clock signal even for a simple disc system having no track number or the like.

Further, according to the present invention, since the repetitive pattern having the frequency corresponding to the reference clock signal is recorded and reproduced, the repetitive pattern is required to have a phase relationship with the reference clock signal and a proportional relationship with the frequency. However, there is also an effect that there is a high degree of freedom in the format of the repetitive pattern that is recorded.

According to the second aspect of the invention, the address number indicating the track address is recorded between the recording area of the digital data of each track and the recording area of the repeating pattern. The reference clock signal for reproducing the digital data can be created while reading this section. Moreover, even if the data structure such as the address number is complicated, the reference clock signal can be regenerated without being directly related thereto.

Further, according to the inventions of claims 3 to 5, the reproduction of the data for the digital medium in which the repeating pattern of the frequency corresponding to the reference clock signal used for the reproduction of the digital data is recorded for each track is performed. When doing so, the repeating pattern of the track to be reproduced is counted for a certain period of time, and the reference clock signal is generated according to the count value obtained as a result. , The reference clock signal for reproducing the digital data of each track can be obtained without performing complicated control. Further, the reference clock signal can be generated even for a simple disk system having no track number or the like.

Further, in the case of the present invention, the repetitive pattern is counted for a certain period of time, and the reference clock signal is generated using the count value obtained as a result, so that the repetitive pattern is proportional to the phase relationship and frequency with the reference clock signal. The relationship is not required, and there is an effect that the circuit device for generating the reference clock signal is simplified.

According to the invention described in claim 4, as the counting means in the invention described in claim 3, the reproduced signals are counted for a predetermined time from the reference position of the track for reproducing the digital data. Decided to use the counter to Therefore, the reproduction timing of the repetitive pattern is specified, and the reference clock signal can be accurately created.

Further, according to the invention described in claim 5, the reference clock signal is created by the two-stage configuration of the frequency synthesizer and the PLL circuit, and the data for frequency division value setting is input to the frequency synthesizer side. Therefore, even when the reference clock signal greatly changes depending on the track, it is possible to create a highly reliable reference clock signal that is resistant to noise and the like.

[Brief description of drawings]

FIG. 1 is a block diagram showing an outline of a configuration of a clock signal generator according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a data structure of tracks of a disc used for reproduction in the present embodiment.

FIG. 3 is a waveform diagram showing various signals used for setting a frequency division ratio of a programmable counter in the clock signal generator shown in FIG.

FIG. 4 is a block diagram showing an outline of a reproduction reference clock generating PLL circuit as a clock signal generating circuit.

5 is a block diagram specifically showing the configuration of the frequency synthesizer shown in FIG.

FIG. 6 is a block diagram showing a previously proposed circuit portion for obtaining the control data input used in FIG. 5;

[Explanation of symbols]

 18 Reference clock signal 61 Playback signal 62 Comparator 63 Signal of which sum or difference is taken (reference clock signal) 64 PLL circuit 67 Binary output in pulse form 66 Counter 68 Window generator 69 Rotation control servo reference signal 71 Disk 73 ( Track 74 Recordable area of repetitive pattern 76 Digital data area 81 Decoder 83 Latch circuit 84 Latch pulse generator 88 Mix circuit 89 Transmission output (obtained from voltage controlled oscillator)

Claims (5)

[Claims] 1. A reference clock used for reproducing digital data of a track in a reading area in front of the recording area of the digital data of each track of a disk medium for recording digital data for each track. A repetitive pattern having a frequency corresponding to the signal is recorded, and when the respective tracks are reproduced, the repetitive pattern recorded in the reading area before the recording area of the digital data in the reproduction target track is reproduced. Then, based on this, a reference clock signal for the track is created to reproduce the digital data recorded in the recording area of the digital data. 2. The disk according to claim 1, wherein an address number indicating an address of the track is recorded between the recording area of the digital data and the recording area of the repeating pattern. Medium recording / reproducing method. 3. A counting means for counting the repetitive pattern for a predetermined time from a replay signal obtained by reading a digital medium in which a repetitive pattern having a frequency corresponding to a reference clock signal used for replaying digital data for each track is recorded. And a reference clock signal generating means for generating a reference clock signal corresponding to the count value obtained by the counting means. 4. The counting means includes the digital
4. The clock signal generator according to claim 3, wherein the clock signal generator is a counter that counts the reproduction signal for a predetermined time from a reference position of a track on which data is reproduced. 5. The reference clock signal generating means includes a decoder for converting the count value obtained by the counting means into data for setting a frequency division value, and a frequency synthesizer for generating a predetermined frequency by the output of the decoder. ,
A PLL circuit for outputting the reference clock signal;
4. The clock signal generator according to claim 3, further comprising a mix circuit for mixing the output of the frequency synthesizer with the output of the voltage controlled oscillator of the PLL circuit.