JPH09219068A - Clock extracting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To correctly extract a clock even from the waveform low in resolution. SOLUTION: A reproduced signal is sampled by the output signal of a VCO 1 in an A/D converter 2. After the sampled value is calculated by a branch metric block 3 as a branch metric, the branch metric is generated as respective pass metrics by first and second ACS circuits 4, 5. Minimum metric values are selected by minimum metric selecting circuits 6, 7 and then a difference pass metric is generated by a subtracter 8. This value is integrated by an integrator 8, then impressed to the VCO 1 as a control signal to variably control the frequency of the output of the VCO 1. Thus, the clock synchronized with the reproduced signal is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock extracting circuit, and more particularly to a method for recording information on a disk-shaped recording medium at a high density.
The present invention relates to a clock extraction circuit that extracts a clock from a reproduction signal by using a PLL circuit in a reproduction device.

[0002]

2. Description of the Related Art In recent years, as computers have become more sophisticated,
Large-capacity file devices such as a hard disk drive (HDD) and a compact disk read only memory (CD-ROM) have become widespread. When reproducing high-density digitally recorded information on such a disk-shaped recording medium, a clock is simultaneously extracted from the reproduced analog signal to detect digital information. Particularly in the case of a file device, the reliability of the detection information is required to be very high, such as an error rate of 10 ⁻⁵ or less for an optical disk and 10 ⁻⁹ or less for a magnetic disk.

Therefore, it is necessary to extract a reproduction clock that accurately follows the rotation of the spindle, and if the clock has a lot of jitter, the reliability of the file device is significantly impaired. Therefore, a conventional clock extraction circuit extracts a clock by adding a feedback system usually called a phase locked loop (PLL) circuit.

FIG. 17 is a block diagram showing an example of a conventional clock extracting circuit. This clock extraction circuit includes a phase comparator 24, a loop filter 25, and a voltage controlled oscillator (VC
O) 26, which is a loop circuit that is a feedback loop circuit.

[0005] The phase comparator 24 compares the phase of the input pulse train REF with the phase of the output clock PCLK, and outputs a phase error signal corresponding to the phase difference. Loop filter 2
5 suppresses the high-frequency component of the input phase error signal and generates VC
It is supplied to O26 as a control voltage. The VCO 26 outputs a clock signal PCLK having a frequency according to the output voltage of the loop filter 25. This PCLK is fed back to the phase comparator 24. As a result, the frequency and phase difference of the output clock PCLK change following the frequency of the input signal (pulsed data) REF.

[0006]

By the way, in order to cope with recent multimedia, further downsizing and a high-density file device are required. On the other hand, in an optical disc apparatus that performs recording and reproduction with a beam spot having a condensing diameter that is proportional to the wavelength of the laser and inversely proportional to the numerical aperture (NA) of the objective lens, a simple beam problem such as a thermal noise problem and a tilt problem occurs. It is difficult to increase the density by reducing the size of the system. Further, in order to achieve high density with a magnetic disk, it is necessary to realize a head flying height on the order of sub-μm with a small head, and it is difficult to improve signal quality.

[0007] By applying Viterbi detection, which has been conventionally used in the field of communication, to a file device, a PRML (Partial) capable of reproducing information satisfactorily even from a reproduced waveform in which an eye pattern has almost been destroyed. Resp
Onse Maximum Likelihood) signal processing technology has begun to be used. This PRML signal processing technique is a signal processing method combining a partial response equalization method and a Viterbi detection method.

However, when data is reproduced from a medium on which high-density recording is performed, the energy of the clock frequency component included in the reproduced signal is reduced due to the reduction in resolution, and the input signal to the clock extraction circuit using the conventional PLL circuit is reduced. Will decrease the signal-to-noise ratio (SNR). Therefore, the sampling jitter increases, and the reliability of the detection information is impaired. Certainly, it is theoretically possible to detect data even from a waveform having a reduced resolution by using the PRML signal processing technique, but if the reproduced clock has a lot of jitter, its performance cannot be sufficiently brought out. Therefore, accurately extracting a clock from a low-resolution waveform is a major problem in high-density recording.

The present invention has been made in view of the above points,
It is an object of the present invention to provide a clock extracting circuit that can accurately extract a clock even from a low-resolution waveform.

[0010]

In order to achieve the above object, the present invention provides a sampling means for sampling an input signal containing a clock component with a sampling signal, and a branch metric from a sampling value obtained by sampling by the sampling means. And a first ACS circuit that receives a branch metric as an input and that corresponds to a channel that leads the optimum phase by a predetermined phase, and a first ACS circuit that receives a branch metric as an input and that corresponds to a channel that lags a predetermined phase from the optimum phase A second ACS circuit, circuit means for clearing the path metric values of the first and second ACS circuits to zero at regular intervals, and a minimum value for each output path metric of the first and second ACS circuits. And a path metric difference generating means for outputting the difference between them, and An integrator for integrating Rick difference, the output value of the integrator output a signal whose oscillation frequency is variable, is obtained by a structure having a digital variable frequency oscillator for supplying to the sampling means as a sampling signal.

Here, a conversion circuit for converting the output value of the integrator into an analog signal, and an analog variable frequency oscillator for outputting a signal whose oscillation frequency is varied by the output signal of the conversion circuit and supplying the signal to the sampling means as a sampling signal May be provided instead of the digital variable frequency oscillator.

By the way, the maximum likelihood detection method used in communication, magnetic recording, and the like, detects information by using characteristics of a reproduction channel having a clear state transition. Consider performing maximum likelihood detection when various signal levels appear with equal probability under white noise. The probability distribution of the time-series data values is the sum of a plurality of Gaussian distributions. Assuming that the center of the i-th level is a _i and the variance is σ ² , the probability P _i (x) that the input value x is at the a _i level is It becomes an expression.

P_i(X) = exp [− (x−a_i)^Two /
(2σ^Two)] / (√2πσ^Two) Time series input x_iIs m_iThe probability Q of the third level is
It can be expressed by the product of the probabilities of the above equation.

Q =. . .・ Pm _i-1 (x _i-1 ) ・ Pm
_{i (x i) · Pm i} + 1 (x i + 1) ·. . . First, the logarithm of the above equation is taken to find m _i (path) that maximizes Q.

LogQ = Σlog [Pm_i(X_i)] = Σlog [1 / (√2πσ)^Two)]-Σ ｛(x_i-A_mi)^Two/ (2σ^Two )｝ To maximize Q, maximize the second term in the above equation
Good. This is the minimum value from M defined by
Is equivalent to finding

M = Σ (x _i −a _mi ) ^{2 The} above M is usually called a metric. Also, a metric at a temporary point is a branch metric, and a certain m _i
The metric value for the series is called a path metric.

For every conceivable path, a path metric is generated from the input sequence x _i, and the path having the smallest path metric is selected. Furthermore, maximum likelihood detection can be performed by outputting data corresponding to each point in the path. However, it is difficult to realize a process of selecting one of infinite length paths in an actual circuit.
This is realized by recursively selecting paths using the Viterbi algorithm.

A Viterbi detector employing a Viterbi algorithm generally includes a branch metric calculation circuit 20, an ACS (Add Compare Select) circuit 21 for calculating a path metric, and a path to select which path, as shown in the block diagram of FIG. It is composed of a path memory 22 for storing whether the detection has been performed and a maximum likelihood determination circuit 23 for determining detection information.

In this Viterbi detector, the branch metric which is the error between the expected value and the actual input value is calculated by the branch metric calculation circuit 20 based on the reproduction signal of the recording medium or the signal input through the transmission path. After ACS
Input to the circuit 21. Here, considering a trellis diagram in which state transitions are developed on a time axis, the ACS circuit 21 selects a path so that one path is connected to one state at each time.

The selected path is stored in the path memory 22. The maximum likelihood determination circuit 23 outputs the path D from the path memory 22.
1 to D4 and errors PM1 to PM4 from the ACS circuit 21.
Selects the maximum likelihood path with the smallest path metric value at this time using the minimum branch metric. By continuing this operation, the paths before a certain time are merged into one,
The maximum likelihood path is determined.

In the Viterbi detector, a path several times past from the present time when the latest data is input cannot be determined, and a possible path remains. There are as many path metric values in the ACS circuit 21 as there are states, but the minimum value of them represents the minimum path metric value before the present time, although the path cannot be determined. This value indicates the degree to which the input sequence matches the channel characteristics in the Viterbi detector.

Now, consider the construction of a phase comparator using path metric values. As shown in FIG. 7, when a path metric value having a channel of phase θ is calculated for each fixed length path for an input sequence having a channel phase shift, a function having a minimum value at phase θ is obtained.

Here, when the minimum value of the path metric for the π / 2 advance channel and the minimum value of the path metric for the π / 2 delay channel are calculated for each fixed length path, FIG. The relationship between the path metric value and the phase amount is obtained. Further, when the difference between the minimum value of the path metric for the π / 2 advance channel and the minimum value of the path metric for the π / 2 delay channel is obtained, the relationship between the difference path metric value and the phase amount is S as shown in FIG.
It is represented by a curved curve. That is, it is possible to configure a PLL circuit by using the difference metric value as phase information for controlling the output oscillation frequency of the VCO.

As with the Viterbi detector, various ACS circuit configurations are conceivable, depending on the characteristics of the reproduction channel. Here, the minimum value of the continuous number of symbols 0 represented by the (1,7) RLL code is 1 (d = 1
After recording NRZI on an optical disk medium, the reproduction is performed. When the reproduction signal is equalized to the PR (1, 1) channel, the state transition of the optimum phase is a ternary and four state transition as shown in FIG.

In the figure, the reproduction states are S ₀ , S ₁ ,
The four states S _{2, S 3,} in the state _{S 0} is then -
There can only be 1 or 0 inputs. If -1 is input, it is in the same state as S _0, the 0 is input transitions to the state S _1, the following impossible only one input. By performing Viterbi detection using this rule, a bit error due to noise can be corrected. FIG. 11 shows the phase relationship between the reproduced waveform and the extracted clock when the state transition is represented in FIG.

However, when the phase advances from the optimum phase by θ, a six-value, four-state transition occurs as shown in FIG.
The phase relationship between the reproduced waveform and the extracted clock at this time is as shown in FIG. When the phase lags behind the optimum phase by θ, a six-value, four-state transition occurs as shown in FIG. 14, and the phase relationship between the reproduced waveform and the extracted clock at this time is as shown in FIG. In this way, the phase shift can be expressed in the form of a state transition, and the phase amount can be detected as the difference between the path metric values from the two state transitions.

In order to construct the above-described phase comparator, not all of the circuit blocks of the Viterbi detector are necessary. What is needed is a circuit system for calculating the path metric difference of a fixed path length for the two types of channels. That is, it is composed of a branch metric calculation block and two ACS circuits.
A phase comparator can be configured by adding circuit means for clearing the path metric value of the S circuit to zero.

Further, the minimum value is selected for each output path metric of the two ACS circuits, the difference between them is output, and the variable frequency oscillator is controlled by the value obtained by integrating the path metric difference with an integrator, thereby making the PLL. A circuit can be configured. This makes it possible to accurately change the signal phase-synchronized with the input signal even if the channel has a reduced resolution due to the high-density recording, or if the reproduction / playback carrier power to noise power ratio (CNR) is low and the clock jitter is large in a normal PLL. It can be output from a frequency oscillator.

[0029]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the clock extracting circuit according to the present invention. The clock extraction circuit according to this embodiment includes a digital voltage controlled oscillator (VCO) 1, an A / D converter 2 that samples, for example, a reproduction signal reproduced from a recording medium, and an A / D converter.
A branch metric calculation block 3 to which an output signal (sample value) of the converter 2 is input, two ACS circuits 4 and 5, two minimum value selection circuits 6 and 7, and a subtractor 8
And an integrator 9 for integrating the output signal of the subtractor 8 and applying the integrated signal to the VCO 1 as a control voltage;
And 5, a clear signal generating circuit (not shown) for clearing the path metric values of the ACS circuits 4 and 5 to zero at regular intervals.

FIG. 2 is a block diagram showing an example of each of the ACS circuits 4 and 5. As shown in the figure, the ACS circuits 4 and 5 add the current branch metric value to the path metric value before the temporary point by the adder 10 similarly to the ACS circuit of a general Viterbi detector, and 11, the smallest path is selected, and the path metric value is held by the delay circuit 12 for the next time calculation.

However, since the ACS circuits 4 and 5 do not need an information signal indicating which path is selected, the ACS circuits 4 and 5 determine the point at which the information signal is not output and the control signal for clearing the path metric to zero. This is different from the ACS circuit of the Viterbi detector.

Next, the operation of the embodiment shown in FIG. 1 will be described. The output oscillation signal of the VCO 1 is supplied to the A / D converter 2 as a sampling signal, where the input reproduction signal is sampled to obtain a sample value x _i , and then, similarly to a normal Viterbi detector, the branch metric calculation block 3 Calculates the branch metric. Metric value itself is not necessary in operation, since the difference becomes a problem because ^{_{(x i -a n) x 2}} i section of the ^two calculations are not required, the branch metric calculation block 3 is actually constant multiplication And a constant adder.

The branch metric values (x _i + α) ² , (x _i ) calculated by the branch metric calculation block 3
_{^{+1) 2, (x i +}} β) 2, (x i -α) 2, (x i -1) 2
And (x _i -β) ² are the first with θ leading phase channel
, And a second ACS circuit 5 having a θ delay phase channel, a path is selected at each time point, and a path metric is generated (where 0 <θ <π). ).

However, the first ACS circuit 4 and the second AC circuit 4
As shown in FIG. 2, the six branch metric values input to the S circuit 5 are the first A assuming branch metrics a, b, c, d, e, and f from the top.
The input branch metrics a, b, c, d,
e and ^{_{f, (x i + α) 2}} , (x i +1) 2, (x i +
_{^{β) 2, (x i -α}} ) 2, (x i -1) 2 and (x _i -β) ²
And the input branch metrics a, b, c, d, e and f of the second ACS circuit 5 are (x _i + β) ² , (x _i +
1) ² , (x _i + α) ² , (x _i −β) ² , (x _i −1) ² and (x _i −α) ² .

In this way, the minimum path metric of the plurality of path metric values generated and output by the first ACS circuit 4 is selected by the minimum value selection circuit 6. Similarly, the minimum path metric is selected by the minimum value selection circuit 7 from the plurality of path metric values generated and output by the second ACS circuit 5.

The minimum path metric value from the leading channel and the minimum path metric value of the lagging channel selected by the minimum value selection circuits 6 and 7 are supplied to the subtractor 7 and subtracted, so that the difference is obtained. Generated as a path metric. This difference path metric has phase information for the optimal phase as described with reference to FIG. The difference path metric having this phase information is
After being integrated by the integrator 9, it is applied as a control signal to the digital VCO 1 to variably control the output oscillation signal frequency.

As a result, the circuit shown in FIG. 1 constitutes a feedback loop, that is, a phase locked loop (PLL). However, the path metric is cleared to zero by a clear signal at regular intervals. In this manner, the clock in the reproduced signal, which is phase-synchronized with the input reproduced signal, is extracted from the digital VCO 1 and output.

As the difference path metric value input to the integrator 9, the SNR of the phase information is improved by using the value immediately before the path metric value is cleared. Therefore, an update timing signal is required. The same as the metric value clear timing can be used instead. The digital VCO 1 can be realized by using, for example, a fixed oscillator, a pulse addition / removal circuit, and a frequency divider as is well known.

Next, a second embodiment of the present invention will be described. FIG. 3 shows a second embodiment of the clock extraction circuit according to the present invention.
FIG. 2 is a block diagram of the embodiment. In the figure, the same components as those of FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. When it is necessary to increase the transfer speed in order to improve the throughput as a disk device, the configuration using the digital VCO 1 as in the first embodiment in FIG.
In some cases, the frequency of the fixed oscillator inside the VCO increases, and it becomes difficult to variably operate the output oscillation frequency according to the input signal.

Therefore, in this embodiment, as shown in FIG. 3, an analog VCO 14 using a varicap is provided in place of the digital VCO 1. The analog VCO 14 can oscillate a frequency clock corresponding to the input analog voltage, and can sufficiently cope with high-speed operation.

Accordingly, in the second embodiment shown in FIG. 3, the difference path metric having the phase information is integrated by the integrator 9, converted to an analog signal by the D / A converter 13, and then converted to the analog VCO 14. To control the output oscillation signal frequency variably. The integrator 8 and the D / A converter 13 are cleared by the same update signal. Thus, even when the transfer speed needs to be increased in order to improve the throughput of the disk device, the clock synchronized with the input reproduction signal can be extracted by controlling the oscillation frequency of the analog VCO 14 which can operate at high speed. It can be output from the analog VCO 14.

Next, a third embodiment of the present invention will be described. FIG. 4 shows a third embodiment of the clock extraction circuit according to the present invention.
FIG. 2 is a block diagram of the embodiment. In the figure, the same components as those of FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. The third embodiment shown in FIG. 4 is characterized in that the zero clear signal of the path metric value is generated by the frequency dividing circuit 15 for dividing the output oscillation signal of the VCO 1.

In FIG. 4, the output oscillation signal of the digital VCO 1 is applied to the A / D converter 2 as a sampling signal, and is divided by a frequency divider 15 into a clear signal. 5 and the integrator 9 to clear them at regular intervals.

Next, a fourth embodiment of the present invention will be described. FIG. 5 shows a fourth embodiment of the clock extraction circuit according to the present invention.
FIG. 2 is a block diagram of the embodiment. In the figure, the same components as those of FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. In this embodiment, as shown in FIG. 5, the output subtraction signal (difference path metric value) of the subtractor 8 is added to the offset constant by the adder 16 and then input to the integrator 9.

That is, depending on the characteristics of the storage medium and the nonlinearity at the time of recording, a slight offset is expected to occur between the difference between the two path metric values output from the ACS circuits 4 and 5 and the phase amount. . Therefore, in this embodiment, in order to correct this offset, an offset is added to the output difference path metric value of the subtractor 8 by the adder 16 to improve the reliability of information detection.

Next explained is the fifth embodiment of the invention. FIG. 6 shows a fifth embodiment of the clock extraction circuit according to the present invention.
FIG. 2 is a block diagram of the embodiment. In the figure, the same components as those of FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. In this embodiment, as shown in FIG. 6, first and second n-stage memories 17 and 18 such as a FIFO memory are used.
And an oscillator 19 that oscillates at a frequency n times or more higher than the output oscillation frequency of the VCO 1.

In FIG. 6, A / D converter 2 converts A / D
The sample value obtained by the D conversion is input to and stored in the first n-stage memory 17, and the memory content is updated (shifted) every time the output oscillation signal (clock) of the VCO 1 is input. The contents of the n-stage memory 17 immediately after being updated are output in parallel to the second n-stage memory 18 and stored (copied).

The second n-stage memory 18, the branch metric calculation block 3, and the two ACS circuits 4 and 5
An output oscillation signal of the second oscillator 19, which is different from the output clock of CO1, is input as the second clock CLK2 and operates. N-stage memory 18 with second clock CLK2
The n data strings serially output from are supplied to the branch metric calculation block 3 to update the path metric, and the ACS circuits 4 and 5 and the minimum value selection circuits 6 and 7
Is generated as a difference path metric by the subtractor 8.

The above operation is performed within one cycle time of the clock output from VCO1. With such a configuration, phase information can be detected for each clock output from the VCO 1, and a higher-speed following operation can be performed than in the second embodiment shown in FIG. However,
Since it is necessary to operate the ACS circuits 4 and 5 at high speed,
When the data transfer rate is high or the number of states is large, the circuit configuration may be difficult.

The present invention is not limited to the above embodiment. For example, in the third to fifth embodiments, a D / A converter and an analog VCO can be used instead of the digital VCO 1. It is.

[0051]

As described above, according to the present invention,
Branch metric calculation block and first and second AC
The S circuit and the path metric difference generating means calculate a path metric difference of a constant path length for the two channels, and operate as a phase comparator by clearing the path metric value to zero at regular intervals. , The output oscillation frequency of the variable frequency oscillator is variably controlled to form a PLL circuit. Therefore, even if the channel or the CNR whose resolution is reduced by high-density recording is low and the clock jitter is low in a normal PLL circuit, Is large, the clock can be extracted from the reproduced signal accurately in phase with the input reproduced signal.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a configuration diagram of an example of an ACS circuit.

FIG. 3 is a block diagram of a second embodiment of the present invention.

FIG. 4 is a block diagram of a third embodiment of the present invention.

FIG. 5 is a block diagram of a fourth embodiment of the present invention.

FIG. 6 is a block diagram of a fifth embodiment of the present invention.

FIG. 7 is a graph showing a minimum path metric value of an input sequence having a phase shift.

FIG. 8 is a graph showing minimum path metric values for a π / 2 leading phase channel and a π / 2 lagging phase channel.

FIG. 9 is a graph showing a difference between minimum path metric values of a π / 2 leading phase channel and a π / 2 lagging phase channel.

FIG. 10 is a state transition diagram when the phase shift amount is 0.

FIG. 11 is a diagram illustrating a relationship between a reproduced waveform having a phase shift amount of 0 and a sampling clock.

FIG. 12 is a state transition diagram when the phase advances by θ.

FIG. 13 is a diagram showing a relationship between a reproduced waveform and a sampling clock when the phase advances by θ.

FIG. 14 is a state transition diagram when the phase is delayed by θ.

FIG. 15 is a diagram showing a relationship between a reproduced waveform and a sampling clock when the phase is delayed by θ.

FIG. 16 is a block diagram showing a general Viterbi detector configuration.

FIG. 17 is a block diagram illustrating an example of a conventional clock extraction circuit.

[Explanation of symbols]

 1, 26 Digital voltage controlled oscillator (VCO) 2 A / D converter 3 Branch metric calculation block 4, 5, 21 ACS circuit 6, 7, 11 Minimum value selection circuit 8 Subtractor 9 Integrator 10, 16 Adder 12 Delay Circuit 13 D / A converter 14 Analog voltage controlled oscillator (VCO) 15 Divider 17, 18 n-stage memory 19 Oscillator 22 Path memory 23 Maximum likelihood determination circuit

Claims (5)

[Claims] 1. A sampling means for sampling an input signal including a clock component with a sampling signal, a calculation block for generating a branch metric from a sampling value obtained by sampling by the sampling means, and receiving the branch metric as an input. A first ACS circuit corresponding to a channel advanced by a predetermined phase from the optimal phase; a second ACS circuit corresponding to a channel receiving the branch metric as an input and delaying a predetermined phase from the optimal phase; Circuit means for clearing the path metric values of the first and second ACS circuits to zero; and a path metric for selecting the minimum value of each of the output path metrics of the first and second ACS circuits and outputting the difference therebetween. Difference generating means; an integrator for integrating the path metric difference; And a digital variable frequency oscillator that outputs a signal whose oscillation frequency is varied according to the output value of the integrator and supplies the signal as the sampling signal to the sampling means. 2. A frequency dividing circuit for dividing the output signal of the digital variable frequency oscillator and supplying the divided output signal to the first and second ACS circuits and the integrator as a path metric zero clear signal. The clock extraction circuit according to claim 1, wherein 3. The clock extracting circuit according to claim 1, further comprising an adding circuit for adding an offset to an output path metric difference of said path metric difference generating means and inputting the offset to said integrator. 4. An n-stage first storage circuit for updating and storing an output signal of said sampling means for each output signal of said digital variable frequency oscillator, and a second storage circuit for copying a storage value of said first storage circuit. A memory circuit, and an oscillator that oscillates at least n times the frequency of the output signal of the digital variable frequency oscillator and inputs it as a clock to the second memory circuit, the branch metric calculation block, and the first and second ACS circuits. 2. The clock extraction circuit according to claim 1, wherein: 5. A conversion circuit for converting the output value of the integrator into an analog signal, and an analog signal which outputs a signal whose oscillation frequency is changed by the output signal of the conversion circuit and supplies the signal as the sampling signal to the sampling means. 5. A clock extraction circuit according to claim 1, wherein a variable frequency oscillator is provided in place of the digital variable frequency oscillator.