JP2001358304A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device not having a step between an upper surface of a capacitor element and other wiring, not having a step in a layer formed thereon, and having high reliability and high yield of manufacturing. SOLUTION: A method for manufacturing the semiconductor device comprises the steps of forming an insulating film 11 on a semiconductor substrate 10, simultaneously forming a lower electrode 26a of the capacitor and a lower metal layer 26b on the film 11, simultaneously forming an insulating film 27a and an intermediate insulating layer 27b of the capacitor on the electrode 26a and the layer 26b, simultaneously forming an upper electrode 28a and an upper metal layer 28b of the capacitor on the film 27a and the layer 27b of the capacitor, conducting the layer 26b with the layer 28b, and forming the capacitor element and metal wirings.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, in semiconductor devices such as ICs and LSIs, a capacitor element is generally manufactured by sequentially forming a capacitor lower electrode, a capacitor insulating film and a capacitor upper electrode on a semiconductor substrate.

FIG. 10 is a process sectional view in a conventional method of manufacturing a semiconductor device.

First, as shown in FIG. 10A, a transistor, a resistor, a wiring, etc. (not shown) are formed on a semiconductor substrate 110, and a first interlayer insulating film 1 is formed thereon.
11, a metal layer is formed on the first interlayer insulating film 111, and the metal layer is etched using photolithography to form a first metal wiring 112 having a predetermined shape. I do.

Then, a second interlayer insulating film 11 is formed on the first interlayer insulating film 111 and the first metal wiring 112.
Form 3 Then, on the second interlayer insulating film 113,
After forming a plurality of connection holes 114 for connecting the first metal wiring 112 and the metal wiring formed in the upper layer by etching using photolithography, a tungsten layer is formed on the entire surface by CVD. . Next, by etching back the tungsten layer, a plurality of tungsten electrodes 115 buried in the connection holes 114 are formed as shown in FIG.

Next, after a metal layer such as aluminum is formed on the entire surface by a sputtering method, the metal layer is etched using a photolithography technique to form a capacitor as shown in FIG. The lower electrode 116 is formed. Here, the capacitor lower electrode 1
16 is electrically connected to the first metal wiring 112 by some of the tungsten 115.

Then, after a silicon oxide film is formed on the entire surface by the CVD method, the silicon oxide film is etched using photolithography technology, and as shown in FIG. A covering capacitor insulating film 117 is formed.

Next, after a metal layer such as aluminum is formed on the entire surface by a sputtering method, the metal layer is etched using a photolithography technique, and as shown in FIG. An upper electrode 118 and a third metal wiring 119 are formed.

In this manner, the capacitor lower electrode 11 is formed on the first interlayer insulating film 111 on the semiconductor substrate 110.
6, capacitor insulating film 117 and capacitor upper electrode 1
18 is manufactured.

[0010]

However, in the conventional semiconductor device and the method of manufacturing the same, the step between the capacitor upper electrode 118 and the third metal wiring 119 is large. Therefore, it is difficult to control the amount of etching when forming the capacitor upper electrode 118 and the third metal wiring 119 by etching, and the capacitor upper electrode 118 and the third metal wiring 119 cannot be formed in a desired shape. In some cases, predetermined capacitor performance may not be obtained, or disconnection may occur. For this reason, the reliability of a semiconductor device such as an IC or LSI including the capacitor element is reduced, and the yield in manufacturing is reduced.

In order to obtain a semiconductor device having a multilayer wiring, it is necessary to form a wiring layer on the capacitor upper electrode 118 and the third metal wiring 119. Is large, and it is difficult to flatten a layer formed thereon. Therefore, a step occurs in a wiring layer formed thereon, and a predetermined performance is obtained. Or the wire breaks.

The present invention solves the above-mentioned problems, and has no step between the upper surface of the capacitor element and another wiring, and there is no step in a layer formed thereon, so that the reliability is high. It is an object of the present invention to provide a semiconductor device having a high yield in manufacturing and a manufacturing method thereof.

[0013]

For this purpose, in a semiconductor device of the present invention, an insulating film formed on a semiconductor substrate, a capacitor lower electrode formed on the insulating film, and a capacitor formed on the capacitor lower electrode are formed. A capacitor element including a capacitor insulating film, and a capacitor upper electrode formed on the capacitor insulating film; a lower metal layer formed on the insulating film from the same metal layer as the capacitor lower electrode; An intermediate insulating layer formed on the metal layer from the same insulating film as the capacitor insulating film, and
An upper metal layer formed of the same metal film as the capacitor upper electrode is provided on the intermediate insulating film, and a metal wiring is provided between the lower metal layer and the upper metal layer.

In the method of manufacturing a semiconductor device according to the present invention, an insulating film is formed on a semiconductor substrate, a capacitor lower electrode and a lower metal layer are simultaneously formed on the insulating film, and the capacitor lower electrode and the lower On the metal layer, simultaneously form a capacitor insulating film and an intermediate insulating layer,
A capacitor upper electrode and an upper metal layer are simultaneously formed on the capacitor insulating film and the intermediate insulating layer, and the lower metal layer and the upper metal layer are conducted to form a capacitor element and a metal wiring.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In an embodiment of the present invention, a semiconductor device is formed on a semiconductor substrate such as a silicon substrate.
C, LSI, etc., a capacitor element, a transistor,
It includes a resistance element, a wiring, and the like.

FIG. 1 is a sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention, and FIG. 2 is a sectional view showing a process in a method of manufacturing a semiconductor device according to the first embodiment of the present invention (part 1). FIG. 3 is a process sectional view (part 2) of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

First, as shown in FIG. 2A, a transistor, a resistor, a wiring, etc. (not shown) are formed on a semiconductor substrate 10 such as a silicon substrate, and then silicon dioxide, PSG and the like are formed thereon. First interlayer insulating film 11
After forming a metal layer made of aluminum, copper, or the like on the first interlayer insulating film 11, the metal layer is etched using photolithography technology to form a metal layer having a predetermined shape. One metal wiring 12 is formed.

Thereafter, a second interlayer insulating film 13 such as a silicon oxide film or a PSG film is formed on the first interlayer insulating film 11 and the first metal wiring 12. And the second
A plurality of connection holes 14 for connecting the first metal wiring 12 and the metal wiring formed in the upper layer are formed in the interlayer insulating film 13 by etching using photolithography technology, and then tungsten is formed on the entire surface. The layer is formed by a CVD method. Next, a plurality of tungsten electrodes 15 embedded in the connection holes 14 are formed by etching back the tungsten layer.

Next, as shown in FIG. 2B, after a metal layer 26 made of aluminum, copper, or the like is formed on the entire surface by sputtering, a silicon oxide film 27 is formed on the metal layer 26 by CVD. And a metal layer 28 made of aluminum, copper, or the like is formed on the silicon oxide film 27 by a sputtering method.

After that, the metal layer 26, the silicon oxide film 27 and the metal layer 28 are etched using photolithography technology, and as shown in FIG. ,
Capacitor insulating film 27a and capacitor upper electrode 28a
And a lower metal layer 26b, an intermediate insulating layer 27b, and an upper metal layer 28b which are to be wirings.

Next, a third interlayer insulating film 29 such as a silicon oxide film or a PSG film is formed on the entire surface. A plurality of connection holes 30 for connecting the upper electrode 28a and a metal wiring formed in an upper layer are formed in a portion of the third interlayer insulating film 29 corresponding to a portion serving as a capacitor element by photolithography. After being formed by the used etching, a tungsten layer is formed on the entire surface of the third interlayer insulating film 29 by a CVD method. Next, by etching back the tungsten layer, a plurality of tungsten electrodes 31 buried in the connection holes 30 are formed as shown in FIG.

Thereafter, a connection hole 32 is formed in a portion of the third interlayer insulating film 29 corresponding to a portion to be a wiring by etching using a photolithography technique. At this time, the upper metal layer 28b and the intermediate insulating layer 27b are etched together with the third interlayer insulating film 29 so that the connection holes 32 reach the lower metal layer 26b. Next, a tungsten layer is again formed on the entire surface of the third interlayer insulating film 29 by the CVD method, and then the tungsten layer is etched back, as shown in FIG. Connection hole 32
A tungsten electrode 33 embedded in the substrate is formed.

As a result, the first metal wiring 12,
The lower metal layer 26b, the upper metal layer 28b, and a later-described fourth metal wiring 34 are electrically connected.

Next, after a metal layer made of aluminum, copper, or the like is formed on the entire surface of the third interlayer insulating film 29, the metal layer is etched using a photolithography technique, and FIG. As shown in FIG. 1, a fourth metal wiring 34 is formed.

Thus, as shown in FIG.
A capacitor element including a capacitor lower electrode 26a, a capacitor insulating film 27a and a capacitor upper electrode 28a on the second interlayer insulating film 13 on the semiconductor substrate 10, and
A semiconductor device having a metal wiring including the lower metal layer 26b, the intermediate insulating layer 27b, and the upper metal layer 28b can be obtained.

The upper metal layer 2 which is the uppermost layer of the metal wiring formed on the second interlayer insulating film 13
The height of 8b is equal to the height of the capacitor upper electrode 28a.

As described above, in the present embodiment, since the height of the capacitor element formed on the second interlayer insulating film is the same as the height of the metal wiring, the height of the capacitor upper electrode and the metal wiring are reduced. Since the control of the etching amount becomes easy and it can be formed into a desired shape, a predetermined capacitor performance cannot be obtained or a disconnection does not occur. For this reason, the reliability of semiconductor devices such as ICs and LSIs including the capacitor element is improved, and the yield in manufacturing is also improved.

Further, when a semiconductor device having a multilayer wiring is obtained, since the height of the capacitor upper electrode and the metal wiring are the same, the layer formed thereon can be flattened and formed thereon. Since there is no step in the wiring layer, predetermined performance cannot be obtained or disconnection does not occur.

Next, a second embodiment of the present invention will be described.

The same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted.

FIG. 4 is a sectional view showing a structure of a semiconductor device according to a second embodiment of the present invention, and FIG. 5 is a sectional view showing a process in a method of manufacturing a semiconductor device according to the second embodiment of the present invention (part 1). FIG. 6 is a process sectional view (part 2) of the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

First, the step shown in FIG.
Since this is the same as the step shown in FIG. 5A in the embodiment, description thereof will be omitted.

Next, as shown in FIG. 5B, a metal layer 46 made of an aluminum-based metal such as aluminum, Al--Si, or Al--Cu is formed on the entire surface by a sputtering method. A metal layer 47 made of a Ti-based metal is formed on 46 by a sputtering method. Here, the metal layers 46 and 47 have a selectivity in etching, that is, have a double structure of metals having different etching rates.

Subsequently, as shown in FIG. 5C, a silicon oxide film 48 is formed on the metal layer 47 by a CVD method, and further, aluminum, copper or the like is formed on the silicon oxide film 48. Is formed by a sputtering method.

Next, FIG. 2 in the first embodiment will be described.
In the same manner as in the step shown in FIG.
6, metal layer 47, silicon oxide film 48 and metal layer 4
9 is etched using photolithography technology,
Capacitor lower electrode 46a in a portion to be a capacitor element
And 47a, a capacitor insulating film 48a, a capacitor upper electrode 49a, and a lower metal layer 46 at a portion to be a wiring.
b and 47b, the intermediate insulating layer 48b and the upper metal layer 4
9b, and FIG. 3 in the first embodiment.
As shown in FIG. 6A, a plurality of tungsten electrodes 52 buried in the connection holes 51 in the third interlayer insulating film 50 such as a silicon oxide film or a PSG film in the same manner as the process shown in FIG. Is formed.

Thereafter, FIG. 3 in the first embodiment
As shown in FIG. 6B, a tungsten electrode 54 buried in the connection hole 53 reaching the lower metal layer 47b is formed in the same manner as in the step shown in FIG.

As a result, the first metal wiring 12,
The lower metal layers 46b and 47b, the upper metal layer 49b, and a later-described fourth metal wiring 55 are electrically connected.

Next, FIG. 3 in the first embodiment will be described.
As in the process shown in FIG.
Structure), the fourth metal interconnection 55
To form

Thus, as shown in FIG.
On the second interlayer insulating film 13 on the semiconductor substrate 10, the capacitor lower electrodes 46a and 47a, the capacitor insulating film 48
a and a capacitor element including a capacitor upper electrode 49a, lower metal layers 46b and 47b, and an intermediate insulating layer 48.
b and a semiconductor device having a metal wiring including the upper metal layer 28b can be obtained.

As described above, in the present embodiment, in addition to the effects of the first embodiment, the metal wiring formed on the second interlayer insulating film is formed of an aluminum-based metal and a Ti-based metal. Because of the stacked structure, a wiring structure resistant to electromigration can be obtained, and there is an effect that reliability can be improved.

Next, a third embodiment of the present invention will be described.

FIG. 7 is a sectional view showing a structure of a semiconductor device according to a third embodiment of the present invention, and FIG. 8 is a sectional view of a process in a method of manufacturing a semiconductor device according to the second embodiment of the present invention (part 1). FIG. 9 is a process sectional view (part 2) of the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

First, the step shown in FIG.
Since this is the same as the step shown in FIG. 2A in the embodiment, description thereof will be omitted.

Next, FIG. 5 in the second embodiment will be described.
A metal layer 66 made of an aluminum-based metal such as aluminum, Al-Si, or Al-Cu is formed on the entire surface by a sputtering method in the same manner as the step shown in FIG. A metal layer 67 made of a Ti-based metal is formed by a sputtering method. Here, the metal layers 66 and 67 have a selective structure in etching, that is, have a double structure of metals having different etching rates.

Thereafter, as shown in FIG. 8B, a portion of the metal layer 67 to be a capacitor element is partially removed to form a concave portion by etching using a photolithography technique.

Next, a silicon oxide film 68 is formed on the metal layer 67 by CVD, and a metal layer 69 made of aluminum, copper or the like is formed on the silicon oxide film 68 by sputtering. , FIG.
As shown in (c), the thin silicon oxide film 68 covers the wall surface of the concave portion from which the metal layer 67 has been removed, and the metal layer 69 enters the concave portion from above and fills the concave portion. State. Here, the upper surface of the metal layer 69 is flat.

Next, FIG. 2 in the first embodiment
In the same manner as in the step shown in FIG.
6, metal layer 67, silicon oxide film 68 and metal layer 6
9 is etched using photolithography technology,
Capacitor lower electrode 66 in a portion to be a capacitor element
a and 67a, the capacitor insulating film 68a, the capacitor upper electrode 69a, and the lower metal
6b and 67b, an intermediate insulating layer 68b, and an upper metal layer 69b.
Similarly to the process shown in FIG. 9A, as shown in FIG. 9A, a plurality of tungsten electrodes buried in connection holes 71 in a third interlayer insulating film 70 such as a silicon oxide film or a PSG film. 72 are formed.

Thereafter, FIG. 3 in the first embodiment
9B, a tungsten electrode 74 buried in the connection hole 73 reaching the lower metal layer 67b is formed in the same manner as in the step shown in FIG. 9B.

As a result, the first metal wiring 12,
The metal layer 66b, the metal layer 67b, the metal layer 69b, and a fourth metal wiring 75 described later are electrically connected.

Next, FIG. 3 in the first embodiment will be described.
As in the process shown in FIG. 9C, FIG.
Structure), the fourth metal interconnection 75
To form

In this way, as shown in FIG.
A capacitor element including capacitor lower electrodes 66a and 67a, a capacitor insulating film 68a and a capacitor upper electrode 69a, a lower metal layer 66b and 67b, and an intermediate insulating layer 68b on the second interlayer insulating film 13 on the semiconductor substrate.
In addition, a semiconductor device having a metal wiring including the upper metal layer 68b can be obtained.

As described above, in this embodiment, in addition to the effects of the first and second embodiments, a concave portion is formed in the capacitor lower electrode, and the capacitor insulating film and the capacitor upper electrode are formed in the concave portion. As a result, the area of the opposing capacitor electrode is increased, and the capacitance of the capacitor is increased. Therefore,
In this embodiment, the space occupied by the capacitor in the semiconductor element can be reduced, and the cost can be reduced.

In the above-described embodiment, the capacitor is formed separately from the wiring portion. However, a part of the wiring may be formed as a capacitor without being separated from the wiring.

It should be noted that the present invention is not limited to the above-described embodiment, but can be variously modified based on the gist of the present invention, and they are not excluded from the scope of the present invention.

[0056]

As described above in detail, according to the present invention, in a semiconductor device, an insulating film formed on a semiconductor substrate, a capacitor lower electrode formed on the insulating film, and a capacitor lower electrode are formed. A capacitor element including a capacitor insulating film formed on the electrode, and a capacitor upper electrode formed on the capacitor insulating film; and a lower metal formed on the insulating film from the same metal layer as the capacitor lower electrode. Layer, an intermediate insulating layer formed on the lower metal layer from the same insulating film as the capacitor insulating film,
And a metal wiring including an upper metal layer formed of the same metal film as the capacitor upper electrode on the intermediate insulating film, wherein the lower metal layer and the upper metal layer are electrically connected.

In the method of manufacturing a semiconductor device,
Forming an insulating film on the semiconductor substrate, simultaneously forming a capacitor lower electrode and a lower metal layer on the insulating film, and simultaneously forming a capacitor insulating film and an intermediate insulating layer on the capacitor lower electrode and the lower metal layer; Then, a capacitor upper electrode and an upper metal layer are simultaneously formed on the capacitor insulating film and the intermediate insulating layer, and the lower metal layer and the upper metal layer are conducted to form a capacitor element and a metal wiring.

In this case, since the height of the capacitor element formed on the insulating film and the height of the metal wiring are the same, it is easy to control the amount of etching when forming the capacitor upper electrode and the metal wiring, and to obtain a desired shape. Because it can be formed, the predetermined capacitor performance can not be obtained,
There is no disconnection. Therefore, the reliability of the semiconductor device including the capacitor element is improved, and the production yield is also improved.

Further, even when a semiconductor device having a multilayer wiring is obtained, since the capacitor upper electrode and the metal wiring have the same height, the layer formed thereon can be flattened and formed thereon. Since there is no step in the wiring layer, predetermined performance cannot be obtained or disconnection does not occur.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a structure of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a process sectional view (part 1) of the method for manufacturing a semiconductor device according to the first embodiment of the present invention;

FIG. 3 is a process sectional view (part 2) of the method for manufacturing a semiconductor device according to the first embodiment of the present invention;

FIG. 4 is a cross-sectional view illustrating a structure of a semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a process cross-sectional view (part 1) of the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 6 is a process cross-sectional view (part 2) in the method for manufacturing a semiconductor device in the second embodiment of the present invention.

FIG. 7 is a sectional view illustrating a structure of a semiconductor device according to a third embodiment of the present invention.

FIG. 8 is a process cross-sectional view (part 1) of the method for manufacturing a semiconductor device in the third embodiment of the present invention.

FIG. 9 is a process cross-sectional view (part 2) of the method for manufacturing a semiconductor device in the third embodiment of the present invention.

FIG. 10 is a process sectional view in a conventional method of manufacturing a semiconductor device.

[Explanation of symbols]

 Reference Signs List 10 semiconductor substrate 11 insulating film 26a, 46a, 66a capacitor lower electrode 27a, 48a, 68a capacitor insulating film 28a, 49a, 69a capacitor upper electrode 26b, 46b, 66b lower metal layer 27b, 48b, 68b intermediate insulating film 28b, 49b, 69b Upper metal layer

Claims (2)

[Claims] An insulating film formed on a semiconductor substrate; a capacitor lower electrode formed on the insulating film; a capacitor insulating film formed on the capacitor lower electrode; A capacitor element including a capacitor upper electrode formed on a capacitor insulating film; (c) a lower metal layer formed of the same metal layer as the capacitor lower electrode on the insulating film; and a capacitor formed on the lower metal layer. An intermediate insulating layer formed of the same insulating film as the insulating film, and an upper metal layer formed of the same metal film as the capacitor upper electrode on the intermediate insulating layer, wherein the lower metal layer and the upper metal A semiconductor device having a metal wiring electrically connected to a layer. (A) forming an insulating film on a semiconductor substrate;
(B) simultaneously forming a capacitor lower electrode and a lower metal layer on the insulating film; (c) simultaneously forming a capacitor insulating film and an intermediate insulating layer on the capacitor lower electrode and the lower metal layer; (E) simultaneously forming a capacitor upper electrode and an upper metal layer on the capacitor insulating film and the intermediate insulating layer, and (e) electrically connecting the lower metal layer and the upper metal layer; A method for manufacturing a semiconductor device, comprising forming a wiring.