JP2001345443A - Semiconductor integrated circuit device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique for promoting high integration of a semiconductor integrated circuit device by ensuring a margin between a gate electrode of an MISFET and a plug on its source or drain. SOLUTION: When forming a W film 9c which constitutes a gate electrode between a source and a drain of an MISFET an undercut is generated by isotropically etching an upper part thereof, and then a sidewall upper part of the W film 9c constituting a gate electrode is tapered by anisotropic etching, and thereafter a plug is formed on a source or a drain of an MISFET.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly, to a fine MISFE.
T (Metal Insulator Semiconductor Field Effect Tra
nsistor) and the technology that is effective in its manufacture.

[0002]

2. Description of the Related Art The source and drain of a MISFET are connected to metal wiring via a plug formed by embedding a conductive film in a contact hole formed on the source and drain. Alternatively, a metal film is formed on the substrate including the inside of the contact hole, and patterned into a desired shape to form a metal wiring, thereby connecting the source and the drain.

[0003]

However, with the miniaturization of the semiconductor integrated circuit device, the plug and the like and the MISF
There is a problem in that a margin for alignment with the gate electrode of the ET is secured, and the yield is reduced due to these short circuits.

In particular, when forming contact holes on the source and drain of a MISFET formed according to a fine design rule, a so-called SAC (Self Align Controller) is used.
ct) technology is used. That is, this is a technique in which a silicon nitride film is formed on the upper surface and side surfaces of a gate electrode, and contact holes are formed by dry etching utilizing a difference in etching rate between the silicon nitride film and a silicon oxide film formed thereon. In this case, a margin for alignment with the gate electrode is not required, and a fine MISFET can be formed.

However, in the above-described SAC technology, the occupation ratio of the silicon nitride film covering the upper surface and side surfaces of the gate electrode and the silicon oxide film formed thereon is determined by the etching selectivity of the two. Furthermore, there is no technique for etching a silicon oxide film without etching the silicon nitride film 100%, and the silicon nitride film is also etched.

For this reason, when the size of the silicon oxide film is reduced in accordance with the miniaturization of the MISFET, the etching rate of the silicon oxide film is reduced, and the silicon nitride film is made thinner. As a result, the shoot margin between the plug buried in the contact hole and the gate electrode decreases, and the yield decreases due to short-circuit failure.

An object of the present invention is to provide a technique for promoting the high integration of a semiconductor integrated circuit device constituted by MISFETs. Also, another object of the present invention is to provide an M
An object of the present invention is to secure a shoot margin between a gate electrode of an ISFET and a plug and to reduce short-circuit defects.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) The semiconductor integrated circuit device of the present invention
(A) a source and a drain formed in a semiconductor substrate; and (b) a gate electrode formed on a semiconductor substrate between the source and the drain via a gate insulating film, and an upper portion of a side wall thereof is tapered. A gate electrode that is shaped;
(C) an insulating film formed on a side portion and an upper portion of the gate electrode.

(2) The semiconductor integrated circuit device of the present invention
(A) a source and a drain formed in a semiconductor substrate; and (b) a gate electrode formed on a semiconductor substrate between the source and the drain via a gate insulating film, and an upper portion of a side wall thereof is tapered. A gate electrode that is shaped;
(C) an insulating film formed on a side portion and an upper portion of the gate electrode; and (d) a plug formed on the source or the drain and in contact with the insulating film.

(3) The semiconductor integrated circuit device of the present invention
(A) a source and a drain formed in a semiconductor substrate; (b) a polycrystalline silicon film formed on a semiconductor substrate between the source and the drain via a gate insulating film; and the polycrystalline silicon film A gate electrode formed of a barrier metal film formed thereon, a tungsten film formed on the barrier metal film and having a tapered upper side wall; and (c) formed on side and upper portions of the gate electrode. An insulating film; and (d) a plug formed on the source or the drain and in contact with the insulating film.

(4) A method of manufacturing a semiconductor integrated circuit device according to the present invention includes: (a) forming a gate insulating film on a semiconductor substrate; and (b) forming a conductive film on the gate insulating film. (C) a step of forming an insulating film on the conductive film; (d) a step of patterning the insulating film into a desired shape; and (e) a step of forming the conductive film using the insulating film as a mask. After isotropically etching the portion, a step of anisotropically etching the conductive film using the insulating film as a mask,
(F) introducing impurities into the semiconductor substrate using the insulating film and the conductive film as a mask.

(5) A method of manufacturing a semiconductor integrated circuit device according to the present invention includes: (a) forming a gate insulating film on a semiconductor substrate; and (b) forming a first conductive film on the gate insulating film. Forming; (c) forming a first insulating film on the first conductive film; (d) patterning the first insulating film into a desired shape; and (e). A step of isotropically etching a part of the first conductive film using the first insulating film as a mask, and then anisotropically etching the first conductive film using the insulating film as a mask; (F) forming source and drain regions by introducing impurities into the semiconductor substrate using the insulating film and the first conductive film as a mask; and (g) forming an upper portion of the first conductive film and Forming a second insulating film covering the side surfaces and extending over the source and drain regions; (H) forming a third insulating film on the second insulating film; and (i) etching the third insulating film on the source or drain region with the second insulating film. A contact hole reaching a source or drain region by etching the exposed second insulating film after exposing the surface of the second insulating film on the semiconductor substrate by etching using a speed difference. And (j) forming a plug by burying a second conductive film in the contact hole.

According to the above-described means, the upper portion of the side wall of the gate electrode is tapered, or the conductive film forming the gate electrode is isotropically etched and then anisotropically etched to form the gate electrode. Because
Thereafter, even if a plug is formed by providing a contact hole on the source or the drain and burying the conductive film, a margin between the gate electrode and the plug can be secured, and a short circuit defect can be reduced. . Further, high integration of the semiconductor integrated circuit device constituted by the MISFET can be achieved.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) A method of manufacturing a semiconductor integrated circuit device according to Embodiment 1 of the present invention will be described in the order of steps with reference to FIGS.

First, as shown in FIG.
An element isolation groove 2 is formed in a semiconductor substrate (hereinafter, simply referred to as a substrate) 1 made of p-type single crystal silicon having a specific resistance of about Ωcm.

In order to form the element isolation groove 2, the substrate 1 in the element isolation region is first etched to form a groove having a depth of about 350 nm, and then the substrate 1 is thermally oxidized at about 1000 ° C. A thin silicon oxide film 6 having a thickness of about 10 nm is formed on the inner wall of the substrate. The silicon oxide film 6 is used to recover the damage caused by the dry etching generated on the inner wall of the groove and to relieve the stress generated at the interface between the silicon oxide film 7 embedded in the groove and the substrate 1 in the next step. Form. Next, a silicon oxide film 7 is formed inside the groove 2. After the silicon oxide film 7 is formed on the silicon oxide film 6 including the inside of the trench, the surface thereof is polished by the CMP method, so that the silicon oxide film 7 remains inside the element isolation trench 2.

Next, a p-type impurity such as boron and an n-type impurity such as phosphorus are ion-implanted into the substrate 1 and then diffused by a heat treatment at about 1000 ° C.
A p-type well 3 and an n-type well 4 are formed.

Next, after the surface of the substrate 1 is wet-cleaned, a clean gate oxide film 8 having a thickness of about 6 nm is formed on each surface of the p-type well 3 and the n-type well 4 by thermal oxidation at about 800.degree. I do.

Further, on the gate oxide film 8, a phosphorus-doped low-resistance polycrystalline silicon film 9a having a thickness of about 100 nm is formed.
Is deposited by a CVD method, a W film 9c (conductive film) having a thickness of about 50 nm is deposited thereon by a sputtering method, and a silicon nitride film 10 having a thickness of about 100 nm is further formed thereon by a CVD method. (Insulating film).

Next, as shown in FIG. 2, the silicon nitride film 10 is dry-etched using a photoresist film (not shown) as a mask. Thereafter, the gate electrode 9 made of the W film 9c and the polycrystalline silicon film 9a is formed by etching the W film 9c and the polycrystalline silicon film 9a using the silicon nitride film 10 as a mask.
The steps will be described in detail with reference to FIGS.

FIG. 3A is a partially enlarged view of the p-well region in FIG. Using the silicon nitride film 10 etched into a desired shape as shown in FIG. 3A as a mask, a part of the W film 9c is isotropically etched to produce an undercut under the silicon nitride film 10. (Figure 3
(B)). Next, as shown in FIG. 2C, the W film 9c is anisotropically etched using the silicon nitride film 10 as a mask. The amount of isotropic etching of the W film 9c is
The increase in resistance caused by the undercut of
Set so that there is no problem in the operation of ET.

Next, the polycrystalline silicon film 9a is anisotropically etched using the silicon nitride film 10 as a mask. As a result, as shown in FIG. 4, a gate electrode 9 composed of a W film 9c and a polycrystalline silicon film 9a having tapered shoulders is formed.

Next, as shown in FIG. 5, on both sides of the gate electrode 9 on the p-type well 3, an n-type impurity such as phosphorus or arsenic is ion-implanted to form an n-type semiconductor region 11, Also, the gate electrode 9 on the n-type well 5
The p-type semiconductor region 12 is formed by ion-implanting a p-type impurity such as boron into both sides of the substrate. next,
After depositing a silicon nitride film having a thickness of about 50 nm on the substrate 1 by the CVD method, the silicon nitride film is anisotropically etched to form a sidewall spacer 13 a on the side wall of the gate electrode 9.

Next, an n ⁺ -type semiconductor region 14 (source, drain) is formed by ion-implanting an n-type impurity such as phosphorus or arsenic into the p-type well 3, and a p-type semiconductor such as boron is formed in the n-type well 4. By implanting impurities, the p ⁺ type semiconductor region 15 (source, drain)
To form Up to this point, LDD (Lightly Doped
N-channel type MISFET Qn and p-channel type MISFET Qp
Is formed.

Next, as shown in FIG.
Silicon oxide film 1 having a thickness of about 700 nm to 800 nm by D method
After depositing 6, the silicon oxide film 16 is polished by a CMP method to flatten its surface. Next, a plurality of contact holes 22 are formed by dry-etching the silicon oxide film 16 using a photoresist film (not shown) as a mask.

Next, a tungsten film 27 having a thickness of about 300 nm is deposited on the silicon oxide film 16 including the inside of the contact hole 22 by a sputtering method.
The tungsten film 27 is polished by CMP until the surface of the silicon oxide film 16 is exposed, so that the tungsten film 27 is left inside the contact hole 22.

Further, a metal film 30 is formed on the tungsten film 27 and the silicon oxide film 16 and is patterned into a desired shape to form an upper wiring 30 on the tungsten film 27. Further, a silicon oxide film 34 is formed on the upper wiring 30. As described above, by repeatedly forming the silicon oxide film and the metal film, a multilayer wiring connected to the source or the drain of the MISFET via the tungsten film 27 can be formed.

As described above, according to the present embodiment, a part of the W film 9c constituting the upper part of the gate electrode is isotropically etched using the silicon nitride film 10 as a mask, and the under film is formed under the silicon nitride film 10. Since the gate electrode was formed by anisotropically etching after the cut was made, the upper part of the side wall of the gate electrode 9 could be tapered, and the tungsten film 27 in the contact hole near the gate electrode could be formed. A margin with the gate electrode 9 can be secured. That is, as shown in FIG. 8, when the upper portion of the side wall of the gate electrode 9 is not tapered, the gap between the gate electrode 9 and the tungsten film 27 is A, whereas the upper portion of the side wall of the gate electrode 9 is tapered. In the case of the shape, the space between the gate electrode 9 and the tungsten film becomes A + B, and a margin between the tungsten film and the gate electrode can be secured. As a result, short-circuit defects can be reduced. Further, high integration of the MISFET can be achieved.

In FIG. 6, although there is a space between the side wall spacer 13a formed on the side wall of the gate electrode 9 and the contact hole 22, the MISFET
In a place where is accumulated, as shown in FIG. 9, a part of the contact hole 22a is formed so as to overlap the silicon nitride film 10 on the gate electrode. In this case, the contact hole 22a is formed with respect to the gate electrode 9 by performing a combination of a condition for increasing the etching rate of silicon oxide with respect to silicon nitride and a condition for increasing the etching rate of silicon nitride with respect to silicon. And can be formed in a self-aligned manner.

In such a case, in particular, the tungsten film 27 in the contact hole 22a and the gate electrode 9
Since it is difficult to secure a margin between the gate electrode 9 and the gate electrode 9, the effect obtained by forming the upper portion of the side wall of the gate electrode 9 into a tapered shape as in the present embodiment is increased.

(Embodiment 2) A method of manufacturing a memory cell portion as a method of manufacturing a semiconductor integrated circuit device according to Embodiment 2 of the present invention will be described in the order of steps with reference to FIGS.

First, as shown in FIG.
An element isolation groove 2 is formed in a semiconductor substrate (hereinafter simply referred to as a substrate) 1 made of p-type single crystal silicon having a specific resistance of about 0 Ωcm. As in the case of the first embodiment, the element isolation 2 is formed by first etching the substrate 1 in the element isolation region to form a groove, and then performing thermal oxidation to form a thin oxide film having a thickness of about 10 nm on the inner wall of the groove. A silicon film 6 is formed and then formed by embedding a silicon oxide film 7 inside the trench 2.

Next, after implanting a p-type impurity such as boron and an n-type impurity such as phosphorus into the substrate 1,
The n-type well 5 and the p-type well 3 are formed by diffusing by heat treatment at 00 ° C.

Next, after the surface of the substrate 1 is wet-cleaned, a clean gate oxide film 8 having a thickness of about 6 nm is formed on the surface of the p-type well 3 by thermal oxidation at about 800.degree. Next, a low-resistance polycrystalline silicon film 9a doped with phosphorus (P) and having a thickness of about 100 nm is formed on the gate oxide film 8 by CVD.
Then, a WN film 9b (barrier metal film) having a film thickness of about 5 nm and a film thickness of 50 nm are formed thereon by sputtering.
A W film 9c (first conductive film) is deposited, and a silicon nitride film 10 (first insulating film) having a thickness of about 100 nm is deposited thereon by CVD. Next, using a photoresist film (not shown) as a mask, the silicon nitride film 10 is formed.
Is dry-etched.

Thereafter, W film 9c, WN film 9b and polycrystalline silicon film 9a are etched using silicon nitride film 10 as a mask to form a gate electrode composed of W film 9c, WN film 9b and polycrystalline silicon film 9a. 9 (word line WL) is formed. Note that, similarly to the first embodiment, gate electrode 9 may have a two-layer structure including W film 9c and polycrystalline silicon film 9a.

First, using the silicon nitride film 10 etched into a desired shape as a mask, a part of the W film 9c is isotropically etched to produce an undercut under the silicon nitride film 10. Next, the W film 9c is anisotropically etched using the silicon nitride film 10 as a mask. The amount of isotropic etching of the W film 9c is such that the increase in resistance caused by the undercut of the W film 9c is caused by the MISFET.
Set so that there is no problem in the operation of. Subsequently, using the silicon nitride film 10 as a mask, the WN film 9b and the W film 9c
Is anisotropically etched. As a result, a gate electrode 9 composed of a W film 9c, a WN film 9b, and a polycrystalline silicon film 9a having tapered shoulders is formed.
1).

Next, as shown in FIG.
An n-type semiconductor region 11 is formed by ion-implanting n-type impurities such as phosphorus or arsenic on both sides of the upper gate electrode 9.

In the steps up to this point, the memory cell selection M
ISFET Qs is formed.

Next, a silicon nitride film 13 (second insulating film) is deposited on the substrate 1 by the CVD method, and then a silicon oxide film 16 (third insulating film) is formed on the silicon nitride film 13 by the CVD method. Is deposited, the silicon oxide film 16 is polished by the CMP method to flatten the surface.

Next, as shown in FIG. 13, the silicon oxide film 16 is dry-etched by dry etching using a photoresist film (not shown) as a mask, and then the silicon nitride film 13 is dry-etched.
N-type semiconductor region 1 of memory cell selection MISFET Qs
1 (source, drain), contact holes 18 and 19 are formed in one upper part.

In forming the contact holes 18 and 19, the etching of the silicon oxide film 16 is performed under conditions that increase the etching rate of silicon oxide with respect to silicon nitride. The etching is performed under the condition that the etching is performed anisotropically so that the silicon nitride film 13 is left on the side wall of the gate electrode 9. As a result, contact holes 18 and 19 having a fine diameter are formed in self-alignment (self-alignment) with gate electrode 9.

Next, a plug 20 is formed inside the contact holes 18 and 19. The plug 20 is formed by depositing a low-resistance polycrystalline silicon film (second conductive film) doped with an n-type impurity such as phosphorus (P) on the silicon oxide film 16 including the insides of the contact holes 18 and 19 by a CVD method. Then, this polycrystalline silicon film is etched back (or polished by a CMP method) and left only in the contact holes 18 and 19 to form the polycrystalline silicon film.

Next, as shown in FIG. 14, a silicon oxide film 21 is deposited on the silicon oxide film 16 by the CVD method, and a bit line (not shown) is formed on the silicon oxide film 21. A silicon oxide film 34 is deposited on the bit line by the CVD method.
The silicon oxide films 34 and 21 on the upper portion 9 are removed by etching, a contact hole 38 is formed, and a plug 39 is formed therein.

Next, CVD is performed on the silicon oxide film 34.
A silicon nitride film 40 and a silicon oxide film 41 are sequentially deposited by a method, and then the silicon oxide film 41 and the silicon nitride film 40 are etched to form a groove 42.
A memory cell is almost completed by forming an information storage capacitance element C including a lower electrode 43, a capacitance insulating film 44, and an upper electrode 45 inside 2. The lower electrode 43 of the information storage capacitor is formed of, for example, a low-resistance polycrystalline silicon film doped with an n-type impurity. In addition, the capacitance insulating film 4
Reference numeral 4 denotes, for example, a tantalum oxide (Ta2O5) film, and the upper electrode 45 includes, for example, a titanium nitride (TiN) film.

As described above, according to the present embodiment, a part of the W film 9c constituting the upper part of the gate electrode is isotropically etched using the silicon nitride film 10 as a mask, and the under film is formed under the silicon nitride film 10. Since the gate electrode is formed by anisotropically etching after the cut is made, the upper portion of the side wall of the gate electrode 9 can be tapered. Therefore, a margin between the plug 20 buried in the contact hole near the gate electrode and the gate electrode 9 can be secured, and short-circuit failure can be reduced. Further, high integration of the MISFET can be achieved.

In particular, the memory cell selecting MISFET Qs
Since high integration is required, a contact hole is formed in self-alignment with the gate electrode 9 using the above-described SAC technique.

In such a case, particularly, it is difficult to secure a margin between the plug in the contact hole and the gate electrode. Therefore, as in the present embodiment, the upper portion of the side wall of the gate electrode 9 has a tapered shape. The effect of doing so is great.

In the second embodiment, the case where the present invention is applied to a method of manufacturing a memory cell portion has been described. However, the present invention can be applied to a method of manufacturing a DRAM including peripheral circuits. That is, the present invention can be applied to the case where the peripheral circuit region described in Embodiment 1 and the memory cell portion described in Embodiment 2 are formed over the same substrate.

In this case, the gate electrode 9 in the peripheral circuit region
Is formed in the same step as the gate electrode 9 (word line WL) of the memory cell portion, and a portion of the W film 9c constituting the gate electrode 9 is isotropically etched and then anisotropically etched. , The shoulder of the W film 9c is tapered.

Further, the bit line described in the second embodiment is used as an embedded wiring, and the plug 27 described in the first embodiment is used.
It can be formed at the same time.

By such a process, the plugs 20, 27
A margin between the gate electrode 9 and the gate electrode 9 can be secured, a short circuit defect can be reduced, and a semiconductor integrated circuit device can be manufactured in a short process. Also, MISF
A semiconductor integrated circuit device with high integration of ET can be manufactured in a short process.

As described above, the method invention made by the present inventor has been specifically described based on the embodiments of the present invention. However, the present invention is not limited to the above embodiments, and the present invention is not limited thereto. It goes without saying that various changes can be made.

[0056]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, a part of the conductive film constituting the gate electrode is isotropically etched using the insulating film as a mask, and then anisotropically etched so that the upper portion of the side wall of the gate electrode is tapered. Therefore, even if a plug, a wiring, or the like is formed in the contact hole near the gate electrode thereafter, a margin between them can be secured, and a short circuit failure can be reduced. Further, if a margin between them can be secured, high integration of the semiconductor integrated circuit device can be achieved.

In particular, when miniaturization is required and the SAC technique is used, it is difficult to secure a margin between the gate electrode and the tungsten film or plug in the contact hole due to the thinning of the silicon nitride film. However, by applying the present invention, a margin between them can be secured. Further, if a margin between them can be secured, high integration of the semiconductor integrated circuit device can be achieved.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view of a substrate, illustrating a method for manufacturing a semiconductor integrated circuit device according to Embodiment 1 of the present invention;

FIG. 2 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 3 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 8 is a diagram for explaining the effect of the present invention.

FIG. 9 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 10 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 11 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 12 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 13 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 14 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention;

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 element isolation groove 3 p-type well 4 n-type well 5 n-type well 6 silicon oxide film 7 silicon oxide film 8 gate oxide film 9a polycrystalline silicon film 9b WN film 9c W film 9 gate electrode 10 silicon nitride film 11 n-type semiconductor region 12 p-type semiconductor region 13 silicon nitride film 13a sidewall spacer 14 n-type semiconductor region 15 p-type semiconductor region 16 silicon oxide film 18 contact hole 19 contact hole 20 plug 21 silicon oxide film 22 contact hole 22a contact hole 27 Plug 30 Upper layer wiring 34 Silicon oxide film 38 Contact hole 39 Plug 40 Silicon nitride film 41 Silicon oxide film 42 Groove 43 Lower electrode 44 Capacitive insulating film 45 Upper electrode C Information storage capacitor Qn n-channel type MISF T Qp p-channel type MISFET Qs for memory cell selection MISFET WL the word line

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H01L 27/092 H01L 27/08 321F 27/108 27/10 621C 21/8242 681A 29/43 29/62 G 21/336 29/78 301Y (72) Inventor Takashi Aoyagi 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Within the Semiconductor Group, Hitachi, Ltd. (72) Daisuke Saito 5--20, Josuihoncho, Kodaira-shi, Tokyo No. 1 F-term in Hitachi, Ltd. Semiconductor Group F-term (reference) 4M104 BB01 BB18 CC01 CC05 DD02 DD07 EE05 EE09 EE17 FF08 FF13 FF18 GG09 GG10 GG14 GG16 HH20 5F033 HH04 HH19 HH34 JJ04 JJ19 KK01 MM04Q05 NN04Q05 QQ11 QQ16 QQ18 QQ25 QQ28 QQ31 QQ33 QQ37 QQ48 RR04 RR06 SS11 TT08 VV06 VV16 XX31 5F040 DA00 DA14 DB01 DC01 EA08 EC01 EC02 EC04 EC07 EC12 EC19 EF02 EH02 EH08 EJ03 EK05 FA07 CB02 FC01 FC01 FC02 BC06 BE03 BF00 BF03 BF07 BF11 BF12 BF15 BF16 BG13 DA27 5F083 AD01 AD10 AD24 AD61 JA06 JA39 JA40 KA01 MA06 MA17 MA19 NA01 PR03 PR12 PR29 PR40

Claims (5)

[Claims] 1. A gate electrode formed on a semiconductor substrate between a source and a drain via a gate insulating film, wherein: (a) a source and a drain formed in the semiconductor substrate; A semiconductor integrated circuit device comprising: a gate electrode having an upper portion having a tapered side wall; and (c) an insulating film formed on a side portion and an upper portion of the gate electrode. 2. A gate electrode formed on a semiconductor substrate between a source and a drain via a gate insulating film, wherein: (a) a source and a drain formed in the semiconductor substrate; (C) an insulating film formed on a side portion and an upper portion of the gate electrode; and (d) a plug formed on the source or the drain and in contact with the insulating film. A semiconductor integrated circuit device comprising: (A) a source and a drain formed in the semiconductor substrate; (b) a polycrystalline silicon film formed on the semiconductor substrate between the source and the drain via a gate insulating film; A barrier metal film formed on the polycrystalline silicon film;
A gate electrode formed of a tungsten film formed on the barrier metal film and having a tapered upper wall portion; (c) an insulating film formed on side and upper portions of the gate electrode; And a plug formed on the drain and in contact with the insulating film. 4. A process for forming a gate insulating film on a semiconductor substrate, a process for forming a conductive film on the gate insulating film, and a process for forming an insulating film on the conductive film. (D) patterning the insulating film into a desired shape; and (e) isotropically etching the part of the conductive film using the insulating film as a mask, and then etching the insulating film. A step of anisotropically etching the conductive film using the following as a mask; and (f) a step of introducing impurities into a semiconductor substrate using the insulating film and the conductive film as a mask. A method for manufacturing a circuit device. 5. A step of forming a gate insulating film on a semiconductor substrate, a step of forming a first conductive film on the gate insulating film, and a step of forming a first conductive film on the gate insulating film. Forming a first insulating film on the conductive film; (d) patterning the first insulating film into a desired shape; and (e) forming the first insulating film using the first insulating film as a mask. (F) etching the first conductive film anisotropically using the insulating film as a mask after isotropically etching a part of the conductive film; and (f) the insulating film and the first conductive film. Forming source and drain regions by introducing impurities into the semiconductor substrate using the film as a mask; and (g) forming a source and drain region that covers the upper and side surfaces of the first conductive film and extends over the source and drain regions. (H) forming a third insulating film on the second insulating film; Forming a film; and (i) etching the third insulating film on the source or drain region by using an etching rate difference from the second insulating film to form a second insulating film on the semiconductor substrate. Forming a contact hole reaching a source or drain region by etching the exposed second insulating film after exposing the surface of the insulating film, and (j) forming a second conductive film in the contact hole. Forming a plug by embedding a conductive film. A method for manufacturing a semiconductor integrated circuit device, comprising: