JP2001326335A - Field effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a FET which is equipped with an electrode for electric field control of high output and operating with high efficiency and whose distortion property is improved. SOLUTION: In a FET which has a gate electrode 5, a source electrode 7, and a drain electrode 8, an RC circuit consisting of a resistor 11 and a MIM capacitor 10 is provided in series between a gate bus bar 4 for collecting gate electrode fingers and an electrode bus bar 12 for electric field control for collecting electrodes 9 for electric field control, and the gate electrode bus bar 4 and the electrode bus bar 12 for electric field control are connected with each other. A resistor 11 attenuates the amplitude of the voltage of the electrode 9 for electric field control less than the amplitude of the voltage of the gate electrode 5, and the capacitor blocks the DC voltage between the electrode 9 for electric field control and the gate electrode 5, and bias can be applied independent of the gate electrode 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a field effect transistor (FET), and more particularly to an FET having an electric field control electrode.

[0002]

2. Description of the Related Art In a field effect transistor (FET), it is important to reduce distortion in addition to increasing output and efficiency. One method for increasing the output is to improve the breakdown voltage characteristics. An FET structure in which an electric field control electrode is provided to achieve high withstand voltage characteristics is disclosed in Japanese Patent Application No. 2000-39.
No. 19 publication. FIG.
FIG. 1 shows a plan view of a conventional FET structure described in Japanese Patent No. 3919. This structure includes a gate pad 3, a gate electrode bus bar 4, a gate electrode 5, and an electric field control electrode 9.
And a source electrode 7 and a drain electrode 8.
The electric field controlling electrode 9 is disposed on the insulating film 6 between the gate electrode 5 and the drain electrode 8. The electric field controlling electrode 9 disperses or alleviates the electric field concentrated on the end of the gate electrode, so that high withstand voltage characteristics can be obtained. High output F
For ET applications, it is desirable to connect the electric field control electrode to the gate electrode and keep it at the same potential. That is, when the gate voltage is applied to the pinch-off side, the electric field control electrode effectively improves the withstand voltage characteristic by the electric field relaxation effect,
Conversely, when a gate voltage is applied to the forward side to reduce the depletion layer and open the channel, lower the resistance of the channel,
Achieve high efficiency operation.

[0003]

However, this structure can provide high withstand voltage characteristics and high efficiency characteristics by lowering the resistance of the channel, but cannot improve the distortion characteristics. This will be described with reference to the drawings. FIG. 4 is a diagram showing a comparison of AM-AM (amplitude-amplitude) characteristics. Normal MESF
When an electric field control electrode is provided in a device such as an ET, and the electric field control electrode is set to the same potential as the gate electrode and operated with a bias setting of class B to class AB operation, the characteristic often shows that the gain expands. . This is due to the transfer characteristic (g
This is caused by an increase in gain due to the non-linearity of m) or an increase in gain due to a decrease in C _gs in the low V _ds region. On the other hand, in a normal MESFET having no electrode for electric field control, particularly, the AM-AM characteristic of a device with a high withstand voltage is such that the channel between the gate electrode and the drain electrode is RF.
Inability to track signals causes channel constriction,
The characteristics are degraded and gain compression occurs.

FIG. 3 shows a change in IV characteristics due to the effect of channel constriction during RF operation. In a normal MESFET without an electric field control electrode, the drain current decreases due to the narrowing of the channel, the output and the efficiency decrease, and a remarkable compression of the gain occurs as shown in FIG.
The distortion characteristics also deteriorate significantly. On the other hand, in an FET in which an electric field control electrode is provided and operated at the same potential as the gate electrode, channel constriction is alleviated and the gain in the low _Vds region is increased. Indicates pansion. Therefore, operating the electric field control electrode at the same potential as the gate electrode is very effective for high output and high efficiency, but is not suitable for low distortion.

Therefore, in order to solve the above problems,
SUMMARY OF THE INVENTION It is an object of the present invention to provide an FET that includes an electric field control electrode that operates with high output and high efficiency and simultaneously improves distortion characteristics.

[0006]

According to a first aspect of the present invention, there is provided a field effect transistor having an electric field control electrode disposed between a gate electrode and a drain electrode. The gate electrode and the electric field control electrode are connected via an RC series circuit.

According to a second aspect of the present invention, in a field effect transistor having an electric field control electrode between a gate electrode and a drain electrode, the gate electrode and the electric field control electrode are connected via a resistor. Connected.

[0008]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a plan view of a high-output FET according to a first embodiment of the present invention. FIG.
1 is a schematic diagram of an FET circuit according to a first embodiment. As shown in FIG. 1, the field-effect transistor according to the present embodiment includes a gate pad 3, a gate electrode bus bar 4, a gate electrode 5, a source electrode 7, a drain electrode 8, an electric field control electrode 9, The electric field control electrode bus bar 12 and the MI
It comprises an M (Metal Insulator Metal) capacitor 10 and a resistor 11. In the conventional FET structure, the gate electrode and the electric field control electrode are directly connected. However, in the FET structure according to the present invention, the resistor 11 and the MIM capacitor 10 are provided between the gate electrode 5 and the electric field control electrode 9. They are provided in series and connected via these.

FIG. 6 is a sectional view taken along the line AA 'of FIG.
As shown in FIG. 6, this cross-sectional structure is
, A channel layer 2, a gate electrode 5, an insulating film 6, a source electrode 7, a drain electrode 8, and an electric field control electrode 9. On a channel layer 2 provided on a GaAs substrate 1, a gate electrode 5, a source electrode 7, and a drain electrode 8
And are arranged. An insulating film 6 is formed to cover the channel layer 2, the gate electrode 5, the source electrode 7, and the drain electrode 8. An electric field control electrode 9 is disposed on the insulating film 6 between the gate electrode 5 and the drain electrode 8.

Next, referring to FIG. 1, the gate electrode 5 is combined with the gate electrode bus bar 4. On the other hand, the electric field control electrode 9 straddles the gate electrode bus bar 4 and is integrated by the electric field control electrode bus bar 12. Although not shown, the source electrode 7 is connected to the ground on the back surface via a via hole. Gate electrode bus bar 4
Are pulled out to the gate pad 3 like a normal FET, connected by a bonding wire or the like, a gate bias is supplied, and an RF signal is input. Although not shown, the drain electrode 8 is combined by a drain electrode pad, connected by a bonding wire or the like, supplied with a drain bias, and outputs an RF signal.

According to the present invention, the electric field control electrode bus bar 12 is made of, for example, a resistor 11 such as an epi-resistor, WSiN, tungsten nitride, titanium nitride, or WSi.
Connected to The resistance of the resistor 11 is determined, for example, within a range from several ohms to several hundred ohms so as to control the amplitude of the voltage input to the electric field control electrode. An MIM capacitor 10 is connected in series between the resistor 11 and the gate pad 3. The MIM capacitor 10 blocks a DC voltage between the gate electrode 4 and the electric field control electrode 9 and transmits an RF signal. By using such a structure, the potential of the electric field control electrode 9 can be controlled independently of the gate electrode 5. In addition, the upper electrode of the MIM capacitor 10 can be connected to a DC power supply independent of the gate via a bonding wire, an RF cut, or the like, and in some cases, can be made floating without determining the DC voltage.

When the DC voltage between the gate electrode 5 and the electric field control electrode 9 can be selected to be the same, the MIM capacitor 10 is not necessary. What is necessary is just to connect with the gate pad 3.

In such a structure, the amplitude of the voltage of the electric field control electrode can be adjusted during the RF operation, and the amount of channel constriction can be controlled. That is, when the resistance value of the resistor 11 is set low, the amplitude of the voltage of the electric field control electrode 9 is large, and the effect of reducing the resistance of the channel is large. As a result, as shown in FIG. Shows the expansion. On the other hand, when the resistance value is set high, the amplitude of the voltage of the electric field control electrode is suppressed, and the expansion of the gain is suppressed. On the other hand, when the DC bias of the electric field control electrode 9 is set deeper than the gate, the transconductance (gd) is suppressed, and the reduction in the channel resistance is also suppressed. Conversely, when the depth is set shallower than the gate bias, the effect of lowering the channel resistance is increased. Therefore, expansion or compression in AM-AM can be controlled by setting the bias.

FIG. 7 shows a second embodiment of the FET of the present invention. In the structure of the second embodiment, the gate electrode 5
, A source electrode 7, a drain electrode 8, and a gate electrode bus bar 4 for collecting the gate electrode 5, an electric field control electrode 9, a resistor 11, and a gate pad 3.

Next, although not shown, the source electrode 7 is connected to the ground on the back surface via a via hole.
The gate electrode bus bar 4 is drawn out to the gate pad 3 similarly to a normal FET, is connected by a bonding wire or the like, and receives a gate bias and an RF signal. Although not shown, the drain electrode 8 is combined by a drain electrode pad, connected by a bonding wire or the like, supplied with a drain bias, and outputs an RF signal.

Next, the resistor 11 is disposed between the gate electrode bus bar 4 and the electric field control electrode 9. Since the second embodiment corresponds to the case where the DC potentials of the electric field control electrode 9 and the gate electrode 5 are selected to be the same, the MIM capacitor as in the first embodiment is not required. Therefore, the present embodiment is different from the first embodiment in that the electric field control electrode bus bar and the portion over the gate bus bar by the air bridge can be omitted. The resistor 11 is, for example, an epi-resistor, WSi
It is made of a resistor such as N, tungsten nitride, titanium nitride, or WSi, and is determined, for example, within a range of several ohms to several hundred ohms so as to control the amplitude of the voltage input to the electric field control electrode.

With such a structure, the amplitude of the voltage of the electric field control electrode during the RF operation is adjusted, and the amount of channel constriction can be controlled. That is, when the resistance value of the resistor 11 is set low, the amplitude of the voltage of the electrode 9 for electric field control is large, and the resistance of the channel is reduced. As a result, as shown in FIG. Show John. On the other hand, when the resistance value is set high, the amplitude of the voltage of the electric field control electrode is suppressed, and the expansion of the gain is suppressed. Further, when the DC bias of the electric field control electrode 9 is set deeper than the gate, gd is suppressed and the reduction in the resistance of the channel is also suppressed. Conversely, when the depth is set shallower than the gate bias, the resistance of the channel is reduced. Therefore, expansion or compression in AM-AM can be controlled by setting the bias.

[0018]

As described above, the present invention can control the frequency dispersion characteristic of the transfer characteristic (gm) of the FET having the electric field control electrode, thereby reducing the intermodulation distortion caused by the nonlinearity of gm. The effect that such distortion characteristics can be improved is obtained. The reason is that, in the present invention, in a FET having a gate electrode and an electric field control electrode, the gate electrode and the electric field control electrode are connected via an RC circuit without being directly connected. The resistor in this RC circuit attenuates the amplitude of the voltage of the electric field control electrode more than that of the gate electrode, and the capacitor disconnects the DC voltage between the electric field control electrode and the gate electrode, This allows the bias to be applied independently.

[Brief description of the drawings]

FIG. 1 is a plan view of an FET according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram of an FET according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a change in I _{ds with} respect to a voltage of V _ds .

FIG. 4 is a diagram showing a comparison of AM-AM characteristics.

FIG. 5 is a plan view of a conventional FET having an electric field control electrode.

FIG. 6 is an AA ′ of the FET according to the first embodiment of the present invention.
It is sectional drawing.

FIG. 7 is a plan view of an FET according to a second embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Channel layer 3 Gate pad 4 Gate electrode bus bar 5 Gate electrode 6 Insulating film 7 Source electrode 8 Drain electrode 9 Electric field control electrode 10 MIM capacitor 11 Resistor 12 Electric field control electrode bus bar

Claims (8)

[Claims] 1. A field effect transistor having an electric field control electrode disposed between a drain electrode and a gate electrode, wherein the gate electrode and the field effect electrode are connected via an RC series circuit. Characteristic field effect transistor. 2. The field effect transistor according to claim 1, wherein said RC series circuit comprises a resistor and an MIM capacitor. 3. The field effect transistor according to claim 2, wherein the resistor attenuates the amplitude of the voltage applied to the electric field control electrode from the amplitude of the voltage applied to the gate electrode. 4. The MIM capacitor according to claim 2, wherein a DC voltage between the field effect electrode and the gate electrode is blocked, and a bias can be applied independently of the gate electrode. 4. The field effect transistor according to 3. 5. The resistor according to claim 2, wherein said resistor is an epi-resistor, a WSiN resistor, a tungsten nitride resistor, a titanium nitride resistor, or a WSi resistor.
Or the field-effect transistor according to 4. 6. A field effect transistor having an electric field control electrode disposed between a drain electrode and a gate electrode, wherein the gate electrode and the electric field control electrode are connected via a resistor. Characteristic field effect transistor. 7. The field effect transistor according to claim 6, wherein the resistor attenuates the amplitude of the voltage to the electric field control electrode from the amplitude of the voltage of the gate electrode. 8. The field effect transistor according to claim 6, wherein said resistor is an epi-resistor, a WSiN resistor, a tungsten nitride resistor, a titanium nitride resistor, or a WSi resistor.