JPH0945868A - High-frequency signal control semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-frequency signal control semiconductor integrated circuit whose output signals are less deformed in waveform. SOLUTION: Both the drains of a first FET 3 and a second FET 4 are connected to a first signal terminal 1, and the sources are connected to a second signal terminal 2. Both, gates of the first FET 3 and the second FET 4 are connected to a control terminal 5. High-frequency signals transmitted between the first signal terminal 1 and the second signal terminal 2 are controlled in amplitude by a voltage applied to a control terminal 5. A voltage between the gate and source of each FET is varied by high-frequency signals, and the FETs are different from each other in threshold value, so that resistance varies less between the drains and sources of the FETs than between the drain and source of the single FET. Therefore, output signals are less deformed in waveform.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a mobile communication device,
In particular, the present invention relates to a high frequency signal controlling semiconductor integrated circuit used in a mobile phone or the like.

[0002]

2. Description of the Related Art In recent years, there has been a demand for a high-frequency variable attenuator that is small in size and has low power consumption for controlling the reception level of a mobile phone or the like and the power amplifier input level. Variable resistance elements such as SiPIN diodes and field effect transistors (hereinafter abbreviated as FET) are used for the variable attenuator. In recent years, particularly, they have excellent high frequency characteristics, have extremely low power consumption, and are highly integrated. There is a trend toward the use of GaAs FETs, which are characterized by their miniaturization.

A conventional high frequency signal controlling semiconductor integrated circuit having a function as a variable attenuator will be described. FIG. 6 is a circuit diagram showing a conventional semiconductor integrated circuit for controlling high frequency signals. In FIG. 6, 1 is the first signal terminal,
2 is a second signal terminal, 5 is a control terminal, and the first signal terminal 1 and the second signal terminal 2 are, for example, impedance 5
It is connected to a high-frequency transmission line of 0Ω. 10 is a FET
And here is a normally-on type GaAs MESF.
ET is used. The FET 10 has a gate connected to the control terminal 5, a drain connected to the first signal terminal 1, and a source connected to the second signal terminal 2.

The operation of the conventional semiconductor integrated circuit for controlling high frequency signals shown in FIG. 6 will be described. The voltage applied to the control terminal 5 is applied to the gate of the FET 10. Therefore, the resistance value between the drain and the source of the FET 10 is sequentially applied to the control terminal 5 from 0 V to a voltage equal to or lower than the threshold voltage of the FET 10, so that the resistance value when the FET 10 is in the conductive state (hereinafter referred to as ON resistance (Hereinafter abbreviated) to a resistance value (hereinafter abbreviated as off resistance) when it is in a non-conductive state. Therefore, the transmission amount of the high frequency signal transmitted between the first signal terminal 1 and the second signal terminal 2 can be controlled by the voltage value applied to the control terminal 5.

[0005]

However, the conventional semiconductor integrated circuit for controlling a high frequency signal has the following problems.

In the conventional semiconductor integrated circuit for controlling high frequency signals, the gate voltage of the FET 10 is constant according to the voltage applied to the control terminal 5, but the drain voltage of the FET 10
Since a high frequency signal is transmitted between the sources, the source voltage is changed by this high frequency signal. That is, F
The gate-source voltage V _gs that determines the drain-source resistance value of the ET 10 is modulated by the transmitted high frequency signal.

Particularly, when a voltage close to the threshold voltage of the FET 10 is applied to the control terminal 5 and the drain-source resistance has a large value close to the off resistance, the drain is caused by the modulation of the gate-source voltage V _gs. -The source-to-source resistance will fluctuate significantly. As a result, a large distortion occurs in the output signal waveform. Distortion of the output signal waveform is not preferable because it causes a great bit error rate and deteriorates communication quality in, for example, a digital mobile phone.

In view of the above problems, it is an object of the present invention to provide a high frequency signal controlling semiconductor integrated circuit in which the distortion of the output signal waveform is small.

[0009]

To achieve the above object, the present invention comprises a plurality of field effect transistors having different threshold voltages and having a gate, a source and a drain connected in common. It is a thing.

Specifically, the means for solving the problems according to the invention of claim 1 is intended for a semiconductor integrated circuit for controlling a high frequency signal, and is provided with a plurality of field effect transistors each having a different threshold voltage, and the sources of the plurality of field effect transistors. And the gates and the drains are commonly connected to each other, and the amplitude of the high-frequency signal transmitted between the common source and the common drain is controlled by the voltage applied to the common gate. It is what

According to the structure of the first aspect of the present invention, the high frequency signal transmitted between the source and the drain of the field effect transistors connected in common is the field effect transistors connected in common. Its amplitude is controlled by the voltage applied to its gate. At this time, even if the gate-source voltage of each field-effect transistor fluctuates due to a high-frequency signal, the threshold voltage of each field-effect transistor is different, so there is a difference between the commonly connected source and the commonly connected drain. The variation of the resistance value is smoother than that of the conventional circuit including one field effect transistor.

According to a second aspect of the present invention, in addition to the configuration of the first aspect, the plurality of field effect transistors have the same channel profile and different gate lengths.

According to the structure of the second aspect of the present invention, a plurality of field effect transistors having different threshold voltages can be formed on the same substrate simply by changing the mask layout without increasing the number of manufacturing steps.

According to a third aspect of the present invention, in the structure of the first aspect, the plurality of field effect transistors are formed on a (100) crystal plane of a compound semiconductor substrate and have the same channel profile. Moreover, a configuration is added in which the major axis direction of the gate electrode and the <0-1-1> direction make different angles.

According to the third aspect of the invention, a plurality of field effect transistors having different threshold voltages can be formed on the same substrate by simply changing the mask layout without increasing the number of manufacturing steps.

[0016]

1 is a circuit diagram of a semiconductor integrated circuit for controlling a high frequency signal according to an embodiment of the present invention. In FIG. 1, 1 is a first signal terminal, 2 is a second signal terminal, 5
Is a control terminal, and the first signal terminal 1 and the second signal terminal 2 are connected to a high frequency transmission line. 3 is the first F
ET and 4 are second FETs, both of which are normally-on type MESFETs formed on a GaAs substrate. The electrodes of the first FET 3 and the second FET 4 are connected to a common terminal, the drains are both connected to the first signal terminal 1, and the sources are both connected to the second signal terminal 2. The gates are both connected to the control terminal 5.

The threshold voltage of the first FET 3 is different from that of the second FET 4, and the threshold voltage of the first FET 3 is -2.
V, the threshold voltage of the second FET 4 is -2.5V. Further, the sum (W _g1 + W _g2 ) of the gate width W _g1 of the first FET 3 and the gate width W _g2 of the second FET 4 is 1.2 mm.
It is formed to become.

FIG. 2 is a graph showing the distortion characteristic of the circuit shown in FIG. 1, in which the third-order intermodulation distortion IM3 is plotted based on the measurement result by the two-tone method. In FIG. 2, the vertical axis represents the third-order intermodulation distortion IM3 (dBc), and the horizontal axis represents the gate width (W _g1 / (W _g1 + W _g2 )) of the first FET 3 with respect to the total gate width. The frequencies of the two signals given in the measurement are 0.990 GHz and 1.01 GHz.
Hz and the signal level is -3 dBm, respectively.

As shown in FIG. 2, W _g1 / (W _g1 + W _g2 )
= 1 (that is, the circuit shown in FIG.
IM3 is -1.
It is about 4 dBc. Also, W _g1 / (W _g1 + W _g2 ) = 0
Also (that is, when the circuit shown in FIG. 1 is composed of only the second FET 4), the third-order intermodulation distortion IM3 is −14.
It is about dBc. However, the first FET 3 and the second FET 3
The third-order intermodulation distortion IM3 is improved to about −18 dBc by connecting the FETs 4 in parallel with each other and setting W _g1 / (W _g1 + W _g2 ) to 0.2 to 0.5.

As can be seen from the above experimental facts, the distortion in the output signal waveform is reduced by connecting the FETs having different threshold voltages in parallel. This mechanism will be described with reference to FIG.

FIG. 3 is a graph schematically showing the relationship between the gate-source voltage and the drain current in the FET. In FIG. 3, the vertical axis represents the drain current, and the horizontal axis represents the gate-source voltage. The broken line on the right is the first FE
It is a curve showing the characteristic of T3, and shows that the drain current flows when the gate-source voltage exceeds the threshold voltage V _th1 . The broken line on the left side is a curve showing the characteristics of the second FET 4, and shows that the drain current flows when the gate-source voltage exceeds the threshold voltage V _th2 . The solid line is a curve showing the characteristics of the circuit according to the present embodiment in which the first FET 3 and the second FET 4 are connected in parallel.

As described in the section of the problem, the cause of the distortion of the output signal waveform in the high frequency signal controlling semiconductor integrated circuit is that the high frequency signal to be transmitted modulates the gate-source voltage. Especially when the control voltage is FE
When the voltage is set near the threshold voltage of T, the gate-source voltage is modulated at the portion where the bending of the FET characteristic curve is the largest, so that the distortion in the output signal waveform becomes very large. It can be considered that the magnitude of this distortion corresponds to the angle (θ ₁ and θ ₂ ) that the characteristic curve of the FET makes with the gate-source voltage axis at the threshold voltage.

This angle usually hardly changes even if the threshold voltage of the FET is different. Therefore, a single FET
When using, the distortion in the output signal waveform does not change much even if the threshold voltage is different. However, when two FETs having different threshold voltages are connected in parallel, the bending angle of the characteristic curve becomes small as shown by the solid line in FIG. Therefore, the circuit according to the present embodiment reduces distortion in the output signal waveform.

FIG. 4 is a sectional structural view showing an example of the device structure of the semiconductor integrated circuit according to this embodiment. In FIG. 4, 6 is a semi-insulating GaAs substrate, and semi-insulating GaA
The first FET 3 and the second FET 4 are formed on the s substrate 6. The first FET 3 is the source / drain region 3
1, a gate electrode 32, and an n-type channel layer 33, and the second FET 4 includes a source / drain region 41, a gate electrode 42, and an n-type channel layer 43. The gate electrodes 32 and 42 are formed by, for example, Al vapor deposition.

The first FET 3 and the second FET 4 have the same channel profile but different gate lengths. Here, the gate length of the first FET 3 is 1 μm and the gate length of the second FET 4 is 0. It is set to 5 μm. Second
Since the short-channel effect of the FET 4 becomes more remarkable than that of the first FET 3, the threshold voltage shifts to the negative side.
That is, the FETs having different threshold voltages can be formed only by the mask layout without increasing the number of manufacturing steps. By connecting the first FET 3 and the second FET 4 in parallel, a circuit as shown in FIG. 1 can be configured and distortion in the output signal waveform can be reduced.

FIG. 5 is a plan view showing another example of the device structure of the semiconductor integrated circuit according to this embodiment. In FIG. 5, the first FET 3 and the second FET 4 are formed on the (100) crystal plane of the GaAs substrate. First FET
3 has a source / drain region 31 and a gate electrode 32, and the second FET 4 has a source / drain region 41.
And the gate electrode 42, and the channel profiles of the first FET 3 and the second FET 4 are the same.

Here, the gate electrode 32 of the first FET 3
Is formed to be parallel to the <0-1-1> direction, and the long axis direction of the gate electrode 42 of the second FET 4 is perpendicular to the <0-1-1> direction. Is formed. In this case, the second FET 4 is the first FET 3
The threshold voltage shifts to the more negative side. That is, the FETs having different threshold voltages can be formed only by the mask layout without increasing the number of manufacturing steps. By connecting the first FET 3 and the second FET 4 in parallel, a circuit as shown in FIG. 1 can be configured and distortion in the output signal waveform can be reduced.

In this embodiment, a circuit in which two FETs are connected in parallel has been described as an example, but two or more FEs are connected.
It goes without saying that connecting T in parallel further improves the characteristics in the vicinity of the threshold voltage and further reduces the distortion in the output signal waveform.

[0029]

According to the semiconductor integrated circuit for controlling a high frequency signal of the first aspect of the present invention, even if the gate-source voltage of each field effect transistor constituting the circuit fluctuates due to the high frequency signal, they are connected in common. Since the fluctuation of the resistance value between the source and the drain connected in common is smoother than that of the conventional circuit including one field effect transistor, the waveform distortion of the transmitted high frequency signal is smaller than that of the conventional one. can do.

According to the semiconductor integrated circuit for controlling a high frequency signal of the second aspect of the present invention, a plurality of field effect transistors having different threshold voltages are formed on the same substrate only by changing the mask layout without increasing the number of manufacturing steps. Since it can be formed, it is possible to easily realize a semiconductor integrated circuit for controlling a high-frequency signal in which the distortion of the waveform of the transmitted high-frequency signal is smaller than before.

According to the semiconductor integrated circuit for controlling a high frequency signal of the third aspect of the invention, a plurality of field effect transistors having different threshold voltages are formed on the same substrate only by changing the mask layout without increasing the number of manufacturing steps. Since it can be formed, it is possible to easily realize a semiconductor integrated circuit for controlling a high-frequency signal in which the distortion of the waveform of the transmitted high-frequency signal is smaller than before.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a semiconductor integrated circuit for controlling a high frequency signal according to an embodiment of the present invention.

FIG. 2 is a graph showing distortion characteristics of the circuit shown in FIG.

FIG. 3 is a graph for explaining a mechanism of improving distortion characteristics according to the present invention.

FIG. 4 is a sectional structural view showing an example of a device structure of a semiconductor integrated circuit for controlling a high frequency signal according to an embodiment of the present invention.

FIG. 5 is a plan view showing an example of a device structure of a semiconductor integrated circuit for controlling a high frequency signal according to an embodiment of the present invention.

FIG. 6 is a circuit diagram showing a conventional high-frequency signal control semiconductor integrated circuit.

[Explanation of symbols]

 1 1st signal terminal 2 2nd signal terminal 3 1st FET 4 2nd FET 5 Control terminal 6 Semi-insulating GaAs substrate 10 FET 31 Source / drain region 32 Gate electrode 33 n-type channel layer 41 Source / drain Region 42 Gate electrode 43 n-type channel layer

Claims (3)

[Claims] 1. A plurality of field effect transistors each having a different threshold voltage, wherein sources, gates, and drains of the plurality of field effect transistors are commonly connected to each other, and the common source and common drain are connected to each other. A semiconductor integrated circuit for controlling a high-frequency signal, characterized in that the amplitude of a high-frequency signal transmitted between and is controlled by a voltage applied to the common gate. 2. The semiconductor integrated circuit for controlling a high frequency signal according to claim 1, wherein the plurality of field effect transistors have the same channel profile and different gate lengths. 3. The plurality of field effect transistors are formed on a (100) crystal plane of a compound semiconductor substrate, have the same channel profile, and have a <0-1-1> in the major axis direction of the gate. The semiconductor integrated circuit for controlling a high frequency signal according to claim 1, wherein the angles formed by the directions are different from each other.