JPH08330332A - Semiconductor device - Google Patents

Abstract

PURPOSE: To prevent parasitic oscillation in a high output FET transistor. CONSTITUTION: In a FET transistor where a Schottky connection gate electrode 4 is provided on an n-type conductive layer 1 along with source and gate electrodes 2, 3 of ohmic connection, the gate electrode 4 has resistance of 100Ω/cm or less per unit length and length in the range of 130-400μm in the direction of channel width. Maximum effective power gain is lowered in the frequency range of 28 GHz or above and the parasitic oscillation is suppressed without lowering the maximum stabilized power gain of a high output FET transistor in the operating band i.e., 500MHz-28GHz.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a high output field effect transistor.

[0002]

2. Description of the Related Art Conventionally, high-power field-effect transistors have been used in satellite repeaters, etc.
High reliability is required. FIG. 3 is a plan layout diagram of a conventional high-output field-effect transistor. The drain electrode 12 and the source electrode 13, which are electrodes that are ohmic-connected to the n-type gallium arsenide conductive layer 11, and the gate electrode that is Schottky-connected. 14 and 14 are alternately arranged in parallel. The drain pad 15, the source pad 16, and the gate pad 17 are connected to the electrodes, respectively, and are connected to external wiring.

In the conventional high output field effect transistor having such a structure, in order to obtain a high power gain, the length of a plurality of gate electrodes arranged in parallel (hereinafter referred to as gate fingers) is 80 μm to 125 μm. Is designed to range. The material of the gate finger is a metal having a resistance per unit length of 100 Ω / mm or less, such as WSi.
A metal such as / Au was used.

[0004]

In this conventional high output field effect transistor, a positive feedback parasitic oscillation occurs via a gate finger at a frequency other than the operating frequency, particularly in the range of 50 GHz to 60 GHz, and as a amplifying element, There was a case where the function was deteriorated.

[0005]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a high output field effect transistor which prevents the occurrence of such parasitic oscillation.

[0006]

According to the present invention, a gate electrode Schottky-connected on an n-type conductive layer has a resistance per unit length of 100 Ω / cm or less and a length in a channel width direction. Is in the range of 130 μm to 400 μm.

Here, at least the gate electrode is formed on the n-type conductive layer formed to have a predetermined width, with both ends protruding from the region of the conductive layer. Also,
A plurality of gate electrodes are arranged between a plurality of source electrodes and drain electrodes arranged in parallel, and the plurality of gate electrodes are connected to the same gate pad at one end thereof,
The length of the gate electrode is the length from the gate pad to the other end.

[0008]

[Function] The length of the gate electrode is 130 μm to 400 μm
Setting the range to lowers the maximum available power gain in the frequency range of 28 GHz or higher, suppresses parasitic oscillation, and maximizes the maximum output in the range of 500 MHz to 28 GHz, which is the high-power field-effect transistor use band. The stable power gain will not be reduced.

[0009]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a plan view of a high output field effect transistor showing an embodiment of the present invention. In the figure, 1 is an n-type gallium arsenide conductive layer formed on a semiconductor substrate,
A drain electrode 2 and a source electrode 3 forming an ohmic connection with the n-type gallium arsenide conductive layer 1 are alternately arranged in parallel on the surface thereof. A gate electrode 4 forming a Schottky junction with the n-type gallium arsenide conductive layer 1 is arranged between the drain electrode 2 and the source electrode 3, respectively. The electrodes 2, 3 and 4 are electrically connected to the drain pad 5, the source pad 6 and the gate pad 7, respectively, and to the external wiring.

The plurality of gate electrodes 4 arranged in parallel, that is, the gate fingers 4, have a resistance per unit length of 100 Ω / mm or less, and the direction of the current flowing through the n-type gallium arsenide conductive layer 1. The vertical length is designed to be 150 μm. That is, this gate finger is formed of a metal layer having a resistance per unit length of 100 Ω / mm or less as in the conventional case, but the length is set to a value in the range of 130 μm to 400 μm, which is longer than the conventional case. doing.

Here, the gate finger 4 is configured such that both ends thereof are projected to both sides of the n-type gallium arsenide conductive layer 1 so as to straddle the n-type gallium arsenide conductive layer 1 formed as a region of a predetermined width. What is said is the same as a normal high output field effect transistor. The length of the gate finger 4 is the length from the gate pad 7 connected to one end to the other end.

As described above, by forming the gate finger 4 longer than before, parasitic oscillation due to positive feedback via the gate finger 4 which is generated in a frequency range of 28 GHz or higher is suppressed, and high output is achieved. A significant decrease in the maximum stable power gain, which is one of the performance indexes of the field effect transistor, is prevented in the band of use of the field effect transistor from 500 MHz to 28 GHz. The high output field effect transistor of this example has a maximum stable power gain of 15 dB at 10 GHz and a gate finger length of 1.
Similar to the case of 00 μm, and parasitic oscillation was suppressed in the frequency region of 50 GHz or higher.

FIG. 2 is a characteristic diagram for explaining this effect. The maximum stable power gain and the maximum available power gain of a high output field effect transistor having a resistance per unit length of 100 Ω / mm or less are frequency dependent. Showing sex. In this characteristic, the gate finger length Wu is 100 μm to 200 μm.
The maximum stable power gain in the range of 500 MHz to 28 GHz, which is the operating frequency band of the high output field effect transistor, does not decrease when the length is increased to 50 GHz
It can be seen that the maximum available power gain drops significantly at frequencies above Hz.

Conventionally, parasitic oscillation has occurred in 50
Although it was in the range of -60 GHz, the frequency was 50
The maximum effective power gain in the range from GHz to 60 GHz is lower than the maximum effective power gain when the gate finger length Wu is 100 μm (in this case, parasitic oscillation occurs) because the gate finger length is 130 μm. The lower limit of the gate finger length Wu that can suppress oscillation is 1
It becomes 30 μm.

Further, from FIG. 2, the same effect as described above can be obtained up to the range of the gate finger length Wu of 400 μm where the maximum stable power gain in the operating frequency band of the high output field effect transistor starts to decrease. Therefore, it can be seen that by setting the gate finger length Wu in the range of 130 μm to 400 μm, parasitic oscillation can be suppressed without reducing the maximum stable power gain in the used frequency band.

For example, in the present invention, the gate finger length is 3
Even when a high output field effect transistor of 50 μm is constructed, the maximum stable power gain at 10 GHz is 15 dB as in the case of the gate finger length of 150 μm.
Thus, parasitic oscillation is suppressed in the frequency range of 50 GHz or higher.

[0017]

As described above, the high output field effect transistor of the present invention has a gate electrode length of 130 μm.
By setting the range from m to 400 μm, the frequency becomes 2
The maximum available power gain in the range of 8 GHz or higher is reduced, parasitic oscillation is suppressed, and the maximum stable power gain is not reduced in the range of 500 MHz to 28 GHz, which is the operating band of the high output field effect transistor. The effect can be obtained.

[Brief description of drawings]

FIG. 1 is a plan layout view of an embodiment of a field effect transistor of the present invention.

FIG. 2 is a characteristic diagram of the maximum available power gain and the maximum stable power gain with the length of the gate finger as a parameter.

FIG. 3 is a plan layout diagram of an example of a conventional field effect transistor.

[Explanation of symbols]

 1 n-type gallium arsenide conductive layer 2 drain electrode 3 source electrode 4 gate electrode (gate finger) 5 drain pad 6 source pad 7 gate pad

Claims (3)

[Claims] 1. A semiconductor device comprising a high output field effect transistor having a gate electrode Schottky-connected on an n-type conductive layer and source and drain electrodes connected in ohmic contact, wherein the gate electrode is a unit. A semiconductor device having a resistance per length of 100 Ω / cm or less and a length in the channel width direction of 130 μm to 400 μm. 2. The semiconductor device according to claim 1, wherein at least the gate electrode is formed on an n-type conductive layer having a predetermined width, with both ends protruding from the region of the conductive layer. 3. A plurality of source electrodes and drain electrodes are alternately arranged in parallel, and a plurality of gate electrodes are provided between each source electrode and drain electrode. Is connected to the same gate pad at one end thereof, and the length of the gate electrode is the length from the gate pad to the other end.