JP2010034282A - Field-effect type transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a field-effect type transistor simply formed and having excellent characteristics. <P>SOLUTION: The field-effect type transistor has a source electrode 20 formed to an active region 40 and a drain electrode 30 formed to the active region 40. The field-effect type transistor incldues: a gate electrode 10 formed to the active region 40 and held between the source electrode 20 and the drain electrode 30; and an FP electrode 50 formed near the gate electrode 10 on the side outer than a region held between the gate electrode 10 and the source electrode 20. The field-effect type transistor further has a grounded FP pad 52 contained in the FP electrode 50 and formed outside the active region 40. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a field effect transistor.

With the advancement of communication technology, higher output and higher gain characteristics are required for high output field effect transistors (hereinafter referred to as “FETs”) used in amplification amplifiers. Such FET is disclosed in, for example, Patent Documents 1-3. Examples of the FET include a GaAs-FET and a Si-MOSFET, and in recent years, an FET made of GaN or SiC. In these FETs, attempts have been made to obtain high characteristics by optimizing the structure. For example, in order to obtain a high output during high voltage operation, a field plate (hereinafter referred to as “FP”) electrode structure for reducing current collapse by relaxing the electric field at the gate end is well known. . The FP electrode includes a “gate FP” connected to the gate and a “source FP” connected to the source. In particular, the source FP structure has an effect of reducing the gate-drain capacitance Cgd by cutting off the lines of electric force between the gate and the drain to reduce the capacitance Cgd between the gate and the drain (Faraday shield effect), and is useful for improving the gain.
JP 2006-245474 A JP 2006-286952 A JP 2002-94055 A

  Here, the FET having the source FP structure will be described with reference to FIGS. FIG. 7 is a plan view showing a configuration of an FET having a source FP structure. 8 is a sectional view taken along line VIII-VIII in FIG. Hereinafter, the “FP electrode” represents a “source FP” connected to a source.

  As shown in FIG. 7, the gate electrode 10, the source electrode 20, and the drain electrode 30 each have a finger in the active region 40. The gate finger 11, the source finger 21, and the drain finger 31 are formed in parallel to each other. The source finger 21 is formed between the two gate fingers 11. The FP electrode 50 is formed so as to cover the gate finger 11 in order to relax the electric field at the gate end. The FP electrode 50 is formed so as to be connected to the source electrode 20. Therefore, the FP electrode 50 is formed so as to cover the entire gate-source region. Specifically, the FP electrode 50 is formed between two gate fingers 11 sandwiching the source finger 21. The source finger 21 is grounded by a via hole 23 of the source pad 22. For this reason, the FP electrode 50 connected to the source electrode 20 is also grounded.

  As shown in FIG. 8, the FP electrode 50 is formed on the gate electrode 10 via an insulating film. The FP electrode 50 is formed so as to cover the gate electrode 10. As described above, the FP electrode 50 is grounded via the source electrode 20. By covering the gate electrode 10 with the grounded FP electrode 50, the electric lines of force between the gate and the drain are blocked. Such a Faraday shield effect can reduce the gate-drain capacitance Cgd. In other words, this increases the gain and improves the stability of the device. In addition, when the FP electrode 50 is loaded, the gate-drain electric field in the FET is dispersed from the gate end to the FP electrode 50 end. Thereby, the collapse characteristic, that is, the Po characteristic during high voltage operation can be improved.

  In the above configuration, the FP electrode 50 is formed so as to cover all the gate fingers 11 in the active region 40 in order to sufficiently connect the source electrode 20. For this reason, there is a problem that a parasitic capacitance Cgs between the gate and the source is generated and the gain is reduced.

  In order to solve this problem, there is an FET having a cross-sectional structure shown in FIG. 9 as a second prior art. FIG. 9 is a cross-sectional view showing a second configuration of the FET having the source FP structure. As shown in FIG. 9, a gap 80 is provided under the connection line between the FP electrode 50 and the source. Instead of the gap 80, a low dielectric constant film may be provided. Thereby, the parasitic capacitance Cgs is reduced. In order to obtain such a structure, it is necessary to go through a plurality of complicated processes, and formation is very difficult.

  On the other hand, as a third prior art, there is an FET having a planar pattern as shown in FIG. FIG. 10 is a plan view showing a third configuration of the FET having the source FP structure. As shown in FIG. 10, FP fingers 51 are formed in the vicinity of the gate fingers 11. Here, the FP finger 51 is a part of the FP electrode 50 and is a finger-like portion in the active region 40. Then, the FP fingers 51 are connected by the FP bridge 81. Here, the FP bridge 81 is a part of the FP electrode 50 and is a portion that connects the source finger 21 and the FP finger 51 so as to straddle the gate finger 11. That is, it is a planar pattern in which the FP electrode 50 between the gate finger 11 and the source finger 21 is partially opened. Thereby, the parasitic capacitance Cgs is reduced. However, the gate-source region is partially covered, and the influence on the gain of the parasitic capacitance Cgs in that portion is inevitable.

  Further, as a fourth prior art, there is an FET having a planar pattern as shown in FIG. FIG. 11 is a plan view showing a fourth configuration of the FET having the source FP structure. As shown in FIG. 11, the FP bridge 81 is formed only at the base and tip of the finger. Then, the FP electrode 50 and the source electrode 20 are connected only at the root and tip of the finger. However, even with the fourth prior art, the parasitic capacitance Cgs still remains, although it is reduced as compared with the third prior art. In addition, since the portion where the FP electrode 50 and the source electrode 20 are connected is reduced, there is a problem that the grounding property is deteriorated.

  Further, as a fourth prior art, there is an FET having a planar pattern as shown in FIG. FIG. 11 is a plan view showing a fourth configuration of the FET having the source FP structure. As shown in FIG. 11, the FP bridge 81 is formed only at the base and tip of the finger. Then, the FP electrode 50 and the source electrode 20 are connected only at the root and tip of the finger. However, even with the fourth prior art, the parasitic capacitance Cgs still remains, although it is reduced as compared with the third prior art. In addition, since the portion where the FP electrode 50 and the source electrode 20 are connected is reduced, there is a problem that the grounding property is deteriorated.

  A field effect transistor according to the present invention includes a source electrode formed in an active region, a drain electrode formed in the active region, and a gate formed in the active region and sandwiched between the source electrode and the drain electrode. An electrode, a field plate electrode formed in the vicinity of the gate electrode outside the region sandwiched between the gate electrode and the source electrode, and included in the field plate electrode, formed outside the active region, and grounded FP pad. Thereby, a field effect transistor having an FP (field plate) effect and a high RF gain can be provided without particularly complicating the manufacturing process.

  According to the present invention, it is possible to provide a field effect transistor that can be easily formed and has good characteristics.

Embodiment.
First, a field effect transistor (hereinafter referred to as “FET”) according to the present invention will be described with reference to FIGS. FIG. 1 is a plan view showing the configuration of the FET. 2 is a cross-sectional view taken along the line II-II in FIG. For example, the FET has a configuration in which a large number of units are arranged in an array on a semiconductor substrate 60. In FIG. 1, two adjacent units are illustrated. The FET can be used as a microwave amplifier or a power switching element.

  An active region 40 and a non-active region 41 provided outside the active region 40 are formed in the semiconductor substrate 60. The active region 40 is provided with a channel region, a source region, and a drain region. That is, the active region 40 is an operation region that can be operated as an FET. The FET has a gate electrode 10, a source electrode 20, and a drain electrode 30. These electrodes have a plurality of fingers. Specifically, in many units, these electrodes are each formed in a comb shape. In the active region 40, the plurality of gate fingers 11, the plurality of source fingers 21, and the plurality of drain fingers 31 are formed in parallel to each other. These fingers are formed so as to straddle the active region 40. Further, both ends of these fingers are formed so as to protrude into the inactive region 41. These are arranged in the order of the drain finger 31, the gate finger 11, the source finger 21, the gate finger 11, and the drain finger 31 in the active region 40. That is, in one unit, the gate finger 11 is sandwiched between the source finger 21 and the drain finger 31.

  The source finger 21 is formed on the source region of the active region 40. Source finger 21 extends from source pad 22 formed in inactive region 41. That is, one end (base) of the source finger 21 is connected to the source pad 22. The other end (tip) of the source finger 21 is positioned between a drain pad 32 described later and a tip-side FP pad 52 described later. That is, the source finger 21 is provided on the active region 40 side with respect to the drain pad 32 and is formed so as to straddle the front end side FP pad 52. The source finger 21 protrudes from the tip side FP pad 52 to the drain pad 32 side.

  In the non-active region 41, the tip side FP pad 52 and the tip part of the source finger 21 come into contact with each other. The source pad 22 is grounded by a via hole 23. Further, the source pad 22 is formed in a substantially rectangular shape, and a part thereof protrudes toward the active region 40 side. The protruding portion of the source pad 22 is formed corresponding to an FP finger 51 described later, and is in contact with a root-side FP pad 53 described later.

  The drain finger 31 is formed on the drain region of the active region 40. The drain finger 31 extends from the drain pad 32 formed in the inactive region 41. That is, one end (base) of the drain finger 31 is connected to the drain pad 32. Further, the other end (tip) of the drain finger 31 is located between the root side FP pad 53 and the active region 40. That is, the drain finger 31 is formed closer to the active region 40 than the root side FP pad 53. In other words, the drain finger 31 is not formed on the root side FP pad 53. The drain pad 32 is connected to the end of the drain finger 31 opposite to the source pad 22. That is, the active region 40 is sandwiched between the drain pad 32 and the source pad 22.

  The gate finger 11 is formed on the channel region of the active region 40. The gate finger 11 extends from the gate bus bar 12 formed in the inactive region 41. That is, one end (base) of the gate finger 11 is connected to the gate bus bar 12. The other end (tip) of the gate finger 11 is located between the tip side FP pad 52 and the active region 40. That is, the gate finger 11 is formed closer to the active region 40 than the tip side FP pad 52. In other words, the gate finger 11 is not formed so as to overlap the tip side FP pad 52. The gate bus bar 12 extends in a direction orthogonal to the extending direction of the gate fingers 11. The gate bus bar 12 is provided between the source pad 22 and the root side FP pad 53. The gate bus bar 12 is electrically connected to the gate pad 13 formed in the inactive region 41.

  In addition, a field plate (hereinafter referred to as “FP”) electrode 50 is formed in the FET according to the present embodiment. Here, the “FP electrode” represents a “source FP” connected to the source electrode. A part of the FP electrode 50 is formed in the vicinity of the gate finger 11. Further, this portion is formed in a finger shape in the active region 40, like the gate finger 11 and the like. In this specification, the portion of the FP electrode 50 formed in a finger shape is referred to as an FP finger 51. Specifically, the FP electrode 50 is formed in a substantially U-shape inside the two drain fingers 31. The FP finger 51 is provided on the gate finger 11 and between the gate finger 11 and the drain finger 31. The FP finger 51 extends so as to be parallel to the gate finger 11, the source finger 21, and the drain finger 31. The FP finger 51 is formed outside the region sandwiched between the gate finger 11 and the source finger 21. That is, the FP finger 51 is not formed between the adjacent gate finger 11 and the source finger 21.

  The FP finger 51 extends from the tip side FP pad 52 and the root side FP pad 53. Here, the FP pad means a connection portion of the FP electrode 50 with another electrode or the like. That is, the tip side FP pad 52 or the root side FP pad 53 is provided at both ends of the FP finger 51. The tip side FP pad 52 and the root side FP pad 53 are formed in the inactive region 41. The tip side FP pad 52 is formed on the tip side of the source finger 21. The front end side FP pad 52 is formed between the drain pad 32 and the gate finger 11. Further, the tip side FP pad 52 is formed between the two drain fingers 31. As described above, the tip side FP pad 52 is connected to the source finger 21. That is, the FP electrode 50 is grounded via the source electrode 20 by the front end side FP pad 52.

  The root side FP pad 53 is formed on the root side of the gate finger 11. The root side FP pad 53 is formed between the gate bus bar 12 and the drain finger 31. The root side FP pad 53 is formed corresponding to each FP finger 51. As described above, the root side FP pad 53 is connected to the protruding portion of the source pad 22. That is, the FP electrode 50 is grounded via the source electrode 20 by the root side FP pad 53. As described above, in the inactive region 41, the FP pads 52 and 53 are provided on the tip side of the source finger 21 and the base of the gate finger 11, respectively. Electrodes are connected to the FP pads 52 and 53 from the tip side of the source finger 21 and the source pad 22 at the base.

  As shown in FIG. 2, a source ohmic metal 61 and a drain ohmic metal 62 are formed on a semiconductor substrate 60 such as a GaAs substrate. The source ohmic metal 61 is formed on the source region of the active region 40. The drain ohmic metal 62 is formed on the drain region of the active region 40. The source ohmic metal 61 and the drain ohmic metal 62 are ohmically connected to the active region 40 of the semiconductor substrate 60. A first protective film 63 having insulating properties is formed on the source ohmic metal 61 and the drain ohmic metal 62. A gate electrode 10 is formed on the first protective film 63. An opening is formed in the first protective film 63 on the channel region of the active region 40, and the gate electrode 10 is buried in this opening. Thereby, the gate electrode 10 and the channel region are connected. The gate electrode 10 is formed in a substantially T shape.

  An insulating second protective film 64 is formed on the first protective film 63 so as to cover the gate electrode 10. On the second protective film 64, the source electrode 20, the drain electrode 30, and the FP electrode 50 are formed. An opening is formed in the first protective film 63 and the second protective film 64 on the source ohmic metal 61, and the source electrode 20 is buried. Thereby, the source electrode 20 and the source ohmic metal 61 are connected. An opening is formed in the first protective film 63 and the second protective film 64 on the drain ohmic metal 62, and the drain electrode 30 is buried. Thereby, the drain electrode 30 and the drain ohmic metal 62 are connected. Further, in the source electrode 20 and the drain electrode 30, both end portions in the width direction are formed away from the second protective film 64. That is, these electrodes have gaps between both end portions in the width direction and the second protective film 64.

  The FP electrode 50 is formed in the vicinity on the gate electrode 10 via the second protective film 64. Specifically, the FP electrode 50 is formed closer to the gate electrode 10 than the drain electrode 30. The FP electrode 50 is formed from a part of the gate electrode 10 toward the drain electrode 30 side. That is, the FP electrode 50 is formed so as to protrude from the part of the gate electrode 10 on the drain electrode 30 side to the drain electrode 30 side. In other words, the FP electrode 50 is formed on the gate electrode 10 and between the gate electrode 10 and the drain electrode 30 in a top view. Thereby, the Faraday shield effect can be acquired. Moreover, as long as the FP electrode 50 can obtain the FP effect, the formation position, shape, and the like of the FP electrode 50 are not particularly limited. If the effect of FP can be obtained, it may be formed only between the gate electrode 10 and the drain electrode 30, or may be formed only on the gate electrode 10, for example. The FP electrode 50 is formed so as not to protrude from the gate electrode 10 to the source electrode 20 side.

  Thus, in the FET according to the present embodiment, there is no portion where the gate-source region is covered with the FP electrode 50 in any portion in the active region 40. For this reason, the parasitic capacitance Cgs between the gate and the source can be reduced. And RF gain can be improved. In addition, since the FP electrode 50 connected to the source electrode 20 is formed in the inactive region 41, the effect of FP can be obtained. That is, the gate-drain capacitance Cgd can be reduced by the Faraday shield effect. In addition, since the electric field between the gate and the drain can be dispersed from the gate end to the FP electrode end, the collapse can be improved, that is, the Po characteristic during high voltage operation can be improved. Thus, the RF gain can be improved while maintaining the effect of FP.

  Note that the FP pads 52 and 53 may be formed on only one of the tip and the base in accordance with the finger length and frequency, and may be brought into contact with the source electrode 20. If the FP electrode 50 can be grounded, the source electrode 20 may not be contacted. For example, as shown in FIG. 3, the tip side FP pad 52 may be directly grounded. Here, another configuration of the FET will be described with reference to FIG. FIG. 3 is a plan view showing another configuration of the FET.

  As shown in FIG. 3, the plurality of FP fingers 51 extend from the FP bar 54 formed in the inactive region 41. The FP bar 54 is formed between the source finger 21 and the drain pad 32. The FP bar 54 is formed between the gate finger 11 and the drain pad 32. That is, the FP bar 54 is not formed so as to overlap the gate finger 11 and the source finger 21. The FP bar 54 extends in a direction orthogonal to the extending direction of the FP fingers 51.

  The FP bar 54 is electrically connected to the tip side FP pad 52 formed in the inactive region 41. The tip side FP pad 52 is grounded by a via hole 55. That is, the FP electrode 50 is directly grounded by the via hole 55 instead of being grounded by contact between the source finger 21 and the FP electrode 50 at the front end side of the source finger 21. Even with such a configuration, the same effect as described above can be obtained. In addition, the tip side FP pad 52 may be grounded not only by the via hole 55 but also by bonding to the ground. Thus, as long as it is sufficient to ground the FP electrode 50, it may be grounded in any way, and the shapes of the FP pads 52 and 53 may be long bars as described above.

  Next, a method for manufacturing the FET will be described. The method for manufacturing the FET can be simply described because it can be the same as the conventional method. First, the active region 40 and the inactive region 41 are formed in the semiconductor substrate 60. Then, the source ohmic metal 61 and the drain ohmic metal 62 are formed in a desired shape on the semiconductor substrate 60. Next, a first protective film 63 is formed so as to cover the source ohmic metal 61 and the drain ohmic metal 62, and an opening is formed in the first protective film 63. Thereafter, the T-type gate electrode 10 is formed so as to be embedded in the opening of the first protective film 63. Then, a second protective film 64 is formed so as to cover the gate electrode 10.

  Next, the FP electrode 50 is formed on the second protective film 64. The material of the FP electrode 50 can be Au, Pt, Ti, TiN or the like, but is not limited to this. Further, as a method of forming the FP electrode 50, vapor deposition lift-off, sputtering, or the like can be used, but is not limited thereto. The FP electrode 50 is also formed in the inactive region 41 as shown in FIG. Specifically, the tip side FP pad 52 is formed on the tip side of the source finger 21 to be formed later. Then, the base side FP pad 53 is formed on the base side of the gate finger 11, that is, between the gate bus bar 12 and the drain finger 31.

  Openings are formed in the first protective film 63 and the second protective film 64 on the source ohmic metal 61 and the drain ohmic metal 62. Thereafter, the source electrode 20 and the drain electrode 30 are formed so as to be embedded in the openings on the source ohmic metal 61 and the drain ohmic metal 62. Thereby, the source ohmic metal 61 and the source electrode 20 and the drain ohmic metal 62 and the drain electrode 30 are connected. At this time, the source electrode 20 and the FP electrode 50 are connected by extending the source electrode 20 to the FP pads 52 and 53. In the back surface process, via holes 23 are formed on both surfaces of the source pad 22 from the back surface. Next, a back metal is formed so as to be embedded in the via hole 23. Ti, Pt, Au, or the like can be used as the back metal, but is not limited thereto. By connecting the back surface and the source pad 22 by the via hole 23, the source electrode 20 and the FP pads 52 and 53 are also grounded. The FET according to the present embodiment is formed as described above. Further, an FET having good characteristics can be obtained without complicating the manufacturing process like the FET shown in FIG. For this reason, it is simple and productivity can be improved.

  Here, FIG. 4 shows the result of comparing the RF input / output characteristics of the conventional FET shown in FIGS. 7 and 10 and the FET of the present invention. Here, the finger length is 1000 μm, the gate width is 10 mm, and the frequency is 2 GHz. In FIG. 4, the horizontal axis represents input power Pin [dBm], and the vertical axis represents output power Pout [dBm]. Reference numeral 70 denotes an FET with an aperture ratio of 100%, reference numeral 71 denotes an FET with an aperture ratio of 80%, reference numeral 72 denotes an FET with an aperture ratio of 50%, and reference numeral 73 denotes an FET with an aperture ratio of 0%.

  Here, the aperture ratio is the ratio of the open area to the FP electrode 50 covering the gate-source area as shown in FIG. That is, the ratio of the area not covered with the FP electrode 50 in the area between the gate and the source in the active region 40. In other words, it is the ratio of the length of the FP electrode 50 having an opening between the gate and the source to the finger length. That is, an aperture ratio of 100% represents the FET of the present invention, an aperture ratio of 0% represents the FET shown in FIG. 7, and an aperture ratio of 80% and an aperture ratio of 50% represent the FET shown in FIG. As shown in FIG. 4, when compared with the same input power Pin, it can be seen that the output power Pout increases as the aperture ratio increases.

  FIG. 5 is a graph obtained by re-plotting the relationship between the aperture ratio and the gain. In FIG. 5, the horizontal axis represents the aperture ratio [%], and the vertical axis represents the gain [dB]. As shown in FIG. 5, the gain increases as the aperture ratio increases. Specifically, a part of the FP electrode 50 covering between the gate and the source is opened, and the gain increases as the region becomes larger. That is, the gain increases as the number of FP electrodes 50 covering the gate-source region decreases. This is considered to be due to the reduction of the parasitic capacitance Cgs due to the FP electrode 50 covering between the gate and the source. In the case of the present invention with an aperture ratio of 100%, it can be seen that the gain of 3 dB or more is improved as compared with an FET with an aperture ratio of 0%.

  In the conventional structure, since the source electrode 20 and the FP electrode 50 are connected in the active region 40, it is impossible to make the aperture ratio 100%. Further, when the aperture ratio is close to 100% in the conventional structure, it is considered that the grounding property of the FP electrode 50 is deteriorated and the gain is decreased. For this reason, also in FIG. 5, when the aperture ratio is 80% in the conventional structure, the gain is slightly reduced. Therefore, the present invention in which the FP pads 52 and 53 are provided in the non-active region 41 improves the grounding property. Therefore, it can be considered that the gain improvement is effective when compared with the conventional structure with the same aperture ratio.

  FIG. 6 shows the result of simulating the relationship between the aperture ratio of the FP electrode 50 and the grounding property. In FIG. 6, the horizontal axis represents frequency [GHz], and the vertical axis represents S12 [dB]. Here, S12 is one of the S parameters of the FET and is the magnitude of the signal returning from the output side of the FET to the input side. That is, the smaller the numerical value, the smaller the signal that returns, and the better the isolation. Here, a source finger 21, a gate finger 11, a drain finger 31, and an FP finger 51 each having a finger length of 1000 μm are arranged in parallel, and S12 of the gate and the drain is calculated.

  As shown in FIG. 6, the isolation S12 became smaller as the aperture ratio became lower. That is, as the aperture ratio decreases, the grounding property of the FP electrode 50 is improved, the lines of electric force between the gate and the drain are shielded, and the isolation S12 is improved. That is, the isolation S12 due to the Faraday shield effect is improved. Here, the grounding property is compared between the FET having the FP electrode 50 and the FET having the FP electrode 50 and having no FP electrode 50, which is indicated by reference numeral 74. First, at a frequency of 2 GHz, an FET with an aperture ratio of 0%, which covers the entire surface between the gate and the source with the FP electrode 50, and an FET without the FP electrode 50 are compared. From the graph of FIG. 6, it can be seen that the FET with an aperture ratio of 0% improves the isolation S12 by 10 dB. In addition, at a frequency of 2 GHz, an FET with an aperture ratio of 100% grounded at both ends of the FP electrode 50 and an FET without the FP electrode 50 are compared. From the graph of FIG. 6, it can be seen that the FET with 100% aperture ratio improves the isolation S12 by 7.5 dB.

  Next, the grounding property of the FET due to the difference in aperture ratio will be compared. Comparing an FET with an aperture ratio of 100% and an FET with an aperture ratio of 0% at a frequency of 2 GHz, it can be seen that the isolation S12 is only a difference of about 2.5 dB. The influence of grounding gain (MSG: Maximum Stable Gain) is estimated to be a degree of deterioration of 1.25 dB. Thus, it can be seen that the difference in the isolation S12 due to the aperture ratio is not so large as compared with the case where the FET does not have the FP electrode 50. That is, it can be seen that the difference in grounding property due to the aperture ratio is not so large.

  Therefore, considering the result of FIG. 5, it can be said that the gate-source parasitic capacitance Cgs is more susceptible to the gain due to the source-grounded FP electrode 50, although the grounding property is also important. That is, if the FP pads 52 and 53 in the inactive region 41 can maintain the grounding property to some extent, rather than connecting the FP electrode 50 and the source electrode 20 in the active region 40 widely in order to maintain the grounding property, The gain can be further improved by reducing the parasitic capacitance Cgs.

  However, according to the calculation result of FIG. 6, the grounding property gradually deteriorates as the frequency increases. For this reason, if the finger length of 1000 μm is to be used in a high frequency range, the connection between the tip and the base FP pads 52 and 53 alone cannot ground the entire long finger, and gain reduction due to poor grounding can be seen. is expected. However, since it is common to shorten the finger length in order to suppress the phase shift in a high frequency region, the grounding property is improved as the finger length is shortened. Therefore, in practical use, it is considered that there is no problem in connection with the FP pads 52 and 53 installed in the tip and root inactive areas 41 at any frequency. On the contrary, in the case of a low frequency, the difference in grounding property due to the aperture ratio is further reduced, so that it is considered that only one FP pad 52, 53 is possible. That is, the FP pads 52 and 53 are considered to be possible only on the tip side of the source finger or only on the base side of the gate finger.

  Since the FP pads 52 and 53 are arranged in the inactive region 41 where the elements are separated and have the same potential (ground) as the back surface, the effect of the FP does not depend on the shape of the FP pad, and the frequency depending on the shape. There is no difference in dependency. The FP pads 52 and 53 may have any shape, but if there are no process restrictions (such as alignment margins), it is better to make the area connected to the source as wide as possible on the FP pads 52 and 53. The good thing to enhance is self-evident.

  From the above results, when the FP electrode 50 is added to the FET, it is possible to increase the breakdown voltage and gain due to the electric field relaxation effect and the shielding effect. However, depending on the pattern and structure to which the FP electrode 50 is connected, It can be seen that the gain is reduced and the characteristic is unstable. This is because when the FP electrode 50 and the source electrode 20 are connected, a parasitic capacitance Cgs is generated in the gate-source region covered with the FP electrode 50. In the FET according to the present invention, in order to effectively solve this problem without increasing the number of man-hours, the FP pads 52 and 53 are provided in the inactive region 41 and the FP electrode 50 is grounded. As a result, the portion of the active region 40 where the gate-source region is covered with the FP electrode 50 can be eliminated. And RF gain can be improved, maintaining the effect of FP.

It is a top view which shows the structure of FET concerning embodiment. It is II-II sectional drawing of FIG. It is a top view which shows the other structure of FET concerning embodiment. It is a graph which shows the result of having compared the RF input / output characteristic of the conventional FET and the FET of the present invention. It is a graph shown about the relationship between an aperture ratio and a gain. It is a graph which shows the result of having simulated the relationship between an aperture ratio and grounding property. It is a top view which shows the structure of FET of the conventional source FP structure. It is VIII-VIII sectional drawing of FIG. It is sectional drawing which shows the 2nd structure of the FET of the conventional source FP structure. It is a top view which shows the 2nd structure of the FET of the conventional source FP structure. It is a top view which shows the 2nd structure of the FET of the conventional source FP structure.

Explanation of symbols

10 gate electrodes, 11 gate fingers, 12 gate bus bars,
13 gate pad, 20 source electrode, 21 source finger, 22 source pad,
23 via holes, 30 drain electrodes, 31 drain fingers,
32 drain pads, 40 active regions, 41 inactive regions,
50 FP electrode, 51 FP finger, 52 FP pad on the tip side,
53 FP pad, 54 FP bar, 55 via hole, 60 semiconductor substrate,
61 source ohmic metal, 62 drain ohmic metal, 63 first protective film,
64 second protective film, 70 FET with 100% aperture ratio, 71 FET with 80% aperture ratio,
72 FET with an aperture ratio of 50%, 73 FET with an aperture ratio of 0%,
74 FET without FP electrode, 80 gap, 81 FP bridge

Claims (4)

A source electrode formed in the active region;
A drain electrode formed in the active region;
A gate electrode formed in the active region and sandwiched between the source electrode and the drain electrode;
A field plate electrode formed in the vicinity of the gate electrode outside the region sandwiched between the gate electrode and the source electrode;
A field effect transistor including an FP pad included in the field plate electrode, formed outside the active region, and grounded. The source electrode is grounded;
The field effect transistor according to claim 1, wherein the FP pad is in contact with the source electrode.   The field effect transistor according to claim 1, wherein the FP pad is grounded by a via hole or bonding. The FP electrode has FP fingers,
The field effect transistor according to claim 1, wherein the FP pad is formed at both ends of the FP finger.

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