JP2013182993A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-gain semiconductor device.SOLUTION: A metal ground surface is formed on the side of a substrate immediately below at least a partial region of a shield plate electrode, and the shield plate electrode short-circuited by a source electrode is arranged in the vicinity of a drain electrode. Thereby, an active layer between the gate and the drain is interposed by the ground surface from top and bottom. Thereby, a region between the drain and the gate is electrically shielded, capacitor Cgd between the gate and the drain is reduced, and increase in capacitor Cgs between the gate and the source is suppressed.

Description

  Embodiments described herein relate generally to a semiconductor device.

  A source field plate is known as a field relaxation technique for a field effect transistor (FET). By disposing the source field plate between the gate and the drain, the electric field concentration in the vicinity of the gate electrode can be reduced, and as a result, the breakdown voltage of the FET can be improved. In order to effectively relax the electric field, the source field plate is arranged in the vicinity of the gate electrode or overlapping the gate electrode.

Special table 2007-537593

K. Asano et al., “New Novel High Power AlGaAs / GaAs HFET with a Field-Modulating Plate Operated at 35V Drain Voltage with 35V Drain Voltage Operation Field Modulating Plate , "Technical Digest, 1998 International Electronic Device Conference, American Institute of Electrical and Electronics Engineers, pp. 59-62, (1998 IEEE IEDM Technical Digest, December 1998, pp. 59-62). Y.-F. Wu, et al., “Field Plate Optimization 30W / mm GaN HEMTs by Field Plate Optimization,” Electron Device Letters , American Institute of Electrical and Electronics Engineers, Vol. 25, March 2004, pages 117-119 (IEEE EDL, vol. 25, March 2004, pp. 117-119). H. Xing et al., “High Breakdown Voltage AlGaN-GaN HEMTs Achieved by Multiple Field Plates Realized by Multi-Field Plates,” Electron Device Letters, USA Electric Electronic Society, Vol. 25, April 2004, 161-163 (IEEE EDL, vol. 25, April 2004, pp. 161-163).

  An FET operating at a high frequency such as a millimeter wave band can be expected to have a high gain when operating at a relatively low frequency such as a microwave band. On the other hand, since the feedback becomes large, it is difficult to suppress oscillation. Although the source field plate is effective in suppressing oscillation, the source field plate shorted to the source is arranged near the gate, so that the gate-source capacitor Cgs is increased. As a result, the gain of the FET decreases. In addition, since the ground plane exists only on the surface side of the semiconductor device, the electrical shield effect between the gate and the drain in the semiconductor active layer cannot be expected so much.

  The problem to be solved by the present embodiment is to provide a high gain semiconductor device.

  A metal ground plane is formed on the substrate side immediately below at least a partial region of the shield plate electrode, and a shield plate electrode short-circuited to the source electrode is disposed in the vicinity of the drain electrode so that the active layer between the gate and drain is connected from above and below. Insert it on the ground. The drain-gate is electrically shielded to reduce the gate-drain capacitor Cgd and suppress the increase of the gate-source capacitor Cgs.

FIG. 2 is a schematic plan pattern configuration diagram of the semiconductor device according to the first embodiment. FIG. 4 is a detailed schematic plan pattern configuration diagram of a unit transistor portion in the semiconductor device according to the first embodiment. FIG. 3 is a schematic sectional view taken along the line II-II in FIG. 2. FIG. 2 is a schematic cross-sectional structure diagram taken along line II of FIG. 1 (Structure example 1 of FET cell). FIG. 2 is a schematic sectional view taken along the line II of FIG. 1 (FET cell structure example 2). FIG. 2 is a schematic cross-sectional structure diagram taken along the line I-I in FIG. FIG. 2 is a schematic cross-sectional structure diagram taken along the line II of FIG. 1 (FET cell structure example 4). The typical plane pattern block diagram of the high frequency semiconductor device which concerns on the modification 1 of 1st Embodiment. The typical plane pattern block diagram of the high frequency semiconductor device which concerns on the modification 2 of 1st Embodiment. FIG. 10 is a schematic cross-sectional configuration diagram taken along line III-III in FIG. 9. FIG. 10 is another schematic cross-sectional configuration diagram taken along line III-III in FIG. 9. The detailed schematic plane pattern block diagram of the unit transistor part of the semiconductor device which concerns on 2nd Embodiment. The typical cross-section block diagram which follows the IV-IV line of FIG. The typical plane pattern block diagram of the high frequency semiconductor device which concerns on the modification 1 of 2nd Embodiment. The typical plane pattern block diagram of the high frequency semiconductor device which concerns on the modification 2 of 2nd Embodiment. The typical cross-section block diagram which follows the VV line | wire of FIG. FIG. 16 is another schematic cross-sectional configuration diagram along line VV in FIG. 15.

  Next, embodiments will be described with reference to the drawings. In the following, the same elements are denoted by the same reference numerals to avoid duplication of explanation and to simplify the explanation. It should be noted that the drawings are schematic and different from the actual ones. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  The embodiment described below exemplifies an apparatus and a method for embodying the technical idea, and the embodiment does not specify the arrangement of each component as described below. This embodiment can be modified in various ways within the scope of the claims.

[First embodiment]
(Semiconductor device)
A schematic planar pattern configuration of the semiconductor device 25 according to the first embodiment is expressed as shown in FIG. Further, in the semiconductor device 25 according to the first embodiment, the detailed schematic planar pattern configuration of the unit transistor portion is expressed as shown in FIG. 2, and a schematic cross-sectional structure taken along line II-II in FIG. Is expressed as shown in FIG. Also in FIG. 1, the shield plate electrode 30 and the shield plate short-circuit electrode 32 as shown in FIG. 2 are arranged in the same manner as in FIG. 2 in each unit transistor portion, but the illustration is omitted to avoid complexity. Yes. The schematic cross-sectional structure taken along the line II of FIG. 1 is expressed as shown in FIGS. 4 to 7, the shield plate electrode 30 and the ground electrode 50 disposed in the recess portion of the substrate 10 immediately below at least a partial region of the shield plate electrode 30 are shown in the drawings.

  As shown in FIGS. 1 to 3, the semiconductor device 25 according to the first embodiment includes a substrate 10, a gate electrode 24, a source electrode 20, a drain electrode 22, an insulating layer 34, and a shield plate electrode. 30 and a ground electrode 50.

  The gate electrode 24 is disposed on the first surface of the substrate 10 and has a plurality of fingers. The source electrode 20 is disposed on the first surface of the substrate 10, has a plurality of fingers, and is disposed adjacent to the gate electrode 24. The drain electrode 22 has a plurality of fingers and is disposed to face the source electrode 20 with the gate electrode 24 interposed therebetween.

  As shown in FIG. 3, the insulating layer 34 is disposed so as to cover the gate electrode 24, the substrate 10 between the gate electrode 24 and the source electrode 20 and the drain electrode 22, and at least a part of the source electrode 20 and the drain electrode 22. The

  As shown in FIG. 3, the shield plate electrode 30 is disposed on the first surface of the substrate 10 between the gate electrode 24 and the drain electrode 22 and on the drain electrode 22 via an insulating layer 34, and is short-circuited with the source electrode 20. Then, the gate electrode 24 and the drain electrode 22 are electrically shielded.

  As shown in FIG. 3, the ground electrode 50 is disposed on the second surface side of the substrate 10 immediately below at least a partial region of the shield plate electrode 30.

  In addition, as shown in FIG. 3, the ground electrode 50 is formed on the substrate 10 immediately below at least a partial region of the shield plate electrode 30, and on the inner wall of the recess portion formed from the second surface facing the first surface of the substrate 10. It may be arranged on two surfaces. The width of the recess portion is represented by Wt as shown in FIG.

  Further, as shown in FIG. 3, the bottom portion of the recess portion may be disposed on the substrate 10 immediately below at least a partial region of the shield plate electrode 30. Although the recess portion has a uniform width Wt in FIG. 3, the recess portion may have a tapered shape that gradually decreases from the width of the second surface of the substrate 10. Moreover, you may provide the reverse taper shape which becomes wide gradually from the width | variety of the 2nd surface of the board | substrate 10. FIG.

  Further, the ground electrode 50 formed on the second surface facing the first surface of the substrate 10 may have a bathtub structure as shown in FIG.

Further, the outer frame portion of the semiconductor device 25, as shown in FIG. 3, may include the same thickness T _B and the substrate 10. That is, when the substrate 10 is thin, the mechanical strength is weakened, at least the outer frame portion of the semiconductor device 25, it is desirable to have a comparable thickness T _B and the substrate 10.

In the semiconductor device 25 according to the first embodiment, as shown in FIG. 3, the ground electrode 50 is formed on the substrate 10 side immediately below at least a partial region of the shield plate electrode 30, and the source electrode 20 is adjacent to the drain electrode 22. By arranging the short-circuited shield plate electrode 30, the active layer 10 (AA) having the thickness T _A is sandwiched between the gate electrode 24 and the drain electrode 22 from above and below by the ground plane. For this reason, the electrical shielding effect between the gate electrode 24 and the drain electrode 22 can be increased.

3, the thickness T _A of the active layer 10 (AA) between the gate electrode 24 and drain electrode 22 is, for example, from about 5μm~ about 30 [mu] m, the outer frame portion of the semiconductor device 25, equivalent to the substrate 10 the thickness T _B is, for example, from about 20μm~ about 1 mm. The distance L between the drain electrode 22 and the gate electrode 24 is, for example, about 0.5 μm to about 20 μm. Moreover, it is desirable to have the relationship shown to following Formula (1).

T _B > T _A , T _A / L <10 (1)

As shown in FIG. 3, the semiconductor device 25 according to the first embodiment has a configuration in which the active layer 10 (AA) having a thickness T _A is sandwiched between the gate electrode 24 and the drain electrode 22 from above and below by a ground plane. With this, a part of the electric lines of force between the gate electrode 24 and the drain electrode 22 can be released to the ground electrode 50. For this reason, the electrical shielding effect between the gate electrode 24 and the drain electrode 22 can be increased, and the electric field concentration between the gate electrode 24 and the drain electrode 22 can be reduced.

Further, as shown in FIG. 3, the shield plate electrode 30 is disposed away from the gate electrode 24 by a distance W _SG longer than at least the thickness t1 of the insulating layer. With this configuration, it is possible to increase the electrical shield effect between the drain and gate, reduce the gate-drain capacitor Cgd, and suppress the increase in the gate-source capacitor Cgs. Here, the shield plate electrode 30 may be disposed away from the gate electrode 24 by a distance W _SG longer than at least the thickness t1 of the insulating layer. Here, W _SG > 0 may be sufficient.

  Further, as shown in FIGS. 2 and 3, the shield plate electrode 30 covers at least a part of the upper portion of the drain electrode 22 with the insulating layer 34 interposed therebetween.

  The electrical shield effect between the gate and the drain by the shield plate electrode 30 can be expected as the thickness t1 of the insulating layer 34 is reduced. When the thickness t1 of the insulating layer 34 is relatively thick, the number of electric lines of force that run in the insulating layer 34 between the gate electrode 24 and the drain electrode 22 increases, and the electric current between the gate electrode 24 and the drain electrode 22 increases. The effective shield effect is reduced. On the other hand, when the thickness t1 of the insulating layer 34 is relatively thin, the number of electric lines of force that run in the insulating layer 34 between the gate electrode 24 and the drain electrode 22 is reduced accordingly, and the gate electrode 24 and the drain are reduced. This is because the electrical shielding effect between the electrodes 22 is enhanced.

  Further, as shown in FIG. 3, the drain pad electrode 22 </ b> P may be disposed on the drain electrode 22, and the source pad electrode 20 </ b> P may be disposed on the source electrode 20. The drain pad electrode 22P and the source pad electrode 20P can reduce the resistance components of the drain electrode 22 and the source electrode 20 each having a finger structure.

  Further, as shown in FIG. 2, the semiconductor device 25 according to the first embodiment includes a shield plate short-circuit electrode 32 having a wiring structure that is disposed on the substrate 10 and short-circuits the shield plate electrode 30 and the source electrode 20. Prepare.

As shown in FIG. 3, in the semiconductor device 25 according to the first embodiment, the upper end of the shield plate electrode 30 measured from the first surface of the substrate 10 is higher than the upper end of the gate electrode 24. Only _{SG is} expensive. With this configuration, the electrical shield effect between the drain and the gate can be enhanced.

  In the semiconductor device 25 according to the first embodiment, the shield plate electrode 30 short-circuited to the source electrode is disposed in the vicinity of the drain electrode 22 to electrically shield the drain and the gate, and the gate-drain capacitor Cgd can be reduced and an increase in the gate-source capacitor Cgs can be suppressed. For this reason, the electric field concentration between the gate and the drain can be relaxed without deteriorating the high frequency characteristics.

In the semiconductor device 25 according to the first embodiment, since it is possible to reduce the gate-drain capacitor Cgd, this result, it is possible to reduce the S parameter S _12, to obtain a semiconductor device of high gain be able to.

  In the semiconductor device 25 according to the first embodiment, the plurality of FET cells 40 are disposed on the semi-insulating substrate 10 and the first surface of the semi-insulating substrate 10 as shown in FIG. The gate electrode 24 having a plurality of fingers, the source electrode 20 and the drain electrode 22 are disposed on the first surface of the semi-insulating substrate 10, and the plurality of fingers are bundled for each of the gate electrode 24, the source electrode 20 and the drain electrode 22. , G4, source terminal electrodes S1, S2,..., S5 and drain terminal electrodes D1, D2,..., D4, and source terminal electrodes S1, S2,. VIA holes SC1, SC2,..., SC5 arranged at the lower part of S5, and a second terminal surface opposite to the first surface of the semi-insulating substrate 10, and a source terminal electrode 1, S2, ..., VIA holes SC1, SC2 respect S5, ..., and a ground electrode connected via a SC5 (not shown).

  In the FET cell 40, the plurality of gate electrodes 24 are connected to the gate bus line 24a, and the gate bus line 24a is connected to the gate terminal electrodes G1 to G4 via the gate bus line 24b.

  Input bonding wires are connected to the gate terminal electrodes G1, G2,..., G4, and output bonding wires are connected to the drain terminal electrodes D1, D2,.

  A source terminal electrode S1 is formed on a barrier metal layer (not shown) formed on the inner wall of the VIA holes SC1, SC2,..., SC5 and a filling metal layer (not shown) formed on the barrier metal layer and filling the VIA hole. , S2,..., S5 are connected to a ground electrode (not shown).

  The semi-insulating substrate 10 is a GaAs substrate, a SiC substrate, a GaN substrate, a substrate in which a GaN epitaxial layer is formed on a SiC substrate, a substrate in which a heterojunction epitaxial layer made of GaN / AlGaN is formed on a SiC substrate, a sapphire substrate, or One of the diamond substrates.

  In the semiconductor device 25 according to the first embodiment, the semiconductor device includes any one of a GaAs-based HEMT, a GaAs MESFET, and a GaN-based HEMT. That is, in the semiconductor device 25 according to the first embodiment, the semiconductor device uses a semiconductor material particularly suitable for high-frequency operation such as GaN and GaAs.

  In the configuration example of FIG. 1, for example, the cell width W1 is about 120 μm, W2 is about 80 μm, the cell length W3 is about 100 μm, W4 is about 120 μm, and the gate width is 100 μm × 6 lines × 4 cells = 2.40 mm or so.

  On the other hand, there is a structure in which the VIA holes SC1 to SC5 are not particularly arranged below the source terminal electrodes S1 to S5. In this case, for example, a side electrode is disposed on the side surface of the substrate 10 to provide a ground potential to the source terminal electrodes S1 to S5, and the source terminal electrodes S1 to S5 and the second surface of the substrate 10 are provided. You may employ | adopt the structure which connects the arrange | positioned grounding conductor. Alternatively, the ground potential can be applied to the source terminal electrodes S1 to S5 by wire bonding. Alternatively, instead of providing the source terminal electrodes S1 to S5, a VIA hole called a slot VIA may be formed in the source electrode 20 itself.

  In the semiconductor device 25 according to the first embodiment, as shown in FIG. 1, the gate bus lines 24a and 24b are arranged below the connection electrodes of the source electrode 20 and the source terminal electrodes S1 to S5. However, conversely, the gate bus lines 24a and 24b may be disposed above the connection electrodes of the source electrode 20 and the source terminal electrodes S1 to S5.

  In the semiconductor device 25 according to the first embodiment, the source terminal electrodes S1 to S5 are disposed in the vicinity of the gate terminal electrodes G1 to G4 as shown in FIG. You may arrange | position in the vicinity of the electrodes D1-D4.

(FET cell structure)
(Structural example 1)
As a schematic cross-sectional configuration along the line I-I in FIG. 1, the configuration example 1 of the FET cell 40 includes a substrate 10, an epitaxial growth layer 12 disposed on the substrate 10, and an epitaxial growth layer 12 as shown in FIG. 4. The electron supply layer 18 disposed above, the source electrode 20, the gate electrode 24, and the drain electrode 22 disposed on the electron supply layer 18, and the gate electrode 24, between the gate electrode 24, the source electrode 20, and the drain electrode 22 On the substrate 10, the insulating layer 34 disposed so as to cover at least a part of the source electrode 20 and the drain electrode 22, the first surface of the substrate 10 between the gate electrode 24 and the drain electrode 22, and the drain electrode 22, A shield that is disposed through the insulating layer 34, is short-circuited with the source electrode 20, and electrically shields between the gate electrode 24 and the drain electrode 22. It comprises a rate electrode 30, a ground electrode 50 disposed on the substrate 10 surface immediately below at least a partial region of the shield plate electrode 30. A two-dimensional electron gas (2DEG) layer 16 is formed at the interface between the epitaxial growth layer 12 and the electron supply layer 18. In the configuration example 1 shown in FIG. 4, a high electron mobility transistor (HEMT) is shown.

Specifically, in the case of a GaAs-based HEMT, the substrate 10 is formed of a GaAs substrate, the epitaxial growth layer 12 is formed of a GaAs layer, and the electron supply layer 18 is formed of, for example, an aluminum gallium arsenide layer (Al _y Ga _{1 -y} As) (0.1 ≦ y ≦ 1). In the case of a GaN-based HEMT, the substrate 10 is formed of a GaN substrate or a SiC substrate, the epitaxial growth layer 12 is formed of a GaN layer, and the electron supply layer 18 is, for example, an aluminum gallium nitride layer (Al _x Ga _{1). -x} N) (0.1 ≦ x ≦ 1).

(Structural example 2)
As a schematic cross-sectional configuration taken along line II in FIG. 1, the configuration example 2 of the FET cell 40 includes a substrate 10, an epitaxial growth layer 12 disposed on the substrate 10, and an epitaxial growth layer 12 as shown in FIG. Source region 26 and drain region 28 disposed on top, source electrode 20 disposed on source region 26, gate electrode 24 disposed on epitaxial growth layer 12 and drain electrode 22 disposed on drain region 28 The gate electrode 24, the substrate 10 between the gate electrode 24 and the source electrode 20 and the drain electrode 22, the insulating layer 34 covering at least part of the source electrode 20 and the drain electrode 22, the gate electrode 24 and the drain Disposed on the first surface of the substrate 10 between the electrodes 22 and the drain electrode 22 via an insulating layer 34; A shield plate electrode 30 which is short-circuited with the source electrode 20 and electrically shields between the gate electrode 24 and the drain electrode 22, and a ground electrode 50 disposed on the surface side of the substrate 10 immediately below at least a part of the shield plate electrode 30 With. A Schottky contact is formed at the interface between the epitaxial growth layer 12 and the gate electrode 24. In the configuration example 2 shown in FIG. 5, a metal-semiconductor field effect transistor (MESFET) is shown. For example, in the case of a GaAs MESFET, the substrate 10 is formed of a GaAs substrate, and the epitaxial growth layer 12 is formed of an epitaxially grown GaAs layer. The source region 26 and the drain region 28 can be formed by ion implantation of Si ions or the like.

(Structural example 3)
As a schematic cross-sectional configuration taken along line II in FIG. 1, the configuration example 3 of the FET cell 40 includes a substrate 10, an epitaxial growth layer 12 disposed on the substrate 10, and an epitaxial growth layer 12 as shown in FIG. An electron supply layer 18 disposed above, a source electrode 20 and a drain electrode 22 disposed on the electron supply layer 18, a gate electrode 24 disposed in a recess on the electron supply layer 18, a gate electrode 24, Substrate 10 between gate electrode 24 and source electrode 20 and drain electrode 22, insulating layer 34 disposed so as to cover at least a part of source electrode 20 and drain electrode 22, and substrate between gate electrode 24 and drain electrode 22 10 on the first surface of 10 and the drain electrode 22 with an insulating layer 34 interposed therebetween, short-circuited with the source electrode 20, and gate electrode 24 and drain Includes a shield plate electrode 30 which electrically shield between electrode 22 and ground electrode 50 disposed on the substrate 10 surface immediately below at least a partial region of the shield plate electrode 30. A 2DEG layer 16 is formed at the interface between the epitaxial growth layer 12 and the electron supply layer 18. In the configuration example 3 illustrated in FIG. 6, the HEMT is illustrated.

Specifically, in the case of a GaAs-based HEMT, the substrate 10 is formed of a GaAs substrate, the epitaxial growth layer 12 is formed of a GaAs layer, and the electron supply layer 18 is formed of, for example, an aluminum gallium arsenide layer (Al _y Ga _{1 -y} As) (0.1 ≦ y ≦ 1). In the case of a GaAs HEMT, an active layer may be formed in the electron supply layer 18 immediately below the gate electrode 24 by ion implantation of Si ions or the like.

In the case of a GaN-based HEMT, the substrate 10 is formed of a GaN substrate or a SiC substrate, the epitaxial growth layer 12 is formed of a GaN layer, and the electron supply layer 18 is, for example, an aluminum gallium nitride layer (Al _x Ga _{1). -x} N) (0.1 ≦ x ≦ 1).

(Structural example 4)
As a schematic cross-sectional configuration taken along the line II of FIG. 1, the configuration example 4 of the FET cell 40 includes a substrate 10, an epitaxial growth layer 12 disposed on the substrate 10, and an epitaxial growth layer 12 as shown in FIG. An electron supply layer 18 disposed above, a source electrode 20 and a drain electrode 22 disposed on the electron supply layer 18, a gate electrode 24 disposed in a two-stage recess on the electron supply layer 18, and a gate electrode 24, the substrate 10 between the gate electrode 24 and the source electrode 20 and the drain electrode 22, the insulating layer 34 disposed so as to cover at least a part of the source electrode 20 and the drain electrode 22, and the gap between the gate electrode 24 and the drain electrode 22. An insulating layer 34 is disposed on the first surface of the substrate 10 and on the drain electrode 22, is short-circuited with the source electrode 20, and is drained with the gate electrode 24. Includes a shield plate electrode 30 which electrically shield between emission electrode 22, a ground electrode 50 disposed on the substrate 10 surface immediately below at least a partial region of the shield plate electrode 30. A 2DEG layer 16 is formed at the interface between the epitaxial growth layer 12 and the electron supply layer 18. In the configuration example 4 illustrated in FIG. 7, the HEMT is illustrated.

Specifically, in the case of a GaAs-based HEMT, the substrate 10 is formed of a GaAs substrate, the epitaxial growth layer 12 is formed of a GaAs layer, and the electron supply layer 18 is formed of, for example, an aluminum gallium arsenide layer (Al _y Ga _{1 -y} As) (0.1 ≦ y ≦ 1). In the case of a GaAs HEMT, an active layer may be formed in the electron supply layer 18 immediately below the gate electrode 24 by ion implantation of Si ions or the like.

In the case of a GaN-based HEMT, the substrate 10 is formed of a GaN substrate or a SiC substrate, the epitaxial growth layer 12 is formed of a GaN layer, and the electron supply layer 18 is, for example, an aluminum gallium nitride layer (Al _x Ga _{1). -x} N) (0.1 ≦ x ≦ 1).

  In the semiconductor device 25 according to the first embodiment, the gate electrode 24 has a T-shaped cross-sectional structure along the channel direction of the source / drain direction, and the electric field around the gate electrode 24 is relaxed. You may have.

(Modification 1)
A schematic planar pattern configuration of the semiconductor device according to the first modification of the first embodiment is expressed as shown in FIG. In the semiconductor device according to the first modification of the first embodiment, the shield plate electrode 30 is disposed so as to overlap a part of the drain electrode 22. That is, with respect to the length L0 of the drain electrode 22 in contact with the active region AA, the length L1 at which the shield plate electrode 30 is disposed on the active region AA has a relationship of L1 <L0. Here, the active area AA corresponds to an effective current conduction area between the source electrode 20 and the drain electrode 22 on the substrate 10. The active region AA includes the lower part of the gate electrode 24, the source electrode 20, and the drain electrode 22 on the substrate 10. Further, the region between the gate electrode 24 and the source electrode 20 and the region of the gate electrode 24 and the drain electrode 22 is also included on the substrate 10.

  In FIG. 8, the schematic cross-sectional structure along the II-II line is the same as FIG.

As shown in FIG. 3, in the semiconductor device 25 according to the first modification of the first embodiment, the ground electrode 50 is formed on the substrate 10 side immediately below at least a partial region of the shield plate electrode 30, and the vicinity of the drain electrode 22. The shield plate electrode 30 that is short-circuited to the source electrode 20 is disposed on the active electrode 10 (AA) having a thickness T _A between the gate electrode 24 and the drain electrode 22 so that the ground layer is sandwiched from above and below. Yes. For this reason, the electrical shielding effect between the gate electrode 24 and the drain electrode 22 can be increased.

  As shown in FIG. 3, the semiconductor device 25 according to the first modification of the first embodiment has a configuration in which the active layer 10 (AA) between the gate electrode 24 and the drain electrode 22 is sandwiched from above and below by a ground plane. Thus, part of the electric lines of force between the gate electrode 24 and the drain electrode 22 can be released to the ground electrode 50. For this reason, the electrical shielding effect between the gate electrode 24 and the drain electrode 22 can be increased, and the electric field concentration between the gate electrode 24 and the drain electrode 22 can be reduced.

  In the semiconductor device according to the first modification of the first embodiment, since the shield plate electrode 30 is disposed so as to overlap a part of the drain electrode 22, the drain and gate are electrically shielded, and the gate and drain are It is possible to reduce the inter-capacitor Cgd and suppress the increase in the gate-source capacitor Cgs. As a result, in the semiconductor device 25 according to the first modification of the first embodiment, a high gain semiconductor device can be obtained. Other configurations are the same as those of the first embodiment.

(Modification 2)
A schematic planar pattern configuration of the high-frequency semiconductor device according to the second modification of the first embodiment is expressed as shown in FIG. Further, a schematic cross-sectional structure taken along line III-III in FIG. 9 is represented as shown in FIG. 10, and another schematic cross-sectional structure taken along line III-III in FIG. 9 is represented as shown in FIG. Is done.

  In the semiconductor device according to the second modification of the first embodiment, the shield plate short-circuit electrodes 32 a, 32 b, 32 c, and 32 d are disposed so as to overlap the gate electrode 24.

  In the example of FIG. 10, the shield plate short-circuit electrodes 32a, 32b, 32c, and 32d are disposed on the gate electrode 24 via the air gap GAP. In the example of FIG. 11, the shield plate short-circuit electrodes 32 a, 32 b, 32 c, and 32 d are disposed on the gate electrode 24 via the insulating layer 34. Other configurations are the same as those of the first embodiment.

  In the configuration of the first embodiment and the modification example 1 shown in FIGS. 2 and 8, when the stripe of the gate electrode 24 becomes longer, the length of the source electrode 20 and the shield plate short-circuit electrode 32 in the extending direction becomes longer. The wiring due to the short circuit between the source electrode 20 and the shield plate electrode 30 becomes longer, and the value of the parasitic inductance connected to the source of the FET cell increases.

  In contrast, in the semiconductor device according to the second modification of the first embodiment, the shield plate short-circuit electrodes 32a, 32b, 32c, and 32d overlap the gate electrode 24 through the air gap GAP or the insulating layer 34. Therefore, the wiring distance between the source electrode 20 and the shield plate electrode 30 can be shortened. For this reason, the short-circuit wiring between the source electrode 20 and the shield plate electrode 30 can be shortened, the parasitic inductance connected to the source of the FET cell can be reduced, and the feedback impedance of each FET cell can be reduced.

  As shown in FIGS. 10 to 11, in the semiconductor device 25 according to the second modification of the first embodiment, the ground electrode 50 is formed on the substrate 10 side immediately below at least a partial region of the shield plate electrode 30, and the drain By arranging a shield plate electrode 30 short-circuited to the source electrode 20 in the vicinity of the electrode 22, the active layer 10 (AA) between the gate electrode 24 and the drain electrode 22 is sandwiched from above and below by a ground plane. For this reason, the electrical shielding effect between the gate electrode 24 and the drain electrode 22 can be increased.

  As shown in FIGS. 10 to 11, the semiconductor device 25 according to the second modification of the first embodiment has a configuration in which the active layer 10 (AA) between the gate electrode 24 and the drain electrode 22 is sandwiched from above and below by a ground plane. With this, a part of the electric lines of force between the gate electrode 24 and the drain electrode 22 can be released to the ground electrode 50. For this reason, the electrical shielding effect between the gate electrode 24 and the drain electrode 22 can be increased, and the electric field concentration between the gate electrode 24 and the drain electrode 22 can be reduced.

  In the semiconductor device according to the second modification of the first embodiment, the drain-gate is electrically shielded, the gate-drain capacitor Cgd is reduced, and the increase in the gate-source capacitor Cgs is suppressed. be able to. For this reason, the electric field concentration between the gate and the drain can be relaxed without deteriorating the high frequency characteristics.

Also in the semiconductor device 25 according to a second modification of the first embodiment, since it is possible to reduce the gate-drain capacitor Cgd, it is possible to reduce the S parameter S _12, a semiconductor device of high gain Can be obtained.

[Second Embodiment]
A schematic planar pattern configuration of the semiconductor device 25 according to the second embodiment is expressed in the same manner as in FIG. A detailed schematic planar pattern configuration of the unit transistor portion of the semiconductor device according to the second embodiment is expressed as shown in FIG. 12, and a schematic cross-sectional configuration along the line IV-IV in FIG. As shown in FIG.

  Also in the semiconductor device 25 according to the second embodiment, the same FET cell structure as in FIGS. 4 to 7 can be configured. In this case, the shield plate electrode 30 is configured as shown in FIGS.

  As shown in FIGS. 12 to 13, the semiconductor device 25 according to the second embodiment includes a substrate 10, a gate electrode 24, a source electrode 20, a drain electrode 22, an insulating layer 34, and a shield plate electrode. 30 and a ground electrode 50.

  The gate electrode 24 is disposed on the first surface of the substrate 10 and has a plurality of fingers. The source electrode 20 is disposed on the first surface of the substrate 10, has a plurality of fingers, and is disposed adjacent to the gate electrode 24. The drain electrode 22 has a plurality of fingers and is disposed to face the source electrode 20 with the gate electrode 24 interposed therebetween.

  As shown in FIG. 13, the insulating layer 34 is disposed so as to cover at least a part of the gate electrode 24, the drain electrode 22, the substrate 10 between the gate electrode 24 and the source electrode 20 and the drain electrode 22, and the source electrode 20. The

  As shown in FIG. 13, the shield plate electrode 30 is disposed on the first surface of the substrate 10 between the gate electrode 24 and the drain electrode 22 and on the drain electrode 22 via an insulating layer 34, and short-circuited with the source electrode 20. Then, the gate electrode 24 and the drain electrode 22 are electrically shielded. In the semiconductor device 25 according to the second embodiment, the shield plate electrode 30 is disposed on the drain electrode 22 via the insulating layer 34 as shown in FIG. In comparison, the electrical shielding effect between the gate electrode 24 and the drain electrode 22 is further increased.

  As shown in FIG. 12, the ground electrode 50 is disposed on the surface side of the substrate 10 immediately below at least a partial region of the shield plate electrode 30.

  In addition, as shown in FIG. 12, the ground electrode 50 is formed on the substrate 10 immediately below at least a partial region of the shield plate electrode 30, and on the inner wall of the recess portion formed from the second surface facing the first surface of the substrate 10. It may be arranged on two surfaces.

  Further, as shown in FIG. 12, the bottom portion of the recess portion may be disposed on the substrate 10 immediately below at least a partial region of the shield plate electrode 30.

  Further, the ground electrode 50 formed on the second surface facing the first surface of the substrate 10 may have a bathtub structure as shown in FIG.

Further, the outer frame portion of the semiconductor device 25, like FIG. 3, may include the same thickness T _B and the substrate 10. That is, when the substrate 10 is thin, the mechanical strength is weakened, at least the outer frame portion of the semiconductor device 25, it is desirable to have a comparable thickness T _B and the substrate 10.

  In the semiconductor device 25 according to the second embodiment, as shown in FIG. 12, the ground electrode 50 is formed on the substrate 10 side immediately below at least a partial region of the shield plate electrode 30, and the source electrode 20 is adjacent to the drain electrode 22. The shield plate electrode 30 that is short-circuited is disposed so that the active layer 10 (AA) is sandwiched between the gate electrode 24 and the drain electrode 22 from above and below by the ground plane. For this reason, the electrical shielding effect between the gate electrode 24 and the drain electrode 22 can be increased.

  As shown in FIG. 13, the semiconductor device 25 according to the second embodiment has a configuration in which the active layer 10 (AA) between the gate electrode 24 and the drain electrode 22 is sandwiched between the upper and lower sides by the ground plane, so that the gate electrode A part of electric lines of force between the 24 and drain electrodes 22 can be released to the ground electrode 50. For this reason, the electrical shielding effect between the gate electrode 24 and the drain electrode 22 can be increased, and the electric field concentration between the gate electrode 24 and the drain electrode 22 can be reduced.

Further, as shown in FIG. 13, the shield plate electrode 30 is disposed away from the gate electrode 24 by a distance W _SG longer than at least the thickness t1 of the insulating layer. With this configuration, it is possible to increase the electrical shield effect between the drain and gate, reduce the gate-drain capacitor Cgd, and suppress the increase in the gate-source capacitor Cgs. Here, the shield plate electrode 30 may be disposed away from the gate electrode 24 by a distance W _SG longer than at least the thickness t1 of the insulating layer. Here, W _SG > 0 may be sufficient.

  Further, as shown in FIGS. 12 and 13, the shield plate electrode 30 covers the upper portion of the drain electrode 22 with the insulating layer 34 interposed therebetween. The electrical shielding effect between the gate and the drain by the shield plate electrode 30 is higher as the thickness t1 of the insulating layer 34 is thinner. When the thickness t1 of the insulating layer 34 is relatively thick, the number of electric lines of force that run in the insulating layer 34 between the gate electrode 24 and the drain electrode 22 increases, and the electric current between the gate electrode 24 and the drain electrode 22 increases. The effective shield effect is reduced. On the other hand, when the thickness t1 of the insulating layer 34 is relatively thin, the number of lines of electric force that run in the insulating layer 34 between the gate electrode 24 and the drain electrode 22 is reduced, and the distance between the gate electrode 24 and the drain electrode 22 is reduced. This is because the electrical shielding effect is enhanced.

  As shown in FIG. 13, a source pad electrode 20 </ b> P may be disposed on the source electrode 20. The resistance component of the source electrode 20 having a finger structure can be reduced by the source pad electrode 20P.

  Further, as shown in FIG. 12, the semiconductor device 25 according to the second embodiment includes a shield plate short-circuit electrode 32 that is disposed on the substrate 10 and has a wiring structure that short-circuits the shield plate electrode 30 and the source electrode 20. Prepare.

As shown in FIG. 13, in the semiconductor device 25 according to the second embodiment, the upper end of the shield plate electrode 30 measured from the first surface of the substrate 10 is higher than the upper end of the gate electrode 24. Only _{SG is} expensive. With this configuration, the electrical shield effect between the drain and the gate can be enhanced.

  In the semiconductor device 25 according to the second embodiment, the shield plate electrode 30 short-circuited to the source electrode is disposed in the vicinity of the drain electrode 22 to electrically shield the drain and the gate, and the gate-drain capacitor. Cgd can be reduced and an increase in the gate-source capacitor Cgs can be suppressed. For this reason, the electric field concentration between the gate and the drain can be relaxed without deteriorating the high frequency characteristics.

In the semiconductor device 25 according to the second embodiment, since it is possible to reduce the gate-drain capacitor Cgd, this result, it is possible to reduce the S parameter S _12, to obtain a semiconductor device of high gain be able to.

  Other configurations are the same as those in the first embodiment, and thus redundant description is omitted.

(Modification 1)
A schematic planar pattern configuration of a semiconductor device according to Modification 1 of the second embodiment is expressed as shown in FIG. In the semiconductor device according to the first modification of the second embodiment, the shield plate electrode 30 is disposed so as to overlap a part of the drain electrode 22. That is, with respect to the length L0 of the drain electrode 22 in contact with the active region AA, the length L1 at which the shield plate electrode 30 is disposed on the active region AA has a relationship of L1 <L0.

  In FIG. 14, the schematic cross-sectional structure along the IV-IV line is the same as FIG.

  In the semiconductor device 25 according to the first modification of the second embodiment, as shown in FIG. 13, the ground electrode 50 is formed on the substrate 10 side immediately below at least a partial region of the shield plate electrode 30, and the vicinity of the drain electrode 22. In addition, the shield plate electrode 30 short-circuited to the source electrode 20 is disposed, so that the active layer 10 (AA) between the gate electrode 24 and the drain electrode 22 is sandwiched from above and below by the ground plane. For this reason, the electrical shielding effect between the gate electrode 24 and the drain electrode 22 can be increased.

  As shown in FIG. 13, the semiconductor device 25 according to the first modification of the second embodiment has a configuration in which the active layer 10 (AA) between the gate electrode 24 and the drain electrode 22 is sandwiched from above and below by the ground plane. Thus, part of the electric lines of force between the gate electrode 24 and the drain electrode 22 can be released to the ground electrode 50. For this reason, the electrical shielding effect between the gate electrode 24 and the drain electrode 22 can be increased, and the electric field concentration between the gate electrode 24 and the drain electrode 22 can be reduced.

  In the semiconductor device according to the first modification of the second embodiment, since the shield plate electrode 30 is disposed so as to overlap a part of the drain electrode 22, the drain and gate are electrically shielded, and the gate and drain are It is possible to reduce the inter-capacitor Cgd and suppress the increase in the gate-source capacitor Cgs. As a result, in the semiconductor device 25 according to the first modification of the second embodiment, a high gain semiconductor device can be obtained. Other configurations are the same as those of the second embodiment.

(Modification 2)
A schematic planar pattern configuration of the high-frequency semiconductor device according to Modification 2 of the second embodiment is expressed as shown in FIG. Further, a schematic cross-sectional structure along the VV line in FIG. 15 is represented as shown in FIG. 16, and another schematic cross-sectional structure along the VV line in FIG. 15 is represented as shown in FIG. Is done.

  In the semiconductor device according to the second modification of the second embodiment, the shield plate short-circuit electrodes 32 a, 32 b, 32 c, and 32 d are disposed so as to overlap the gate electrode 24.

  In the example of FIG. 16, the shield plate short-circuit electrodes 32a, 32b, 32c, and 32d are disposed on the gate electrode 24 via the air gap GAP. In the example of FIG. 17, the shield plate short-circuit electrodes 32 a, 32 b, 32 c, and 32 d are disposed on the gate electrode 24 via the insulating layer 34. Other configurations are the same as those of the second embodiment.

  In the configuration of the second embodiment and its modification example 1 shown in FIGS. 12 and 14, when the stripe of the gate electrode 24 becomes longer, the length in the extending direction of the source electrode 20 and the shield plate short-circuit electrode 32 becomes longer. The wiring due to the short circuit between the source electrode 20 and the shield plate electrode 30 becomes longer, and the value of the parasitic inductance connected to the source of the FET cell increases.

  In contrast, in the semiconductor device according to the second modification of the second embodiment, the shield plate short-circuit electrodes 32a, 32b, 32c, and 32d overlap the gate electrode 24 through the air gap GAP or the insulating layer 34. Therefore, the wiring distance between the source electrode 20 and the shield plate electrode 30 can be shortened. For this reason, the short-circuit wiring between the source electrode 20 and the shield plate electrode 30 can be shortened, the parasitic inductance connected to the source of the FET cell can be reduced, and the feedback impedance of each FET cell can be reduced.

  As shown in FIGS. 16 to 17, the semiconductor device 25 according to the second modification of the second embodiment forms a ground electrode 50 on the substrate 10 side immediately below at least a partial region of the shield plate electrode 30, and By arranging a shield plate electrode 30 short-circuited to the source electrode 20 in the vicinity of the electrode 22, the active layer 10 (AA) between the gate electrode 24 and the drain electrode 22 is sandwiched from above and below by a ground plane. For this reason, the electrical shielding effect between the gate electrode 24 and the drain electrode 22 can be increased.

  As shown in FIGS. 16 to 17, the semiconductor device 25 according to the first modification of the second embodiment has a configuration in which the active layer 10 (AA) between the gate electrode 24 and the drain electrode 22 is sandwiched from above and below by a ground plane. With this, a part of the electric lines of force between the gate electrode 24 and the drain electrode 22 can be released to the ground electrode 50. For this reason, the electrical shielding effect between the gate electrode 24 and the drain electrode 22 can be increased, and the electric field concentration between the gate electrode 24 and the drain electrode 22 can be reduced.

  In the semiconductor device according to the second modification of the second embodiment, the drain-gate is electrically shielded, the gate-drain capacitor Cgd is reduced, and the increase in the gate-source capacitor Cgs is suppressed. be able to. For this reason, the electric field concentration between the gate and the drain can be relaxed without deteriorating the high frequency characteristics.

Also in the semiconductor device 25 according to a second modification of the second embodiment, since it is possible to reduce the gate-drain capacitor Cgd, it is possible to reduce the S parameter S _12, a semiconductor device of high gain Can be obtained.

  As described above, according to the present embodiment, a high gain semiconductor device can be provided.

[Other embodiments]
Although this embodiment has been described, this embodiment is presented as an example and is not intended to limit the scope of the invention. The novel embodiment can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. This embodiment and its modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  Semiconductor chips mounted on the semiconductor device according to the embodiment are not limited to FETs and HEMTs, but are LDMOS (Laterally Diffused Metal-Oxide-Semiconductor Field Effect Transistors) and heterojunction bipolar transistors (HBTs). Needless to say, an amplifying element such as a transistor is also applicable.

  As described above, various embodiments that are not described herein are included.

DESCRIPTION OF SYMBOLS 10 ... Substrate 12 ... Epitaxial growth layer 16 ... Two-dimensional electron gas (2DEG) layer 18 ... Electron supply layer 20 ... Source electrode 20P ... Source pad electrode 22 ... Drain electrode 22P ... Drain pad electrode 24 ... Gate electrodes 24a, 24b ... Gate bus Line 25 ... Semiconductor device 26 ... Source region 28 ... Drain region 30 ... Shield plate electrodes 32, 32a, 32b, 32c, 32d ... Shield plate short-circuit electrode 34 ... Insulating layer 40 ... FET cell 50 ... Ground electrodes G1, G2,. G4: gate terminal electrodes S1, S2,..., S5 ... source terminal electrodes D, D1, D2,..., D4 ... drain terminal electrodes SC1 to SC5 ... VIA hole AA ... active region

Claims (15)

A substrate,
A gate electrode disposed on the first surface of the substrate, each having a plurality of fingers, a source electrode disposed adjacent to the gate electrode, and disposed opposite the source electrode across the gate electrode A drain electrode;
The gate electrode, the substrate between the gate electrode and the source electrode and the drain electrode, and an insulating layer disposed to cover at least part of the source electrode and the drain electrode;
The insulating layer is disposed on the first surface of the substrate and on the drain electrode between the gate electrode and the drain electrode, short-circuited with the source electrode, and electrically between the gate electrode and the drain electrode. A shield plate electrode for shielding
And a ground electrode disposed on the substrate surface side immediately below at least a partial region of the shield plate electrode.   The ground electrode is disposed on the substrate directly below at least a partial region of the shield plate electrode, on the inner wall of the recess formed from the second surface facing the first surface of the substrate, and on the second surface. The semiconductor device according to claim 1.   The semiconductor device according to claim 2, wherein a bottom portion of the recess portion is disposed on the substrate immediately below at least a partial region of the shield plate electrode.   The semiconductor device according to claim 1, wherein the ground electrode formed on the second surface opposite to the first surface of the substrate has a bathtub structure.   The semiconductor device according to claim 1, wherein an outer frame portion of the semiconductor device has a thickness equivalent to that of the substrate.   6. The semiconductor device according to claim 1, wherein the shield plate electrode is arranged to be separated from the gate electrode by a distance that is at least longer than the thickness of the insulating layer.   The semiconductor device according to claim 1, wherein the shield plate electrode covers at least a part of an upper portion of the drain electrode with the insulating layer interposed therebetween.   The semiconductor device according to claim 1, further comprising a shield plate short-circuit electrode that is disposed on the substrate and short-circuits the shield plate electrode and the source electrode.   The semiconductor device according to claim 8, wherein the shield plate short-circuit electrode is disposed so as to overlap the gate electrode.   The semiconductor device according to claim 8, wherein the shield plate short-circuit electrode is disposed on the gate electrode via an insulating layer.   The semiconductor device according to claim 8, wherein the shield plate short-circuit electrode is disposed on the gate electrode through an air gap.   The semiconductor device according to claim 1, wherein an upper end of the shield plate electrode measured from the first surface of the substrate is higher than an upper end of the gate electrode. A gate terminal electrode, a source terminal electrode and a drain terminal electrode, which are disposed on the first surface of the substrate and formed by bundling a plurality of fingers for each of the gate electrode, the source electrode and the drain electrode;
A VIA hole disposed under the source terminal electrode;
The ground electrode disposed on the second surface opposite to the first surface of the substrate and connected to the source terminal electrode via the VIA hole. 2. The semiconductor device according to claim 1.   The substrate may be a GaAs substrate, a SiC substrate, a GaN substrate, a substrate having a GaN epitaxial layer formed on the SiC substrate, a substrate having a heterojunction epitaxial layer made of GaN / AlGaN on the SiC substrate, a sapphire substrate, or a diamond substrate. The semiconductor device according to claim 1, wherein the semiconductor device is any one.   The semiconductor device according to claim 1, wherein the semiconductor device includes any one of a GaAs-based HEMT, a GaAs MESFET, and a GaN-based HEMT.

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