JP2001326248A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JP2001326248A
JP2001326248A JP2000142684A JP2000142684A JP2001326248A JP 2001326248 A JP2001326248 A JP 2001326248A JP 2000142684 A JP2000142684 A JP 2000142684A JP 2000142684 A JP2000142684 A JP 2000142684A JP 2001326248 A JP2001326248 A JP 2001326248A
Authority
JP
Japan
Prior art keywords
solder
semiconductor integrated
integrated circuit
circuit board
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000142684A
Other languages
Japanese (ja)
Inventor
Yasushi Murata
靖 村田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP2000142684A priority Critical patent/JP2001326248A/en
Publication of JP2001326248A publication Critical patent/JP2001326248A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device which can deal with cost reduction. SOLUTION: A solder sheet is placed over an electric circuit board 1 and a solder foil is punched at a part on the circuit wiring 12 of the electric circuit board 1 being bonded to a semiconductor integrated circuit element 5. It is then transferred onto the circuit wiring 12 and unnecessary solder foil is removed thus forming solder bumps 4 on the circuit wiring 12. Subsequently, the external bonding electrodes 6 of the semiconductor integrated circuit element is placed on the solder bumps 4 and heated, fused and cooled thus solder bonding the semiconductor integrated circuit element 5 and the electric circuit board 1.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体集積回路素
子と電気回路基板を接合して形成される半導体装置の製
造方法にかんするものであり、より詳細にはハンダ合金
を用いて半導体集積回路素子と電気回路基板とを接合す
る技術分野に属する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device formed by joining a semiconductor integrated circuit element and an electric circuit board, and more particularly, to a semiconductor integrated circuit element using a solder alloy. And the electric circuit board.

【0002】[0002]

【従来の技術】従来、半導体集積回路素子と電気回路基
板とをハンダ接合するためにに一般的に用いられてきた
製造方法は、下記のような手順である。その従来の製造
方法を図4から図10を用いて説明する。
2. Description of the Related Art Conventionally, a manufacturing method generally used for soldering a semiconductor integrated circuit element to an electric circuit board is as follows. The conventional manufacturing method will be described with reference to FIGS.

【0003】まずはじめに図4に示すように、半導体集
積回路素子5の表面に、ハンダと濡れ性の良い銅(C
u)からなる金属薄膜31を形成する。
First, as shown in FIG. 4, a surface of a semiconductor integrated circuit element 5 is coated with copper (C) having good wettability with solder.
A metal thin film 31 made of u) is formed.

【0004】つぎに図5に示すように、金属薄膜31上
の全面にレジスト膜を形成し、フォトリソグラフィー法
によって半導体集積回路素子5の外部接合電極部上のレ
ジスト膜32だけを除去してレジスト膜開口部32aを
形成する。
Next, as shown in FIG. 5, a resist film is formed on the entire surface of the metal thin film 31, and only the resist film 32 on the external bonding electrode portion of the semiconductor integrated circuit element 5 is removed by photolithography to remove the resist film. The film opening 32a is formed.

【0005】つぎに図6に示すように、金属薄膜31を
陰極としてハンダメッキ液中にて電解メッキを行い、レ
ジスト膜開口部32a部分のみにハンダ33を所定量析
出させる。
Next, as shown in FIG. 6, electrolytic plating is performed in a solder plating solution using the metal thin film 31 as a cathode, and a predetermined amount of solder 33 is deposited only on the resist film opening 32a.

【0006】つぎに図7に示すように、メッキ阻止膜と
して使用したレジスト膜32を剥離除去する。
Next, as shown in FIG. 7, the resist film 32 used as the plating stopper film is peeled off.

【0007】つぎに図8に示すように、金属薄膜31の
うちハンダ33析出部だけを残すように金属薄膜31を
エッチング除去する。
Next, as shown in FIG. 8, the metal thin film 31 is removed by etching so that only the solder 33 deposition portion of the metal thin film 31 is left.

【0008】つぎに図9に示すように、析出したハンダ
33金属部を加熱して溶融させて合金化し、接合バンプ
33aとする。
Next, as shown in FIG. 9, the deposited metal portion of the solder 33 is heated and melted to form an alloy, thereby forming a bonding bump 33a.

【0009】つぎに図10に示すように、接合バンプ3
3aを形成した半導体集積回路素子5と電気回路基板3
5とを所定の位置で対向させて重ねあわせ、その接続バ
ンプ33aと回路配線36とを接触させて、加熱するこ
とでハンダが溶融して接合が完成する。
Next, as shown in FIG.
Semiconductor integrated circuit element 5 having 3a formed thereon and electric circuit board 3
5 are placed facing each other at a predetermined position, and the connection bump 33a and the circuit wiring 36 are brought into contact with each other and heated to melt the solder and complete the joining.

【0010】上に述べた製造方法は、フォトリソグラフ
ィー法とメッキ法を中核技術とする半導体装置製造方法
であるので、高密度化に対応しやすく接合部の形状や大
きさが安定するという利点がある。また、使用する装置
類が半導体集積回路素子製造装置とかなりの部分で共通
化できるという利点もある。
The above-described manufacturing method is a method of manufacturing a semiconductor device using photolithography and plating as core technologies, and therefore has the advantage that it can be easily adapted to high density and the shape and size of the junction are stable. is there. Also, there is an advantage that the devices to be used can be shared in a considerable part with the semiconductor integrated circuit device manufacturing device.

【0011】[0011]

【発明が解決しようとする課題】しかしながら、従来の
製造方法には、製造装置が高価であり、さらに各半導体
集積回路素子に対する初期費用が高くつき、そのうえハ
ンダメッキの析出組成がばらつきやすく、また少量品種
の処理は非常に高コストであるという欠点を有してい
る。
However, in the conventional manufacturing method, the manufacturing equipment is expensive, the initial cost for each semiconductor integrated circuit element is high, the deposition composition of solder plating is apt to vary, and The processing of varieties has the disadvantage of being very expensive.

【0012】〔発明の目的〕本発明の目的は、上記課題
を解決して、低コストでの半導体装置製造が可能であ
り、また、ハンダバンプの合金組成を安定化することが
可能な半導体装置の製造方法を提供することである。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device which can solve the above-mentioned problems, can manufacture a semiconductor device at low cost, and can stabilize the alloy composition of solder bumps. It is to provide a manufacturing method.

【0013】[0013]

【課題を解決するための手段】上記目的を達成するため
に、本発明の半導体装置の製造方法においては、下記記
載の工程を採用する。
In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention employs the following steps.

【0014】本発明の半導体装置の製造方法では、半導
体集積回路素子と電気回路基板とを接合して形成される
半導体装置の製造方法であって、上記電気回路基板面上
にハンダ箔を重ね、電気回路基板の電気配線上で半導体
集積回路素子と接合される部分にあるハンダ箔を打ち抜
いて電気配線上に移動し転写したのち、不要部ハンダ箔
を取り去ることにより上記電気配線上にハンダバンプを
形成する工程と、上記ハンダバンプ部分に半導体集積回
路素子の外部接合電極部分を重ねて加熱して溶融させた
のち冷却する工程とを有し、半導体集積回路素子と電気
回路基板とをハンダ接合することを特徴としている。
According to the method of manufacturing a semiconductor device of the present invention, there is provided a method of manufacturing a semiconductor device formed by joining a semiconductor integrated circuit element and an electric circuit board. Forming a solder bump on the electric wiring by punching out the solder foil on the electric wiring of the electric circuit board at the part to be joined with the semiconductor integrated circuit element, transferring it to the electric wiring and transferring it, and removing the unnecessary part solder foil And a step of superposing an external bonding electrode portion of the semiconductor integrated circuit element on the solder bump portion, heating and melting the cooled portion, and then cooling the semiconductor integrated circuit device and the electric circuit board. Features.

【0015】〔作用〕これら従来の技術課題に対して、
本発明ではハンダシートを打ちぬいて電気回路基板上の
所望の箇所に転写することを基本技術としている。この
ことから、金属箔転写技術でのハンダバンプ形成が可能
となる。
[Operation] In response to these conventional technical problems,
The basic technique of the present invention is to punch a solder sheet and transfer it to a desired location on an electric circuit board. This makes it possible to form solder bumps by metal foil transfer technology.

【0016】この結果、本発明の半導体装置の製造方法
では、安価な製造装置のみでのバンプ形成が行なうこと
ができ、さらにフォトマスクが不要となることから少量
品種の処理コストが大幅に低減でき、またさらいハンダ
組成はハンダ箔だけに依存するので管理が容易であるな
ど、従来技術の課題を解決することが可能となる。
As a result, in the method of manufacturing a semiconductor device according to the present invention, bump formation can be performed only by an inexpensive manufacturing apparatus, and a photomask is not required. In addition, since the solder composition depends only on the solder foil, it is possible to solve the problems of the prior art, such as easy management.

【0017】また、本発明の半導体装置の製造方法で
は、金属箔転写技術として打撃ピンないし打撃ピンアレ
イを用いることから、インパクトプリンタ技術を使用し
たハンダ箔転写が可能となり、さらに低コストなハンダ
バンプ形成ができる.
In the method of manufacturing a semiconductor device according to the present invention, since a hitting pin or a hitting pin array is used as a metal foil transfer technique, a solder foil transfer using an impact printer technique can be performed. it can.

【0018】[0018]

【発明の実施の形態】本発明の最良の実施形態における
半導体装置の製造方法を図面を使用して説明する。以
下、図1、図2、および図3を用いて説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor device according to a preferred embodiment of the present invention will be described with reference to the drawings. Hereinafter, a description will be given with reference to FIGS. 1, 2, and 3.

【0019】まずはじめに図1に示すように、電気回路
基板1を基材11上に回路配線12を積層して構成す
る。電気回路基板1の基材11には厚さ0.4mmのガ
ラス繊維強化エポキシ樹脂を用い、回路配線12には厚
さ18μmの銅配線上に厚さ1μm以下のニッケルメッ
キと金メッキを施したものを用いている。
First, as shown in FIG. 1, an electric circuit board 1 is formed by laminating a circuit wiring 12 on a base material 11. The substrate 11 of the electric circuit board 1 is made of glass fiber reinforced epoxy resin having a thickness of 0.4 mm, and the circuit wiring 12 is a copper wiring having a thickness of 18 μm, which is plated with nickel and gold having a thickness of 1 μm or less. Is used.

【0020】厚さ1μm以下のニッケルメッキ膜、およ
び金メッキ膜は無電界メッキ法によって容易に形成でき
るからであり、回路配線12の表面が金であるので後述
するハンダ転写時に特段の表面処理を必要としないメリ
ットもある。
This is because a nickel plating film and a gold plating film having a thickness of 1 μm or less can be easily formed by an electroless plating method. Since the surface of the circuit wiring 12 is gold, a special surface treatment is required at the time of solder transfer described later. There is also a merit that does not.

【0021】つぎに電気回路基板1上にハンダシート2
を重ねるように配置する。このハンダシート2は厚さ3
0μmの共晶ハンダ(Sn68%+Pb32%)箔21
を厚さ15μmのSUS304シート基材22上に積層
してある。
Next, a solder sheet 2 is placed on the electric circuit board 1.
Are arranged to overlap. This solder sheet 2 has a thickness of 3
0 μm eutectic solder (Sn 68% + Pb 32%) foil 21
Is laminated on a SUS304 sheet substrate 22 having a thickness of 15 μm.

【0022】電気回路基板1とハンダシート2を重ねた
後、回路配線12上のハンダバンプ形成位置のハンダシ
ートに打撃ピン3で打撃を与えて、当該部分のハンダ箔
21をハンダシート2から回路配線12上に転写する。
After the electric circuit board 1 and the solder sheet 2 are overlaid, the solder sheet at the solder bump forming position on the circuit wiring 12 is hit with the hitting pins 3 so that the solder foil 21 at that portion is removed from the solder sheet 2 by the circuit wiring. Transfer onto No. 12.

【0023】打撃ピンの先端径は形成したいハンダバン
プの大きさに依存するが、本発明の実施の形態では先端
直径150μmの超鋼(タングステンカーバイド)製打
撃ピンを用いた。
The tip diameter of the striking pin depends on the size of the solder bump to be formed. In the embodiment of the present invention, a striking pin made of super steel (tungsten carbide) having a tip diameter of 150 μm is used.

【0024】ハンダ箔21を打撃ピン3によって回路配
線12上に転写するには、打撃ピン3による打撃荷重が
適正でなければならない。打撃荷重が過小であるとハン
ダ箔21の転写が不充分となり、過大であるとシート基
材22まで打ちぬかれてバンプ表面にシート基材22の
材質が残留する。
In order to transfer the solder foil 21 onto the circuit wiring 12 by the hitting pins 3, the hitting load by the hitting pins 3 must be appropriate. If the impact load is too small, the transfer of the solder foil 21 becomes insufficient. If the impact load is excessive, the sheet material 22 is punched out and the material of the sheet material 22 remains on the bump surface.

【0025】ハンダ箔転写時の適正な打撃荷重範囲はハ
ンダ箔21の材質とシート基材22の材質に依存してい
ることが実験的に確認できている。本発明の製造方法で
は、上述した材料では20〜80kg/cm2であっ
た。また、打撃ピン3による打撃印加時間は約0.02
秒とした。
It has been experimentally confirmed that the proper range of the impact load during the transfer of the solder foil depends on the material of the solder foil 21 and the material of the sheet substrate 22. In the manufacturing method of the present invention, the above-mentioned material was 20 to 80 kg / cm 2 . In addition, the time for applying a hit with the hitting pin 3 is about 0.02.
Seconds.

【0026】また、本発明の実施形態では実際の打撃ピ
ンを16×16の配列(400μm間隔)で構成してあ
り、複数位置のハンダ箔を同時に打ちぬいてハンダバン
プを構成している。
In the embodiment of the present invention, the actual striking pins are arranged in a 16.times.16 arrangement (interval of 400 .mu.m), and solder foils at a plurality of positions are simultaneously punched to form solder bumps.

【0027】このようにして、図2に示すように回路配
線12上にハンダバンプ4が形成される。
Thus, the solder bumps 4 are formed on the circuit wirings 12 as shown in FIG.

【0028】必要な箇所のハンダバンプ形成(ハンダ転
写)が終了した後、電気回路基板1上からハンダシート
2と打撃ピン3を撤去し、半導体集積回路素子5を半導
体集積回路素子の外部接合電極6がハンダバンプ4と対
向する位置関係で重ね合わせる。
After the formation of solder bumps (solder transfer) at required locations is completed, the solder sheet 2 and the striking pins 3 are removed from the electric circuit board 1 and the semiconductor integrated circuit elements 5 are connected to the external bonding electrodes 6 of the semiconductor integrated circuit elements. Overlap with each other in a positional relationship facing the solder bumps 4.

【0029】半導体集積回路素子の外部接合電極6はア
ルミニウム電極膜上に厚さ1μm以下のニッケルメッキ
と金メッキを施したものを用いている。
As the external bonding electrode 6 of the semiconductor integrated circuit element, an aluminum electrode film having a thickness of 1 μm or less plated with nickel and gold is used.

【0030】一般にアルミニウムとハンダとでは濡れ性
が悪く、アルミニウム電極膜そのままでは後述するハン
ダ溶融時に良好な接合が期待できないためにこのような
表面メッキ処理を加えている。
In general, aluminum and solder have poor wettability, and the aluminum electrode film itself cannot be expected to have good bonding at the time of solder melting described later.

【0031】厚さ1μm以下のニッケルメッキ膜および
金メッキ膜は無電界メッキ法によって容易かつ安価に形
成できるからである。
This is because a nickel plating film and a gold plating film having a thickness of 1 μm or less can be easily and inexpensively formed by electroless plating.

【0032】電気回路基板1と半導体集積回路素子5と
を重ね合わせたのち、ハンダバンプ4の溶融温度以上に
加熱するとハンダバンプ4が溶融して回路配線12と半
導体集積回路素子の外部接合電極6とが接続される。
When the electric circuit board 1 and the semiconductor integrated circuit element 5 are overlaid and heated to a temperature higher than the melting temperature of the solder bump 4, the solder bump 4 is melted, and the circuit wiring 12 and the external bonding electrode 6 of the semiconductor integrated circuit element are connected. Connected.

【0033】この状態で加熱を停止して冷却すると電気
回路基板1と半導体回集積路素子5との接合が完成す
る。
In this state, when heating is stopped and cooling is performed, bonding between the electric circuit board 1 and the semiconductor integrated circuit device 5 is completed.

【0034】接合完成後に、電気回路基板1と半導体集
積回路素子5との空隙にエポキシ系封止樹脂を充填し、
封止樹脂を硬化して本発明による半導体装置が完成す
る。半導体装置完成時の断面模式図を図3に示す。この
ようにして本発明の最適な実施形態が完成する。
After the joining is completed, the gap between the electric circuit board 1 and the semiconductor integrated circuit element 5 is filled with an epoxy-based sealing resin.
The semiconductor device according to the present invention is completed by curing the sealing resin. FIG. 3 is a schematic cross-sectional view of the completed semiconductor device. Thus, an optimal embodiment of the present invention is completed.

【0035】上述した本発明の最適な実施形態の製造方
法では、最適な結果を得るために電気回路基板1の基材
11にはガラス繊維強化エポキシ樹脂を用い、回路配線
12には厚さ18μmの銅配線上に厚さ1μm以下のニ
ッケルメッキと金メッキを施したものを用いている。
In the manufacturing method of the above-described preferred embodiment of the present invention, glass substrate reinforced epoxy resin is used for the base material 11 of the electric circuit board 1 and 18 μm The copper wiring is plated with nickel and gold with a thickness of 1 μm or less.

【0036】また、半導体集積回路素子の外部接合電極
6は、アルミニウム電極膜上に厚さ1μm以下のニッケ
ルメッキと金メッキを施したものを用いた。
As the external bonding electrode 6 of the semiconductor integrated circuit device, an aluminum electrode film was used in which nickel plating and gold plating having a thickness of 1 μm or less were applied.

【0037】しかし、本発明による簡便なハンダバンプ
形成は上記の材料構成でなければ実施できないものでは
なく、たとえば回路配線12を銅だけで構成しても、ま
ったく同様にハンダバンプを形成できるものである。
However, the simple formation of solder bumps according to the present invention cannot be carried out without the above-mentioned material constitution. For example, even if the circuit wiring 12 is formed only of copper, the solder bumps can be formed in exactly the same manner.

【0038】また、電気回路基板1の構成材料について
も同様で、ガラス繊維強化エポキシ樹脂以外でもFP
C、セラミックなど多様の材質が使用できる。
The same applies to the constituent material of the electric circuit board 1.
Various materials such as C and ceramic can be used.

【0039】また、ハンダシートの構成も必要なハンダ
箔厚さに応じて変更可能であり、この場合には打撃ピン
による打撃荷重と打撃印加時間の調整(適正化)さえ行
えば上記の実施の形態と同様のハンダバンプ形成が可能
である。
The configuration of the solder sheet can be changed in accordance with the required thickness of the solder foil. In this case, the above-mentioned embodiment can be implemented only by adjusting (optimizing) the impact load by the impact pin and the impact application time. The same solder bump formation as in the embodiment can be performed.

【0040】[0040]

【発明の効果】以上述べたように、本発明によれば少量
品の半導体集積回路素子に対応した半導体装置の製造な
ど、従来なし得なかった低コストでの半導体装置製造が
可能となる。また、従来技術での半導体装置実装に比し
て初期投資額が軽減されるという効果も併せもつ。
As described above, according to the present invention, it is possible to manufacture a semiconductor device at a low cost, which cannot be achieved conventionally, such as the manufacture of a semiconductor device corresponding to a small number of semiconductor integrated circuit elements. Further, there is also an effect that the initial investment amount is reduced as compared with the conventional semiconductor device mounting.

【0041】さらに、本発明ではハンダバンプ原材料と
してハンダ箔を使用するため、従来のメッキ析出法に比
してハンダバンプの合金組成を一定範囲に管理しやす
く、品質の安定化にも寄与できるのである。
Further, in the present invention, since a solder foil is used as a raw material of the solder bump, the alloy composition of the solder bump can be easily controlled within a certain range as compared with the conventional plating deposition method, and can contribute to stabilization of quality.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の形態における半導体装置の製造
方法を示す断面図である。
FIG. 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

【図2】本発明の実施の形態における半導体装置の製造
方法を示す断面図である。
FIG. 2 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

【図3】本発明の実施の形態における半導体装置の製造
方法を示す断面図である。
FIG. 3 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

【図4】従来技術における半導体装置の製造方法を示す
断面図である。
FIG. 4 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a conventional technique.

【図5】従来技術における半導体装置の製造方法を示す
断面図である。
FIG. 5 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a conventional technique.

【図6】従来技術における半導体装置の製造方法を示す
断面図である。
FIG. 6 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a conventional technique.

【図7】従来技術における半導体装置の製造方法を示す
断面図である。
FIG. 7 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a conventional technique.

【図8】従来技術における半導体装置の製造方法を示す
断面図である。
FIG. 8 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a conventional technique.

【図9】従来技術における半導体装置の製造方法を示す
断面図である。
FIG. 9 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a conventional technique.

【図10】従来技術における半導体装置の製造方法を示
す断面図である。
FIG. 10 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a conventional technique.

【符号の説明】[Explanation of symbols]

1:電気回路基板 2:ハンダシート
3:打撃ピン 4:ハンダバンプ 5:半導体集積回路素子 6:半導体回路素子の外部接続電極 11:基
材 12:回路配線 21:ハンダ箔 2
2:シート基材 31:ハンダと濡れ性の良い金属薄膜 32:
レジスト膜 32a:レジスト膜開口部 33:ハンダ 33a:接続バンプ 35:電気回路基板
36:回路配線
1: Electric circuit board 2: Solder sheet
3: hitting pin 4: solder bump 5: semiconductor integrated circuit element 6: external connection electrode of semiconductor circuit element 11: base material 12: circuit wiring 21: solder foil 2
2: Sheet base material 31: Metal thin film with good wettability with solder 32:
Resist film 32a: Opening of resist film 33: Solder 33a: Connection bump 35: Electric circuit board
36: Circuit wiring

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 半導体集積回路素子と電気回路基板とを
接合して形成される半導体装置の製造方法であって、 上記電気回路基板面上にハンダ箔を重ね、電気回路基板
の電気配線上で半導体集積回路素子と接合される部分に
あるハンダ箔を打ち抜いて電気配線上に移動し転写した
のち、不要部ハンダ箔を取り去ることにより上記電気配
線上にハンダバンプを形成する工程と、 上記ハンダバンプ部分に半導体集積回路素子の外部接合
電極部分を重ねて加熱して溶融させたのち冷却する工程
とを有し、 半導体集積回路素子と電気回路基板とをハンダ接合する
ことを特徴とする半導体装置の製造方法。
1. A method of manufacturing a semiconductor device formed by joining a semiconductor integrated circuit element and an electric circuit board, wherein a solder foil is laminated on the electric circuit board surface, and Forming a solder bump on the electrical wiring by punching out the solder foil at a portion to be joined with the semiconductor integrated circuit element, transferring the transferred foil onto the electrical wiring, and then removing the unnecessary portion of the solder foil; and forming a solder bump on the electrical wiring. A method of superposing an external bonding electrode portion of a semiconductor integrated circuit element, heating, melting, and then cooling, and soldering the semiconductor integrated circuit element and an electric circuit board. .
【請求項2】 上記ハンダ箔を打ち抜く工程は、 打撃ピンを用いる請求項1に記載の半導体装置の製造方
法。
2. The method according to claim 1, wherein the step of punching the solder foil uses a hitting pin.
【請求項3】 上記ハンダ箔を打ち抜く工程は、 打撃ピンアレイを用いる請求項1に記載の半導体装置の
製造方法。
3. The method according to claim 1, wherein the step of punching the solder foil uses a hitting pin array.
JP2000142684A 2000-05-16 2000-05-16 Method for manufacturing semiconductor device Pending JP2001326248A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000142684A JP2001326248A (en) 2000-05-16 2000-05-16 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000142684A JP2001326248A (en) 2000-05-16 2000-05-16 Method for manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
JP2001326248A true JP2001326248A (en) 2001-11-22

Family

ID=18649605

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000142684A Pending JP2001326248A (en) 2000-05-16 2000-05-16 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2001326248A (en)

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