JP2001319949A - Manufacturing method for semiconductor device - Google Patents
Manufacturing method for semiconductor deviceInfo
- Publication number
- JP2001319949A JP2001319949A JP2000135371A JP2000135371A JP2001319949A JP 2001319949 A JP2001319949 A JP 2001319949A JP 2000135371 A JP2000135371 A JP 2000135371A JP 2000135371 A JP2000135371 A JP 2000135371A JP 2001319949 A JP2001319949 A JP 2001319949A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- manufacturing
- semiconductor integrated
- integrated circuit
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体集積回路素
子と電気回路基板を接合して形成される半導体装置の製
造方法に関する発明であり、より詳細にはハンダ合金を
用いて半導体集積回路素子と電気回路基板とを接合する
技術分野に属する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device formed by joining a semiconductor integrated circuit element and an electric circuit board, and more particularly to a method for manufacturing a semiconductor integrated circuit element using a solder alloy. It belongs to the technical field of joining electric circuit boards.
【０００２】[0002]
【従来の技術】従来、半導体集積回路素子と電気回路基
板とをハンダ接合するのに一般的に用いられてきた製造
方法は、下記のような手順である。その手順を図４から
図１０を用いて説明する。2. Description of the Related Art Conventionally, a manufacturing method generally used for soldering a semiconductor integrated circuit element and an electric circuit board is as follows. The procedure will be described with reference to FIGS.
【０００３】まずはじめに、図４に示すように、半導体
集積回路素子５の表面に銅（Ｃｕ）などハンダと濡れ性
の良い金属薄膜３１を全面に形成する。First, as shown in FIG. 4, a metal thin film 31 such as copper (Cu) having good wettability with solder is formed on the entire surface of a semiconductor integrated circuit element 5.
【０００４】つぎに、図５に示すように、金属薄膜３１
上にレジスト膜３２を形成し、フォトリソグラフィー法
によって、半導体集積回路素子５の外部接合電極部上の
レジスト膜３２を除去して、レジスト開口部３２ａを形
成するようにパターンニングする。[0004] Next, as shown in FIG.
A resist film 32 is formed thereon, and the resist film 32 on the external bonding electrode portion of the semiconductor integrated circuit element 5 is removed by photolithography, and patterning is performed so as to form a resist opening 32a.
【０００５】つぎに、図６に示すように、金属薄膜３１
を陰極としてハンダメッキ液中にて電解メッキ処理を行
ない、レジスト開口部３２ａ内にハンダ３３を所定量析
出させる。[0005] Next, as shown in FIG.
Is used as a cathode, electrolytic plating is performed in a solder plating solution, and a predetermined amount of solder 33 is deposited in the resist opening 32a.
【０００６】つぎに、図７に示すように、電解メッキ処
理における阻止膜として使用したレジスト膜３２を剥離
し除去する。Next, as shown in FIG. 7, the resist film 32 used as a blocking film in the electrolytic plating process is peeled off and removed.
【０００７】つぎに、図８に示すように、金属薄膜３１
のうちハンダ３３が形成された領域だけを残すように、
金属薄膜３１をエッチングして不要部分を除去する。Next, as shown in FIG.
So that only the region where the solder 33 is formed is left.
The metal thin film 31 is etched to remove unnecessary portions.
【０００８】つぎに、図８に示すように、析出したハン
ダ３３を加熱して溶融させて合金化し、接合バンプ３３
ａとする。Next, as shown in FIG. 8, the deposited solder 33 is heated and melted to form an alloy, and
a.
【０００９】つぎに、図１０に示すように、接合バンプ
３３ａを形成した半導体集積回路素子５と、電気回路基
板３５とを所定の位置で対向させて重ねあわせ、接合バ
ンプ３３ａと回路配線３６とを接触させて加熱すること
によって、ハンダが溶融して接合が完成する。Next, as shown in FIG. 10, the semiconductor integrated circuit element 5 on which the bonding bumps 33a are formed and the electric circuit board 35 are overlapped so as to face each other at a predetermined position. By contacting and heating, the solder is melted to complete the joining.
【００１０】[0010]
【発明が解決しようとする課題】この図面を用いて説明
した製造方法は、フォトリソグラフィー法とメッキ法を
中核技術とする半導体装置製造方法であるので、高密度
化に対応しやすく接合部の形状や大きさが安定するとい
う利点がある。また、使用する装置類が半導体集積回路
素子製造装置とかなりの部分で共通化できるという利点
もある。Since the manufacturing method described with reference to this drawing is a semiconductor device manufacturing method using photolithography and plating as core technologies, it is easy to cope with high densification and the shape of the joint is easy. There is an advantage that the size is stabilized. Also, there is an advantage that the devices to be used can be shared in a considerable part with the semiconductor integrated circuit device manufacturing device.
【００１１】しかし、従来の製造方法には、製造装置が
高価である、各半導体集積回路素子に対する初期費用が
高くつく、ハンダメッキの析出組成がばらつきやすい、
少量品種の処理は非常に高コストである、という欠点が
ある。However, in the conventional manufacturing method, the manufacturing equipment is expensive, the initial cost for each semiconductor integrated circuit element is high, the deposition composition of solder plating tends to vary,
There is a disadvantage that processing of a small variety is very expensive.
【００１２】〔発明の目的〕本発明の目的は、上記のよ
うな課題点を解決して、低コストでの半導体装置製造が
可能で、また、初期投資額が軽減され、さらに、ハンダ
バンプの合金組成を管理しやすい半導体装置の製造方法
を提供することである。SUMMARY OF THE INVENTION The object of the present invention is to solve the above-mentioned problems, to manufacture a semiconductor device at low cost, to reduce the initial investment amount, and to further improve the solder bump alloy. An object of the present invention is to provide a method for manufacturing a semiconductor device whose composition can be easily controlled.
【００１３】[0013]
【課題を解決するための手段】上記目的を達成するため
に、本発明の半導体装置の製造方法は、下記記載の製造
方法を採用する。In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention employs the following manufacturing method.
【００１４】本発明の半導体装置の製造方法は、半導体
集積回路素子と電気回路基板とを接合して形成される半
導体装置の製造方法であって、上記電気回路基板面上に
ハンダ箔を重さね、その電気回路基板の電気配線上で上
記半導体集積回路素子と接合される部分にあるハンダ箔
を局所的に溶融して上記電気配線上に転写したのち不要
なハンダ箔を取り去ることでハンダバンプを形成する工
程と、上記ハンダバンプ部分に半導体集積回路素子の外
部接合電極部分を重ねて加熱溶融し冷却する工程とを有
し、半導体集積回路素子と電気回路基板とをハンダ接合
することを特徴とする。A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device formed by bonding a semiconductor integrated circuit element and an electric circuit board, wherein a solder foil is weighed on the surface of the electric circuit board. The solder bumps are locally melted on the electric wiring of the electric circuit board, and locally melted and transferred onto the electric wiring, and then the unnecessary solder foil is removed to remove the solder bumps. Forming, and heating, melting and cooling the external bonding electrode portion of the semiconductor integrated circuit device on the solder bump portion, and soldering the semiconductor integrated circuit device and the electric circuit board. .
【００１５】〔作用〕従来の技術課題にたいして、本発
明ではハンダシートを局所的に加熱して溶融させて電気
回路基板上の所望の箇所に転写することを基本技術とす
ることで、金属箔転写技術でのハンダバンプ形成が可能
となる。[Action] In contrast to the conventional technical problems, the present invention is based on the basic technique of locally heating and melting a solder sheet and transferring it to a desired portion on an electric circuit board, thereby obtaining a metal foil transfer. It becomes possible to form solder bumps by technology.
【００１６】これにより、安価な製造装置のみでのバン
プ形成が行なうことができるとともに、フォトマスクが
不要となることから少量品種の処理コストが大幅に低減
できる。また、ハンダ組成はハンダ箔だけに依存するこ
とから管理が容易であり、従来技術の課題を解決するこ
とが可能となる。さらにまた、金属箔転写技術として局
所的な加熱および溶融技術を用いることで熱転写型プリ
ンタ技術を使用したハンダ箔転写が可能となるので、さ
らに低コストなハンダバンプ形成ができる。As a result, bumps can be formed only by an inexpensive manufacturing apparatus, and a photomask is not required, so that the processing cost of a small number of products can be greatly reduced. Further, since the solder composition depends only on the solder foil, it is easy to manage, and the problem of the prior art can be solved. Furthermore, by using a local heating and melting technique as the metal foil transfer technique, solder foil transfer using a thermal transfer printer technique can be performed, so that solder bumps can be formed at lower cost.
【００１７】[0017]
【発明の実施の形態】本発明の最適な実施の形態におけ
る半導体装置の製造方法を図面を用いて説明する。以
下、図１、図２、および図３を使用して半導体装置の製
造方法を詳細に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor device according to a preferred embodiment of the present invention will be described with reference to the drawings. Hereinafter, a method of manufacturing a semiconductor device will be described in detail with reference to FIGS. 1, 2, and 3. FIG.
【００１８】まずはじめに図１に示すように、電気回路
基板１を基材１１上に回路配線１２を積層して構成す
る。First, as shown in FIG. 1, an electric circuit board 1 is formed by laminating a circuit wiring 12 on a base material 11.
【００１９】この電気回路基板１の基材１１には、厚さ
０．４ｍｍのガラス繊維強化エポキシ樹脂を用い、回路
配線１２には厚さ１８μｍの銅配線上に厚さ１μｍ以下
のニッケルメッキと金メッキを施したものを用いてい
る。これは厚さ１μｍ以下のニッケルメッキ膜・金メッ
キ膜は無電界メッキ法によって容易に形成できるからで
あり、回路配線１２の表面が金であるので、後述するハ
ンダ転写時に特段の表面処理を必要としないメリットも
ある。The substrate 11 of the electric circuit board 1 is made of glass fiber reinforced epoxy resin having a thickness of 0.4 mm, and the circuit wiring 12 is made of nickel plating having a thickness of 1 μm or less on copper wiring having a thickness of 18 μm. Gold plated ones are used. This is because a nickel plating film or a gold plating film having a thickness of 1 μm or less can be easily formed by an electroless plating method, and since the surface of the circuit wiring 12 is gold, a special surface treatment is required at the time of solder transfer described later. There is also a merit not to do.
【００２０】つぎに、電気回路基板１上にハンダシート
２を重ねる。ハンダシート２は、厚さ５０μｍの共晶ハ
ンダ（Ｓｎ６８％＋Ｐｂ３２％）箔２１を、厚さ１０μ
ｍのＳＵＳ３０４シート基材２２上に積層してある。Next, the solder sheet 2 is overlaid on the electric circuit board 1. The solder sheet 2 is made of a 50 μm thick eutectic solder (Sn 68% + Pb 32%) foil 21 having a thickness of 10 μm.
m SUS304 sheet substrate 22.
【００２１】電気回路基板１とハンダシート２を重ねた
後、回路配線１２上のハンダバンプ形成位置のハンダシ
ートを加熱ヘッド３で局所的に加熱して溶融させて、こ
の部分のハンダ箔２１をハンダシート２から回路配線１
２上に転写する。After the electric circuit board 1 and the solder sheet 2 are overlaid, the solder sheet at the position where the solder bumps are formed on the circuit wiring 12 is locally heated and melted by the heating head 3, and the solder foil 21 at this portion is soldered. Sheet 2 to circuit wiring 1
Transfer onto 2
【００２２】加熱ヘッド３の先端径は、形成したいハン
ダバンプの大きさに依存するが、本発明の実施の形態で
は先端直径１２０μｍのチタン製加熱ヘッドを用いた。Although the tip diameter of the heating head 3 depends on the size of the solder bump to be formed, a titanium heating head having a tip diameter of 120 μm was used in the embodiment of the present invention.
【００２３】ハンダ箔２１を加熱ヘッド３によって回路
配線１２上に転写するには、加熱ヘッド３による加熱お
よび溶融状態が適正でなければならない。加熱および溶
融が過小であるとハンダ箔２１の転写が不充分となり、
過大であると所望する転写領域よりも大きな領域のハン
ダが転写されるためにハンダバンプが大きくなる。In order to transfer the solder foil 21 onto the circuit wiring 12 by the heating head 3, the heating and melting state of the heating head 3 must be proper. If the heating and melting are too small, the transfer of the solder foil 21 becomes insufficient,
If it is too large, the solder in an area larger than the desired transfer area is transferred, so that the solder bump becomes large.
【００２４】ハンダ箔転写時の適正な加熱温度および加
熱時間範囲は、ハンダ箔２１の材質とシート基材２２の
材質に依存していることが実験的に確認できているが、
上述した材料系では、加熱ヘッド温度３５０℃で、加熱
時間０．０８秒〜０．２０秒の範囲が最適であった。It has been experimentally confirmed that the proper heating temperature and heating time range during the transfer of the solder foil depend on the material of the solder foil 21 and the material of the sheet base material 22.
In the above-described material system, the optimum heating head temperature was 350 ° C. and the heating time was in the range of 0.08 seconds to 0.20 seconds.
【００２５】また、本発明の実施の形態においては実際
の加熱ヘッドをを１６×１６の配列（４００μｍ間隔）
で構成してあり、複数位置のハンダ箔を同時に加熱およ
び溶融してハンダバンプを構成している。Further, in the embodiment of the present invention, the actual heating heads are arranged in a 16 × 16 array (400 μm intervals).
The solder bumps are formed by simultaneously heating and melting the solder foils at a plurality of positions.
【００２６】このようにして、図２に示すように、回路
配線１２上にハンダバンプ４を形成することができる。In this way, as shown in FIG. 2, the solder bumps 4 can be formed on the circuit wirings 12.
【００２７】必要な箇所のハンダバンプ形成（ハンダ転
写）が終了したのち、電気回路基板１上からハンダシー
ト２と加熱ヘッド３を撤去し、半導体集積回路素子５を
半導体集積回路素子の外部接合電極６がハンダバンプ４
と対向する位置関係で重ね合わせる。After the formation of solder bumps (solder transfer) at required locations is completed, the solder sheet 2 and the heating head 3 are removed from the electric circuit board 1 and the semiconductor integrated circuit elements 5 are connected to the external bonding electrodes 6 of the semiconductor integrated circuit elements. Is solder bump 4
Are superimposed on each other in a positional relationship facing each other.
【００２８】半導体集積回路素子の外部接合電極６は、
アルミニウム電極膜上に厚さ１μｍ以下のニッケルメッ
キと金メッキを施したものを用いている。The external bonding electrode 6 of the semiconductor integrated circuit device
An aluminum electrode film having a thickness of 1 μm or less plated with nickel and gold is used.
【００２９】一般にアルミニウムとハンダとでは濡れ性
が悪く、アルミニウム電極膜そのままでは、後述するハ
ンダ溶融時に良好な接合が期待できないために、このよ
うな表面メッキ処理を加えている。厚さ１μｍ以下のニ
ッケルメッキ膜および金メッキ膜は、無電界メッキ法に
よって容易かつ安価に形成できるからである。In general, aluminum and solder have poor wettability, and if the aluminum electrode film is used as it is, good bonding cannot be expected at the time of solder melting described later, such a surface plating treatment is applied. This is because a nickel plating film and a gold plating film having a thickness of 1 μm or less can be easily and inexpensively formed by an electroless plating method.
【００３０】電気回路基板１と半導体集積回路素子５と
を重ね合わせたのち、ハンダバンプ４の溶融温度以上に
加熱すると、ハンダバンプ４が溶融して回路配線１２と
半導体集積回路素子の外部接合電極６とが接続される。
この状態で加熱を停止して冷却すると電気回路基板１と
半導体集積回路素子５との接合が完成する。When the electric circuit board 1 and the semiconductor integrated circuit element 5 are overlaid and heated to a temperature higher than the melting temperature of the solder bump 4, the solder bump 4 is melted and the circuit wiring 12 and the external bonding electrode 6 of the semiconductor integrated circuit element are connected. Is connected.
When heating is stopped and cooling is performed in this state, bonding between the electric circuit board 1 and the semiconductor integrated circuit element 5 is completed.
【００３１】接合完成後に、電気回路基板１と半導体集
積回路素子５との空隙にエポキシ系封止樹脂を充填し、
封止樹脂を硬化して本発明による半導体装置が完成す
る。After joining is completed, the gap between the electric circuit board 1 and the semiconductor integrated circuit element 5 is filled with an epoxy-based sealing resin.
The semiconductor device according to the present invention is completed by curing the sealing resin.
【００３２】半導体装置完成時の断面形状をを図３に示
す。このようにして本発明の最適な実施形態が完成す
る。FIG. 3 shows a sectional shape of the completed semiconductor device. Thus, an optimal embodiment of the present invention is completed.
【００３３】上述した本発明の最適な実施形態の製造方
法では、最適な結果を得るために電気回路基板１の基材
１１にはガラス繊維強化エポキシ樹脂を用い、回路配線
１２には厚さ１８μｍの銅配線上に厚さ１μｍ以下のニ
ッケルメッキと金メッキを形成したものを用いている。In the manufacturing method of the above-described preferred embodiment of the present invention, glass substrate reinforced epoxy resin is used for the base material 11 of the electric circuit board 1 and the circuit wiring 12 has a thickness of 18 μm in order to obtain optimum results. Formed with nickel plating and gold plating with a thickness of 1 μm or less on the copper wiring of FIG.
【００３４】また、半導体集積回路素子の外部接合電極
６は、アルミニウム電極膜上に厚さ１μｍ以下のニッケ
ルメッキと金メッキを形成したものを用いた。As the external bonding electrode 6 of the semiconductor integrated circuit device, an aluminum electrode film on which nickel plating and gold plating having a thickness of 1 μm or less were formed was used.
【００３５】しかし、本発明による簡便なハンダバンプ
形成は上記の材料構成でなければ実施できないものでは
なく、たとえば回路配線１２を銅だけで構成しても、以
上の説明とまったく同様にハンダバンプを形成できる。However, simple solder bump formation according to the present invention cannot be performed unless the above-mentioned material composition is employed. For example, even if the circuit wiring 12 is formed only of copper, the solder bump can be formed in exactly the same manner as described above. .
【００３６】また、電気回路基板１の構成材料について
も同様で、ガラス繊維強化エポキシ樹脂以外でもフレキ
シブル・プリント基板（ＦＰＣ）や、セラミックなど多
様の材質が使用できる。The same applies to the constituent materials of the electric circuit board 1. Various materials such as a flexible printed circuit board (FPC) and ceramic can be used other than the glass fiber reinforced epoxy resin.
【００３７】また、ハンダシートの構成も必要なハンダ
箔厚さに応じて変更可能であり、この場合には加熱ヘッ
ドによる加熱温度と時間の調整（適正化）さえ行えば、
上記実施の形態と同様のハンダバンプ形成が可能であ
る。The configuration of the solder sheet can be changed according to the required solder foil thickness. In this case, if the heating temperature and time by the heating head are adjusted (optimized),
Solder bump formation similar to that of the above embodiment is possible.
【００３８】[0038]
【発明の効果】以上述べたように、本発明の半導体装置
の製造方法によれば、少量品の半導体集積回路素子に対
応した半導体装置の製造など、従来なし得なかった低コ
ストでの半導体装置製造が可能となる。また、従来技術
での半導体装置実装に比して初期投資額が軽減されると
いう効果も併せもつ。As described above, according to the method of manufacturing a semiconductor device according to the present invention, the semiconductor device can be manufactured at a low cost, which cannot be achieved by conventional methods, such as manufacturing of a semiconductor device corresponding to a small number of semiconductor integrated circuit elements. Manufacturing becomes possible. Further, there is also an effect that the initial investment amount is reduced as compared with the conventional semiconductor device mounting.
【００３９】さらに、本発明の半導体装置の製造方法で
は、ハンダバンプ原材料としてハンダ箔を使用するた
め、従来のメッキ析出法に比してハンダバンプの合金組
成を一定範囲に管理しやすく、品質の安定化にも寄与で
きるのである。Further, in the method of manufacturing a semiconductor device according to the present invention, since a solder foil is used as a raw material for the solder bump, the alloy composition of the solder bump can be easily controlled within a certain range as compared with the conventional plating deposition method, and the quality can be stabilized. It can also contribute to.
【図１】本発明の実施の形態における半導体装置の製造
方法を示す断面図である。FIG. 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.
【図２】本発明の実施の形態における半導体装置の製造
方法を示す断面図である。FIG. 2 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
【図３】本発明の実施の形態における半導体装置の製造
方法を示す断面図である。FIG. 3 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;
【図４】従来技術による半導体装置の製造方法を示す断
面図である。FIG. 4 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a conventional technique.
【図５】従来技術による半導体装置の製造方法を示す断
面図である。FIG. 5 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a conventional technique.
【図６】従来技術による半導体装置の製造方法を示す断
面図である。FIG. 6 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a conventional technique.
【図７】従来技術による半導体装置の製造方法を示す断
面図である。FIG. 7 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a conventional technique.
【図８】従来技術による半導体装置の製造方法を示す断
面図である。FIG. 8 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a conventional technique.
【図９】従来技術による半導体装置の製造方法を示す断
面図である。FIG. 9 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a conventional technique.
【図１０】従来技術による半導体装置の製造方法を示す
断面図である。FIG. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a conventional technique.
１：電気回路基板 ２：ハンダシート
３：加熱ヘッド ４：ハンダバンプ ５：半導体集積回路素子 ６：半導体回路素子の外部接続電極 １１：
基材 １２：回路配線 ２１：ハンダ箔 ２
２：シート基材 ３１：ハンダと濡れ性の良い金属薄膜 ３２：
レジスト膜 ３２ａ：レジスト膜開口部 ３３：ハンダ ３３ａ：接続バンプ ３５：電気回路基板
３６：回路配線1: Electric circuit board 2: Solder sheet
3: Heating head 4: Solder bump 5: Semiconductor integrated circuit device 6: External connection electrode of semiconductor circuit device 11:
Base material 12: Circuit wiring 21: Solder foil 2
2: Sheet base material 31: Metal thin film with good wettability with solder 32:
Resist film 32a: Opening of resist film 33: Solder 33a: Connection bump 35: Electric circuit board
36: Circuit wiring
Claims (3)
接合して形成される半導体装置の製造方法であって、 上記電気回路基板面上にハンダ箔を重さね、その電気回
路基板の電気配線上で上記半導体集積回路素子と接合さ
れる部分にあるハンダ箔を局所的に溶融して上記電気配
線上に転写したのち不要なハンダ箔を取り去ることでハ
ンダバンプを形成する工程と、 上記ハンダバンプ部分に半導体集積回路素子の外部接合
電極部分を重ねて加熱溶融し冷却する工程とを有し、 半導体集積回路素子と電気回路基板とをハンダ接合する
ことを特徴とする半導体装置の製造方法。1. A method of manufacturing a semiconductor device formed by joining a semiconductor integrated circuit element and an electric circuit board, comprising: laying a solder foil on the electric circuit board surface; Forming a solder bump by locally melting and transferring the solder foil at a portion to be joined to the semiconductor integrated circuit element on the wiring and transferring the solder foil onto the electric wiring; and forming the solder bump by removing the unnecessary solder foil. And a step of heating, melting, and cooling an external bonding electrode portion of the semiconductor integrated circuit element, and solder-bonding the semiconductor integrated circuit element and the electric circuit board.
る工程は、 加熱ピンを用いる請求項１に記載の半導体装置の製造方
法。2. The method according to claim 1, wherein the step of locally melting and transferring the solder foil uses a heating pin.
る工程は、 加熱ピンアレイを用いる請求項１に記載の半導体装置の
製造方法。3. The method according to claim 1, wherein the step of locally melting and transferring the solder foil uses a heating pin array.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000135371A JP2001319949A (en) | 2000-05-09 | 2000-05-09 | Manufacturing method for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000135371A JP2001319949A (en) | 2000-05-09 | 2000-05-09 | Manufacturing method for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001319949A true JP2001319949A (en) | 2001-11-16 |
Family
ID=18643459
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000135371A Pending JP2001319949A (en) | 2000-05-09 | 2000-05-09 | Manufacturing method for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001319949A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010093031A1 (en) * | 2009-02-13 | 2010-08-19 | 千住金属工業株式会社 | Solder bump formation on a circuit board using a transfer sheet |
| JP2016132178A (en) * | 2015-01-20 | 2016-07-25 | 有限会社日三エンジニアリング | Heat stamping head, foil stamping device and foil stamping method using the same, and articles to be transferred that are acquired thereby |
-
2000
- 2000-05-09 JP JP2000135371A patent/JP2001319949A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010093031A1 (en) * | 2009-02-13 | 2010-08-19 | 千住金属工業株式会社 | Solder bump formation on a circuit board using a transfer sheet |
| CN102396297A (en) * | 2009-02-13 | 2012-03-28 | 千住金属工业株式会社 | Solder bump formation on a circuit board using a transfer sheet |
| JP4962626B2 (en) * | 2009-02-13 | 2012-06-27 | 千住金属工業株式会社 | Solder bump formation on circuit board using transfer sheet |
| KR101206311B1 (en) | 2009-02-13 | 2012-11-29 | 센주긴조쿠고교 가부시키가이샤 | Solder bump formation on a circuit board using a transfer sheet |
| US8701973B2 (en) | 2009-02-13 | 2014-04-22 | Senju Metal Industry Co., Ltd. | Solder bump formation on a circuit board using a transfer sheet |
| TWI462676B (en) * | 2009-02-13 | 2014-11-21 | Senju Metal Industry Co | The solder bumps for the circuit substrate are formed using the transfer sheet |
| JP2016132178A (en) * | 2015-01-20 | 2016-07-25 | 有限会社日三エンジニアリング | Heat stamping head, foil stamping device and foil stamping method using the same, and articles to be transferred that are acquired thereby |
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