JP2001319996A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device

Info

Publication number
JP2001319996A
JP2001319996A JP2000137480A JP2000137480A JP2001319996A JP 2001319996 A JP2001319996 A JP 2001319996A JP 2000137480 A JP2000137480 A JP 2000137480A JP 2000137480 A JP2000137480 A JP 2000137480A JP 2001319996 A JP2001319996 A JP 2001319996A
Authority
JP
Japan
Prior art keywords
silicon substrate
electrode
extraction electrode
semiconductor
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000137480A
Other languages
Japanese (ja)
Other versions
JP3744772B2 (en
Inventor
Tetsuya Okada
哲也 岡田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP2000137480A priority Critical patent/JP3744772B2/en
Publication of JP2001319996A publication Critical patent/JP2001319996A/en
Application granted granted Critical
Publication of JP3744772B2 publication Critical patent/JP3744772B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
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    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
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    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device, which gives a compact package where a packaging area is reduced, at the same time, uses a silicon substrate, does not have any via holes, and can manufacture inexpensively. SOLUTION: A semiconductor device 410 is formed on a silicon substrate 40, then a demountable electrode 44 that is buried into the silicon substrate 40 is formed, an electrode 45 of the semiconductor device 410 is electrically connected to the demountable electrode 44, covering is made by an insulating resin 47 for removing the silicon substrate 40 from a back surface, thus achieving the manufacturing method of the semiconductor device for appropriately packaging an extremely thin and inexpensive, minute semiconductor chip.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は半導体装置の製造方
法に関し、特にシリコン基板に設けた半導体素子を形成
し且つシリコン基板に設けた取り出し電極を用いて半導
体素子の組み立てを行う半導体装置の製造方法に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a semiconductor element provided on a silicon substrate is formed and the semiconductor element is assembled using an extraction electrode provided on the silicon substrate. About.

【０００２】[0002]

【従来の技術】従来の半導体装置の組立工程において
は、ウェハからダイシングして分離した半導体チップを
リードフレームに固着し、金型と樹脂注入によるトラン
スファーモールドによって半導体チップを封止し、リー
ドフレームを切断して個々の半導体装置毎に分離する、
という工程が行われている。この手法によって得れらる
半導体装置は、図１１に示したように、半導体チップ１
の周囲を樹脂層２で被覆し、該樹脂層２の側部から外部
接続用のリード端子３を導出した構造になる（例えば特
開平０５−１２９４７３号）。2. Description of the Related Art In a conventional semiconductor device assembling process, a semiconductor chip separated by dicing from a wafer is fixed to a lead frame, and the semiconductor chip is sealed by a transfer mold using a mold and resin injection. Cutting and separating into individual semiconductor devices,
Is performed. The semiconductor device obtained by this method is, as shown in FIG.
Is covered with a resin layer 2 and a lead terminal 3 for external connection is led out from a side portion of the resin layer 2 (for example, JP-A-05-129473).

【０００３】この構造は、樹脂層２の外側にリード端子
３が突出すること、リードフレームの加工精度の問題や
金型との位置あわせ精度の問題により、外形寸法とその
実装面積の縮小化には限界が見えていた。[0003] This structure reduces the external dimensions and the mounting area due to the protrusion of the lead terminals 3 outside the resin layer 2, the problem of the processing accuracy of the lead frame and the problem of the positioning accuracy with the mold. Was seeing the limits.

【０００４】近年、外形寸法を半導体チップサイズと同
等あるいは近似した寸法にまで縮小する事が可能な、ウ
ェハスケールＣＳＰ（チップサイズパッケージ）が注目
され始めている。これは、図１２（Ａ）を参照して、半
導体ウェハ１１に各種拡散などの前処理を施して多数の
半導体チップ１２を形成し、図１２（Ｂ）に示したよう
に半導体ウェハ１１の上部を樹脂層１３で被覆すると共
に樹脂層１３表面に外部接続用の電極１４を導出し、そ
の後半導体ウェハ１１のダイシングラインに沿って半導
体チップ１１を分割して、図１２（Ｃ）に示したような
完成品としたものである。樹脂層１３は半導体チップ１
２の表面（裏面を被覆する場合もある）を被覆するだけ
であり、半導体チップ１２の側壁にはシリコン基板が露
出する。電極１４は樹脂層１３下部に形成された集積回
路網と電気的に接続されており、実装基板上に形成した
導電パターンに対して電極１４を対向接着することによ
りこの半導体装置の実装が実現する。In recent years, attention has been paid to a wafer-scale CSP (chip size package) capable of reducing an outer dimension to a size similar to or close to a semiconductor chip size. In this, referring to FIG. 12A, a large number of semiconductor chips 12 are formed by performing various pretreatments such as diffusion on a semiconductor wafer 11, and an upper portion of the semiconductor wafer 11 is formed as shown in FIG. Is covered with a resin layer 13, electrodes 14 for external connection are led out on the surface of the resin layer 13, and then the semiconductor chips 11 are divided along dicing lines of the semiconductor wafer 11, as shown in FIG. It is a finished product. The resin layer 13 is the semiconductor chip 1
2 only covers the front surface (which may cover the back surface) of the semiconductor chip 12, and the silicon substrate is exposed on the side wall of the semiconductor chip 12. The electrode 14 is electrically connected to an integrated circuit network formed below the resin layer 13, and the semiconductor device is mounted by bonding the electrode 14 to a conductive pattern formed on a mounting substrate. .

【０００５】斯かる半導体装置は、装置のパッケージサ
イズが半導体チップのチップサイズと同等であり、実装
基板に対しても対向接着で済むので、実装占有面積を大
幅に減らすことが出来る利点を有する。また、後工程に
拘わるコストを大幅に減じることが出来る利点を有する
ものである。（例えば、特開平９−６４０４９号）そこ
で、チップサイズが１ｍｍ角に満たない程度のチップで
は図１３（Ａ）（Ｂ）（Ｃ）に示すように実装されてい
る。[0005] Such a semiconductor device has the advantage that the package size of the device is equivalent to the chip size of the semiconductor chip, and the device can be adhered to the mounting substrate by opposing, so that the area occupied by the mounting can be greatly reduced. Further, there is an advantage that the cost associated with the post-process can be significantly reduced. (For example, Japanese Patent Application Laid-Open No. 9-64049) Therefore, chips having a chip size of less than 1 mm square are mounted as shown in FIGS. 13A, 13B, and 13C.

【０００６】図中、２１はセラミックやガラスエポキシ
等からなる絶縁基板であり、それらが１枚あるいは数枚
重ね合わされて、板厚が２５０〜３５０μｍと製造工程
における機械的強度を維持し得る厚みと、長辺×短辺が
１．０ｍｍ×０．８ｍｍ程度の矩形形状を有している。In FIG. 1, reference numeral 21 denotes an insulating substrate made of ceramic, glass epoxy, or the like, and one or several of them are superposed to have a thickness of 250 to 350 μm, which can maintain the mechanical strength in the manufacturing process. Has a rectangular shape with a long side × short side of about 1.0 mm × 0.8 mm.

【０００７】絶縁基板２１の表面には、タングステン等
の金属ペーストの印刷と、電解メッキ法による前記金属
ペースト上への金メッキによって導電パターンを形成
し、アイランド部２２と電極部２３ａ、２３ｂとを形成
している。アイランド部２２の上には、Ａｇペーストな
どの導電性接着剤２４によって半導体チップ２５が固着
されている。On the surface of the insulating substrate 21, a conductive pattern is formed by printing a metal paste such as tungsten and gold plating on the metal paste by an electrolytic plating method to form an island portion 22 and electrode portions 23a and 23b. are doing. A semiconductor chip 25 is fixed on the island portion 22 by a conductive adhesive 24 such as an Ag paste.

【０００８】半導体チップ２５の表面にはアルミ電極パ
ッド２６が形成され、電極パッド２６と電極部２３ａ、
２３ｂとが、ボンディングワイヤ２７によって電気接続
される。電極パッド２６側に１ｓｔボンド、電極部２３
側に２ｎｄボンドが打たれる。バイポーラトランジスタ
で有れば、電極部２３ａ、２３ｂはエミッタとベースに
対応し、パワーＭＯＳＦＥＴで有れば、ソースとゲート
に対応する。An aluminum electrode pad 26 is formed on the surface of the semiconductor chip 25, and the electrode pad 26 and the electrode portion 23a are formed.
23b are electrically connected to each other by a bonding wire 27. 1st bond on electrode pad 26 side, electrode section 23
A 2nd bond is struck on the side. If it is a bipolar transistor, the electrode portions 23a and 23b correspond to the emitter and the base, and if it is a power MOSFET, it corresponds to the source and the gate.

【０００９】前記絶縁基板２１の裏面側には、同じく金
メッキ層によって第１の外部接続電極２８と第２の外部
接続電極２９ａ、２９ｂが形成される。絶縁基板２１に
はこれを貫通する、円形の第１のビアホール３０と第２
のビアホール３１ａ、３１ｂが形成され、各ビアホール
３０、３１ａ、３１ｂの内部はタングステンなどの導電
材料によって埋設される。素材としては、電気的導電性
と熱伝導性に優れた素材で埋設する。該ビアホール３
０、３１ａ、３１ｂによって、アイランド部２２と第１
の外部接続電極２８とを、電極部２３ａ、２３ｂと第２
の外部接続電極２９ａ、２９ｂとを、各々電気接続す
る。第１の外部接続電極２８が例えばコレクタ電極とな
り、第２の外部接続電極２９ａ、２９ｂが例えばベー
ス、エミッタ電極となる。A first external connection electrode 28 and second external connection electrodes 29a and 29b are formed on the back surface of the insulating substrate 21 by the same gold plating layer. A circular first via hole 30 and a second
Are formed, and the inside of each via hole 30, 31a, 31b is buried with a conductive material such as tungsten. The material is buried with a material having excellent electrical and thermal conductivity. The via hole 3
0, 31a and 31b, the island portion 22 and the first
Of the external connection electrode 28 and the electrode portions 23a and 23b and the second
Are electrically connected to the external connection electrodes 29a and 29b, respectively. The first external connection electrodes 28 are, for example, collector electrodes, and the second external connection electrodes 29a, 29b are, for example, base and emitter electrodes.

【００１０】絶縁基板２１の上方は、半導体チップ２５
とボンディングワイヤ２７とを封止する樹脂層３２で被
覆される。樹脂層３２は絶縁基板２１と共にパッケージ
外形を構成する。パッケージの周囲４側面は樹脂層３２
と絶縁基板２１の切断面で形成され、パッケージの上面
は平坦化した樹脂層３２の表面、パッケージの下面は絶
縁基板２１の裏面側で形成される。The semiconductor chip 25 is located above the insulating substrate 21.
And the bonding wire 27 is covered with a resin layer 32. The resin layer 32 forms an outer shape of the package together with the insulating substrate 21. The four sides around the package are resin layers 32
The upper surface of the package is formed on the flattened surface of the resin layer 32, and the lower surface of the package is formed on the back surface side of the insulating substrate 21.

【００１１】[0011]

【発明が解決しようとする課題】しかしながら図１３で
示した実装構造においていろいろな問題点がある。第１
に、セラミックやガラスエポキシ等の高価な基板材料を
用い、更にタングステン等の高価な金属ペーストを用い
ているので、ローコストの実装構造とは言えない。第２
に、両面の電極等を接続するために、絶縁基板を貫通す
るビアホールが不可欠であり、この加工精度も０．１５
mm程度が限界であるので、更なる小型化の障害となって
いる。第３にこのビアホール内を金属ペーストで充填す
るため作業性が極めて悪く、コスト高の原因となる。第
４に半導体チップを形成する前工程と絶縁基板を用いて
半導体チップを組み立てる後工程に区分されており、リ
ードタイムが長く、製造コストも高くなる等々の多くの
問題点が発生している。However, there are various problems in the mounting structure shown in FIG. First
In addition, since an expensive substrate material such as ceramic or glass epoxy is used, and an expensive metal paste such as tungsten is used, the mounting structure cannot be said to be low cost. Second
In addition, in order to connect electrodes and the like on both sides, a via hole penetrating the insulating substrate is indispensable, and the processing accuracy is 0.15.
The limit of about mm is an obstacle to further miniaturization. Third, since the inside of the via hole is filled with a metal paste, workability is extremely poor, which causes an increase in cost. Fourth, the process is divided into a pre-process for forming a semiconductor chip and a post-process for assembling a semiconductor chip using an insulating substrate, which causes many problems such as a long lead time and a high manufacturing cost.

【００１２】[0012]

【課題を解決するための手段】本発明は上述した種々の
問題点に鑑みてなされたものであり、シリコン基板の予
定の素子形成領域に半導体素子を形成する工程と、前記
シリコン基板の前記素子形成領域の外側に位置し予定の
取り出し電極となる部分にトレンチ溝を形成する工程
と、前記トレンチ溝の少なくとも側面および底面に酸化
膜を形成した後、前記トレンチ溝の底面の前記酸化膜を
除去する工程と、前記トレンチ溝に埋め込まれた導電性
金属よりなる取り出し電極を形成する工程と、前記半導
体素子の電極と前記取り出し電極とを電気的に接続する
工程と、前記シリコン基板表面を絶縁性樹脂で被覆する
工程と、前記シリコン基板を裏面より除去して前記取り
出し電極の裏面を露出する工程と、前記絶縁性樹脂をダ
イシングして個別の半導体素子に分離する工程とから構
成されることに特徴を有する。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned various problems, and comprises a step of forming a semiconductor element in a predetermined element formation region of a silicon substrate; Forming a trench in a portion which is located outside the formation region and which is to be a take-out electrode; forming an oxide film on at least side surfaces and a bottom surface of the trench groove; and removing the oxide film on the bottom surface of the trench groove. Forming an extraction electrode made of a conductive metal embedded in the trench, electrically connecting the electrode of the semiconductor element and the extraction electrode, and insulating the surface of the silicon substrate. A step of coating with a resin, a step of removing the silicon substrate from a back surface to expose a back surface of the extraction electrode, and a step of dicing the insulating resin to separate Characterized in being composed of a separating the conductive element.

【００１３】[0013]

【発明の実施の形態】図１から図１０を参照して本発明
の半導体装置の製造方法を詳述する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor device according to the present invention will be described in detail with reference to FIGS.

【００１４】本発明は、シリコン基板の予定の素子形成
領域に半導体素子を形成する工程と、前記シリコン基板
の前記素子形成領域の外側に位置し予定の取り出し電極
となる部分にトレンチ溝を形成する工程と、前記トレン
チ溝の少なくとも側面および底面に酸化膜を形成した
後、前記トレンチ溝の底面の前記酸化膜を除去する工程
と、前記トレンチ溝に埋め込まれた導電性金属よりなる
取り出し電極を形成する工程と、前記半導体素子の電極
と前記取り出し電極とを電気的に接続する工程と、前記
シリコン基板表面を絶縁性樹脂で被覆する工程と、前記
シリコン基板を裏面より除去して前記取り出し電極の裏
面を露出する工程と、前記シリコン基板の裏面に露出さ
れた前記素子形成領域および前記取り出し電極に接続電
極を形成する工程と、前記絶縁性樹脂をダイシングして
個別の半導体素子に分離する工程から構成されている。According to the present invention, a semiconductor element is formed in a predetermined element formation region of a silicon substrate, and a trench is formed in a portion of the silicon substrate located outside the element formation region and serving as a predetermined extraction electrode. Forming an oxide film on at least a side surface and a bottom surface of the trench groove, removing the oxide film on the bottom surface of the trench groove, and forming an extraction electrode made of a conductive metal embedded in the trench groove. The step of electrically connecting the electrode of the semiconductor element and the extraction electrode, the step of coating the surface of the silicon substrate with an insulating resin, and the step of removing the silicon substrate from the back surface and forming the extraction electrode. A step of exposing a back surface, and a step of forming a connection electrode on the element formation region and the extraction electrode exposed on the back surface of the silicon substrate. And a step of separating into individual semiconductor devices by dicing the insulating resin.

【００１５】本発明の第１の工程は、図１に示す如く、
シリコン基板４０の予定の素子形成領域４１に半導体素
子４１０を形成することにある。In the first step of the present invention, as shown in FIG.
The semiconductor element 410 is to be formed in a predetermined element formation region 41 of the silicon substrate 40.

【００１６】本工程では、約４００μｍの厚みのシリコ
ン基板４０を準備し、シリコン基板４０の素子形成領域
４１に既知の選択拡散法を用いてベース領域４１１、エ
ミッタ領域４１２およびベース領域４１１を囲むように
アニュラーリング領域４１３を形成する。シリコン基板
４０はＮ＋型シリコン基板にＮ−型エピタキシャル層を
積層したものを用い、Ｐ型のベース領域４１１とＮ＋型
のエミッタ領域４１２およびＮ＋型のアニュラーリング
領域４１３を形成する。ここでは、ＮＰＮ型プレーナト
ランジスタを例に挙げたが、ＰＮＰ型プレーナトランジ
スタ、ＭＯＳＦＥＴ等の半導体素子４１０を形成しても
良い。In this step, a silicon substrate 40 having a thickness of about 400 μm is prepared, and a base region 411, an emitter region 412, and a base region 411 are formed in the element formation region 41 of the silicon substrate 40 by using a known selective diffusion method. An annular ring region 413 is formed. The silicon substrate 40 is obtained by laminating an N − type epitaxial layer on an N + type silicon substrate, and forms a P type base region 411, an N + type emitter region 412, and an N + type annular ring region 413. Here, an NPN type planar transistor has been described as an example, but a semiconductor element 410 such as a PNP type planar transistor or MOSFET may be formed.

【００１７】本発明の第２の工程は、図２に示す如く、
シリコン基板４０の素子形成領域４１の外側に位置し予
定の取り出し電極４４となる部分にトレンチ溝４２を形
成することにある。In the second step of the present invention, as shown in FIG.
The purpose of the present invention is to form a trench 42 in a portion of the silicon substrate 40 which is located outside the element formation region 41 and is to be a predetermined extraction electrode 44.

【００１８】本工程では、素子形成領域４１の外側に位
置し予定の取り出し電極４４となる部分を露出して他の
部分をホトレジスト層で被覆し、シリコン基板４０表面
を選択的にドライエッチングして約１００μｍの深さの
トレンチ４２を形成する。予定の取り出し電極４４はボ
ンディングワイヤーが固着できるように一辺２００μｍ
の正方形状にトレンチ溝４２が形成される。なお、半導
体素子４１０は酸化膜（図示しない）で被覆されて保護
されている。In this step, a portion which is located outside the element forming region 41 and is to be the intended extraction electrode 44 is exposed, the other portion is covered with a photoresist layer, and the surface of the silicon substrate 40 is selectively dry-etched. A trench 42 having a depth of about 100 μm is formed. The planned extraction electrode 44 is 200 μm on a side so that a bonding wire can be fixed.
A trench groove 42 is formed in a square shape. The semiconductor element 410 is covered and protected by an oxide film (not shown).

【００１９】本発明の第３の工程は、図３および図４に
示す如く、トレンチ溝４２の少なくとも側面および底面
に酸化膜４３を形成した後、トレンチ溝４２の底面の酸
化膜４３を除去することにある。In the third step of the present invention, as shown in FIGS. 3 and 4, an oxide film 43 is formed on at least the side and bottom surfaces of the trench groove 42, and then the oxide film 43 on the bottom surface of the trench groove 42 is removed. It is in.

【００２０】本工程では、シリコン基板４０表面には減
圧ＣＶＤ法で全面に約５０００Åから１００００Åの厚
い酸化膜４３が形成される（図２）。従って、酸化膜４
３はシリコン基板４１表面、トレンチ溝４２の側面およ
び底面に形成される。続いてこの酸化膜４３を異方性ド
ライエッチングしてシリコン基板４０表面およびトレン
チ溝４２底面の酸化膜４３を選択的に除去する（図
３）。これによりトレンチ溝４２の側面に酸化膜４３が
残る。In this step, a thick oxide film 43 of about 5,000 to 10,000 is formed on the entire surface of the silicon substrate 40 by the low pressure CVD method (FIG. 2). Therefore, the oxide film 4
3 is formed on the surface of the silicon substrate 41 and on the side and bottom surfaces of the trench 42. Subsequently, the oxide film 43 is anisotropically dry-etched to selectively remove the oxide film 43 on the surface of the silicon substrate 40 and the bottom of the trench 42 (FIG. 3). As a result, the oxide film 43 remains on the side surface of the trench 42.

【００２１】本発明の第４の工程は、図５に示す如く、
トレンチ溝４２に埋め込まれた導電性金属よりなる取り
出し電極４４を形成することにある。In the fourth step of the present invention, as shown in FIG.
The purpose is to form an extraction electrode 44 made of a conductive metal buried in the trench 42.

【００２２】本工程では、銅または金等の導電性金属を
電気メッキして、少なくともトレンチ溝４２を埋める。
導電性金属のメッキ膜はトレンチ溝４２を含めてシリコ
ン基板４０に形成された後、ホトエッチングによりトレ
ンチ溝４２の導電性金属のメッキ膜を残してエッチング
除去される。In this step, at least the trench 42 is filled by electroplating a conductive metal such as copper or gold.
After the conductive metal plating film including the trench groove 42 is formed on the silicon substrate 40, the conductive metal plating film is etched away by photoetching while leaving the conductive metal plating film in the trench groove 42.

【００２３】本発明の第５の工程は、図６に示す如く、
半導体素子４１０の電極４５と取り出し電極４４とを電
気的に接続することにある。In the fifth step of the present invention, as shown in FIG.
The purpose is to electrically connect the electrode 45 of the semiconductor element 410 and the extraction electrode 44.

【００２４】本工程では、半導体素子４１０の電極パッ
ド４５と取り出し電極４４とをボールボンディングによ
り各々ボンディングワイヤ４６で接続する。In this step, the electrode pad 45 of the semiconductor element 410 and the extraction electrode 44 are connected to each other by the bonding wires 46 by ball bonding.

【００２５】半導体素子４１０の表面には前述した第１
の工程でアルミ電極パッド４５が形成されており、電極
パッド４５と取り出し電極４４とが、ボンディングワイ
ヤ４６によって電気接続される。電極パッド４５側に１
ｓｔボンド、取り出し電極４４側に２ｎｄボンドが打た
れる。バイポーラトランジスタで有れば、取り出し電極
４４はそれぞれエミッタとベースに対応し、パワーＭＯ
ＳＦＥＴで有れば、ソースとゲートに対応する。On the surface of the semiconductor element 410, the first
In this step, the aluminum electrode pad 45 is formed, and the electrode pad 45 and the extraction electrode 44 are electrically connected by the bonding wire 46. 1 on the electrode pad 45 side
A st bond and a second bond are formed on the extraction electrode 44 side. If the transistor is a bipolar transistor, the extraction electrodes 44 correspond to the emitter and the base, respectively,
If it is an SFET, it corresponds to the source and the gate.

【００２６】本発明の第６の工程は、図７に示す如く、
半導体素子４１０を含みシリコン基板４０表面を絶縁性
樹脂４７で被覆することにある。In the sixth step of the present invention, as shown in FIG.
The surface of the silicon substrate 40 including the semiconductor element 410 is covered with the insulating resin 47.

【００２７】本工程では、シリコン基板４０の上方に移
送したディスペンサ（図示せず）から所定量のエポキシ
系液体樹脂を滴下（ポッティング）し、すべての半導体
素子４１０を共通の樹脂層４７で被覆する。前記液体樹
脂として例えばＣＶ５７６ＡＮ（松下電工製）を用い
た。滴下した液体樹脂は比較的粘性が高く、表面張力を
有しているので、その表面が湾曲する。樹脂層４７の湾
曲した表面を平坦面に加工するには、樹脂が硬化する前
に平坦な成形部材を押圧して平坦面に加工する手法と、
滴下した樹脂層４７を１００〜２００度、数時間の熱処
理（キュア）にて硬化させた後に、湾曲面を例えばダイ
シングブレードで研削することによって平坦面に加工す
る手法とが考えられる。In this step, a predetermined amount of epoxy liquid resin is dropped (potted) from a dispenser (not shown) transferred above the silicon substrate 40, and all the semiconductor elements 410 are covered with the common resin layer 47. . For example, CV576AN (manufactured by Matsushita Electric Works) was used as the liquid resin. Since the dropped liquid resin has relatively high viscosity and surface tension, its surface is curved. In order to process the curved surface of the resin layer 47 into a flat surface, a method of pressing a flat molded member before the resin is cured to process the flat surface into a flat surface,
A method may be considered in which, after the dropped resin layer 47 is cured by heat treatment (curing) at 100 to 200 degrees for several hours, the curved surface is processed into a flat surface by grinding with a dicing blade, for example.

【００２８】本発明の第７の工程は、図８に示す如く、
シリコン基板４０を裏面より除去して取り出し電極４４
の裏面を露出することにある。In the seventh step of the present invention, as shown in FIG.
The silicon substrate 40 is removed from the back surface and the extraction electrode 44
Is to expose the back surface.

【００２９】本工程は本発明の特徴とするものであり、
シリコン基板４０を裏面より研削する。シリコン基板４
０は約４００μｍの厚み有するので、大部分をバックグ
ラインドにより機械的に研削し、残りの１０〜２０μｍ
をスピンエッチングにより化学的に除去して、約１００
μｍの厚みまで研削される。シリコン基板４０の表面は
樹脂層４７で被覆されているので、樹脂層４７の持つ機
械的強度でシリコン基板４０が割れることはない。この
結果、取り出し電極４４の裏面が樹脂層４７の裏面側に
露出される。このとき酸化膜４３は取り出し電極４４の
電気的絶縁材として働いている。This step is a feature of the present invention.
The silicon substrate 40 is ground from the back. Silicon substrate 4
0 has a thickness of about 400 μm, so most of it is mechanically ground by back grinding and the remaining 10 to 20 μm
Is chemically removed by spin etching to obtain about 100
It is ground to a thickness of μm. Since the surface of the silicon substrate 40 is covered with the resin layer 47, the silicon substrate 40 does not break due to the mechanical strength of the resin layer 47. As a result, the back surface of the extraction electrode 44 is exposed on the back surface side of the resin layer 47. At this time, the oxide film 43 functions as an electrical insulating material for the extraction electrode 44.

【００３０】本発明の第８の工程は、図９に示す如く、
シリコン基板４０の裏面に露出された素子形成領域４１
および取り出し電極４４に接続電極４８を形成すること
にある。In the eighth step of the present invention, as shown in FIG.
Element forming region 41 exposed on the back surface of silicon substrate 40
And forming the connection electrode 48 on the extraction electrode 44.

【００３１】本工程では、シリコン基板４０の露出され
た裏面にシリコン酸化膜あるいはシリコン窒化膜、ＰＩ
Ｘ、ＳＯＧ等の保護膜４８をＣＶＤ法あるいはスピンオ
ンにより形成し、シリコン基板４０の裏面全面を覆う。
続いて素子形成領域４１および取り出し電極４４上に選
択エッチングによりコンタクト孔を設け、金等の導電性
金属をスパッター等で付着した後に所望の形状にエッチ
ングして接続電極４９を形成する。接続電極４９ａは素
子形成領域４１とオーミック接触しコレクタ電極として
働き、接続電極４９ｂはエミッタおよびベース電極とし
て働く。In this step, a silicon oxide film or a silicon nitride film, a PI
A protective film 48 of X, SOG, or the like is formed by a CVD method or spin-on, and covers the entire back surface of the silicon substrate 40.
Subsequently, a contact hole is formed by selective etching on the element formation region 41 and the extraction electrode 44, and a conductive metal such as gold is attached by sputtering or the like, and then etched into a desired shape to form a connection electrode 49. The connection electrode 49a makes ohmic contact with the element formation region 41 and functions as a collector electrode, and the connection electrode 49b functions as an emitter and a base electrode.

【００３２】本発明の最終工程は、図１０に示す如く、
絶縁性樹脂４７をダイシングして個別の半導体素子４１
０に分離することにある。The final step of the present invention is as shown in FIG.
Dicing the insulating resin 47 to separate the individual semiconductor elements 41
It is to be separated into zero.

【００３３】本工程では、半導体素子４１０毎に樹脂層
４７とシリコン基板４０を切断して各々の半導体素子４
１０に分離する。切断にはダイシング装置を用い、点線
で示すダイシングライン５０に沿って樹脂層４７とシリ
コン基板４０とをダイシングブレード５１で同時に切断
することにより、半導体素子４１０毎に分割した半導体
装置を形成する。ダイシング工程においてはシリコン基
板４０の裏面側にブルーシート（たとえば、商品名：Ｕ
Ｖシート、リンテック株式会社製）を貼り付け、前記ダ
イシングブレードがブルーシートの表面に到達するよう
な切削深さで切断する。In this step, the resin layer 47 and the silicon substrate 40 are cut for each semiconductor element 410 so that each semiconductor element 4
Separate into 10. The dicing device is used for the cutting, and the resin layer 47 and the silicon substrate 40 are simultaneously cut by the dicing blade 51 along the dicing line 50 shown by the dotted line, thereby forming a semiconductor device divided for each semiconductor element 410. In the dicing step, a blue sheet (for example, product name: U
V sheet, manufactured by Lintec Corporation), and cut at a cutting depth such that the dicing blade reaches the surface of the blue sheet.

【００３４】[0034]

【発明の効果】以上に説明したように、本発明によれ
ば、リードフレームを用いた半導体装置よりも更に小型
化できるパッケージ構造を提供できる利点を有する。こ
のとき、リード端子が突出しない構造であるので、実装
したときの占有面積を低減し、高密度実装を実現でき
る。As described above, according to the present invention, there is an advantage that it is possible to provide a package structure that can be further reduced in size than a semiconductor device using a lead frame. At this time, since the structure is such that the lead terminals do not project, the occupied area when mounting is reduced, and high-density mounting can be realized.

【００３５】また、半導体素子を形成するシリコン基板
に直接取り出し電極を形成するので、従来のようにセラ
ミック基板を用いる必要もなく、且つ半導体素子を他の
マウント部材に固着することも不要となり大幅にコスト
を削減できる。Further, since the extraction electrode is formed directly on the silicon substrate on which the semiconductor element is to be formed, it is not necessary to use a ceramic substrate as in the prior art, and it is not necessary to fix the semiconductor element to another mounting member. Costs can be reduced.

【００３６】更に、シリコン基板は既存の設備で加工が
でき、新たな設備が不要である。シリコン基板も前工程
で処理できるので、後工程がなくなり、リードタイムを
大幅に短縮できる。Further, the silicon substrate can be processed by existing equipment, and no new equipment is required. Since the silicon substrate can be processed in the preceding process, the subsequent process is eliminated, and the lead time can be greatly reduced.

【００３７】更に、ビアホールが不要となるので、スル
ーホール工程を全面的に排除でき、大幅な工程短縮がで
きる。Further, since no via hole is required, the through-hole process can be entirely eliminated, and the process can be greatly reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明を説明するための断面図である。FIG. 1 is a cross-sectional view for explaining the present invention.

【図２】本発明を説明するための断面図である。FIG. 2 is a cross-sectional view for explaining the present invention.

【図３】本発明を説明するための断面図である。FIG. 3 is a cross-sectional view for explaining the present invention.

【図４】本発明を説明するための断面図である。FIG. 4 is a cross-sectional view for explaining the present invention.

【図５】本発明を説明するための断面図である。FIG. 5 is a cross-sectional view for explaining the present invention.

【図６】本発明を説明するための断面図である。FIG. 6 is a cross-sectional view for explaining the present invention.

【図７】本発明を説明するための断面図である。FIG. 7 is a cross-sectional view for explaining the present invention.

【図８】本発明を説明するための断面図である。FIG. 8 is a cross-sectional view for explaining the present invention.

【図９】本発明を説明するための断面図である。FIG. 9 is a cross-sectional view for explaining the present invention.

【図１０】本発明を説明するための平面図である。FIG. 10 is a plan view for explaining the present invention.

【図１１】従来例を説明するための断面図である。FIG. 11 is a cross-sectional view for explaining a conventional example.

【図１２】従来例を説明するための図である。FIG. 12 is a diagram for explaining a conventional example.

【図１３】他の従来例を説明するための図である。FIG. 13 is a diagram for explaining another conventional example.

フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 23/48 Ｈ０１Ｌ 23/12 Ｌ Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat II (reference) H01L 23/48 H01L 23/12 L

Claims (5)

【特許請求の範囲】[Claims] 【請求項１】 シリコン基板の予定の素子形成領域に半
導体素子を形成する工程と、 前記シリコン基板の前記素子形成領域の外側に位置し予
定の取り出し電極となる部分にトレンチ溝を形成する工
程と、 前記トレンチ溝の少なくとも側面および底面に酸化膜を
形成した後、前記トレンチ溝の底面の前記酸化膜を除去
する工程と、 前記トレンチ溝に埋め込まれた導電性金属よりなる取り
出し電極を形成する工程と、 前記半導体素子の電極と前記取り出し電極とを電気的に
接続する工程と、 前記シリコン基板表面を絶縁性樹脂で被覆する工程と、 前記シリコン基板を裏面より除去して前記取り出し電極
の裏面を露出する工程と、 前記絶縁性樹脂をダイシングして個別の半導体素子に分
離する工程とを具備することを特徴とする半導体装置の
製造方法。A step of forming a semiconductor element in a predetermined element formation region of a silicon substrate; and a step of forming a trench in a portion of the silicon substrate located outside the element formation region and serving as a predetermined extraction electrode. Forming an oxide film on at least a side surface and a bottom surface of the trench groove, removing the oxide film on the bottom surface of the trench groove; and forming an extraction electrode made of a conductive metal embedded in the trench groove. Electrically connecting the electrode of the semiconductor element and the extraction electrode; coating the surface of the silicon substrate with an insulating resin; removing the silicon substrate from the back surface to remove the back surface of the extraction electrode. Exposing the insulating resin, and dicing the insulating resin into individual semiconductor elements. Method. 【請求項２】 前記シリコン基板の裏面に露出された前
記素子形成領域および前記取り出し電極に接続電極を形
成する工程を含むことを特徴とする請求項１に記載の半
導体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a connection electrode on the element formation region exposed on the back surface of the silicon substrate and the extraction electrode. 【請求項３】 前記導電性金属は金あるいは銅のメッキ
で形成されることを特徴とする請求項１に記載の半導体
装置の製造方法。3. The method according to claim 1, wherein the conductive metal is formed by plating gold or copper. 【請求項４】 前記半導体素子の電極と前記取り出し電
極とはボンデイングワイヤーで接続されることを特徴と
する請求項１に記載の半導体装置の製造方法。4. The method according to claim 1, wherein the electrode of the semiconductor element and the extraction electrode are connected by a bonding wire. 【請求項５】 前記シリコン基板は裏面より研削により
除去されることを特徴とする請求項１に記載の半導体装
置の製造方法。5. The method according to claim 1, wherein the silicon substrate is removed from a back surface by grinding.
JP2000137480A 2000-05-10 2000-05-10 Manufacturing method of semiconductor device Expired - Fee Related JP3744772B2 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009253239A (en) * 2008-04-11 2009-10-29 Denso Corp Semiconductor device and method of manufacturing the same
JP2010010491A (en) * 2008-06-27 2010-01-14 Jsr Corp Structure with insulating film and method of manufacturing the same, resin composition, and electronic component

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009253239A (en) * 2008-04-11 2009-10-29 Denso Corp Semiconductor device and method of manufacturing the same
JP2010010491A (en) * 2008-06-27 2010-01-14 Jsr Corp Structure with insulating film and method of manufacturing the same, resin composition, and electronic component

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